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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tK2JuPQn1FsTQvOSXTmzoSioHEObeRnPn/IZGYT5//s=; b=NPXQ1L7XhaSTNyDC8uBHT7qyJIKdenNofc5lNCeO5yTWo2ez7/twf0Pgz86H4aqH2D 27kTC/20olz+tqhhOsLmDc3wcUB/EYc9NkFtneVGJ+HnS8hZ43JciG+UmWYTzDg+p+0n lBvg50y7kSJBmGn0nCb51pCsIqnFBOi8MUk7eNZnGzWSEzA/EEaQIgcAxXXvrgPo/fel RVX47FmN9Ta5cX6aCxV1HwLV3sWRVYA9wbuRfmFhl80TBK98OfKQNCj6dS7ySwIuLvtP KTn/8UcjhJkA5RBw+JZKyXYF6NQDXCVKWnknavU9aAdaYvGVFlP/BXuXEzTnyQltDzb2 DyuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tK2JuPQn1FsTQvOSXTmzoSioHEObeRnPn/IZGYT5//s=; b=SELrB3D3umr+WrW4KNUE9iEsRmkqLFCUGRIPFPnBSDA5EnKRe9TH+S/jIhvZtJ+Pj6 BB/xcb16BMTbwppqRzhrAEXPgKklndvRTWKYi3LwwxLncEt3wDAlZL9IScAh6myH8pXU ZsCEjDIbDE0BmxQb/sVEHZW5QWv+fYa9wfwwTigJl/z57klvGzpToex3XygTcX4XDUrr 51/Vzy5b8nIM94s+r82GQ1ao5wums61FLclcVHO8GKbfRE+lk5q4H+bpWfGCF7UMjVil he7T4BCsAUDm616DZAtstDl8/EaDrkN0RuHF2QyRZlUQZNFBzMxW/vFiP2Y8sI524Ft5 I42g== X-Gm-Message-State: AOAM531yx6VSQa4xBcD3nfmvMcIr4142FlJ2PBrrL3lkt1GdnJIITAgS 9XHgp8gMwTn6stllxsI7X336M05iHyu3uQ== X-Google-Smtp-Source: ABdhPJzYveAkUusbnAI6g1vLX8f9njg+ivdscTUeLNxyN2bx1AuxB8YWBhe7L1icXi30YZteAqxlkQ== X-Received: by 2002:adf:ebc9:: with SMTP id v9mr24182869wrn.387.1615224797298; Mon, 08 Mar 2021 09:33:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/54] hw/arm/mps2-tz: Add new mps3-an547 board Date: Mon, 8 Mar 2021 17:32:32 +0000 Message-Id: <20210308173244.20710-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Add support for the mps3-an547 board; this is an SSE-300 based FPGA image that runs on the MPS3. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-43-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 146 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 144 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 0a1e6c20c21..3fbe3d29f95 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -17,6 +17,7 @@ * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524 + * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN= 547 * * Links to the TRM for the board itself and to the various Application * Notes which document the FPGA images can be found here: @@ -30,6 +31,8 @@ * https://developer.arm.com/documentation/dai0521/latest/ * Application Note AN524: * https://developer.arm.com/documentation/dai0524/latest/ + * Application Note AN547: + * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI05= 47B_SSE300_PLUS_U55_FPGA_for_mps3.pdf * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Gu= ide * (ARM ECM0601256) for the details of some of the device layout: @@ -37,6 +40,8 @@ * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM def= ines * most of the device layout: * https://developer.arm.com/documentation/101104/latest/ + * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM: + * https://developer.arm.com/documentation/101773/latest/ */ =20 #include "qemu/osdep.h" @@ -68,13 +73,14 @@ #include "hw/qdev-clock.h" #include "qom/object.h" =20 -#define MPS2TZ_NUMIRQ_MAX 95 -#define MPS2TZ_RAM_MAX 4 +#define MPS2TZ_NUMIRQ_MAX 96 +#define MPS2TZ_RAM_MAX 5 =20 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, FPGA_AN524, + FPGA_AN547, } MPS2TZFPGAType; =20 /* @@ -153,6 +159,7 @@ struct MPS2TZMachineState { #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") #define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") +#define TYPE_MPS3TZ_AN547_MACHINE MACHINE_TYPE_NAME("mps3-an547") =20 OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) =20 @@ -252,6 +259,49 @@ static const RAMInfo an524_raminfo[] =3D { { }, }; =20 +static const RAMInfo an547_raminfo[] =3D { { + .name =3D "itcm", + .base =3D 0x00000000, + .size =3D 512 * KiB, + .mpc =3D -1, + .mrindex =3D 0, + }, { + .name =3D "sram", + .base =3D 0x01000000, + .size =3D 2 * MiB, + .mpc =3D 0, + .mrindex =3D 1, + }, { + .name =3D "dtcm", + .base =3D 0x20000000, + .size =3D 4 * 128 * KiB, + .mpc =3D -1, + .mrindex =3D 2, + }, { + .name =3D "sram 2", + .base =3D 0x21000000, + .size =3D 4 * MiB, + .mpc =3D -1, + .mrindex =3D 3, + }, { + /* We don't model QSPI flash yet; for now expose it as simple ROM = */ + .name =3D "QSPI", + .base =3D 0x28000000, + .size =3D 8 * MiB, + .mpc =3D 1, + .mrindex =3D 4, + .flags =3D IS_ROM, + }, { + .name =3D "DDR", + .base =3D 0x60000000, + .size =3D MPS3_DDR_SIZE, + .mpc =3D 2, + .mrindex =3D -1, + }, { + .name =3D NULL, + }, +}; + static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mp= c) { MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); @@ -893,6 +943,55 @@ static void mps2tz_common_init(MachineState *machine) }, }; =20 + const PPCInfo an547_ppcs[] =3D { { + .name =3D "apb_ppcexp0", + .ports =3D { + { "ssram-mpc", make_mpc, &mms->mpc[0], 0x57000000, 0x1000 = }, + { "qspi-mpc", make_mpc, &mms->mpc[1], 0x57001000, 0x1000 }, + { "ddr-mpc", make_mpc, &mms->mpc[2], 0x57002000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp1", + .ports =3D { + { "i2c0", make_i2c, &mms->i2c[0], 0x49200000, 0x1000 }, + { "i2c1", make_i2c, &mms->i2c[1], 0x49201000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x49202000, 0x1000, { 53= } }, + { "spi1", make_spi, &mms->spi[1], 0x49203000, 0x1000, { 54= } }, + { "spi2", make_spi, &mms->spi[2], 0x49204000, 0x1000, { 55= } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x49205000, 0x1000 }, + { "i2c3", make_i2c, &mms->i2c[3], 0x49206000, 0x1000 }, + { /* port 7 reserved */ }, + { "i2c4", make_i2c, &mms->i2c[4], 0x49208000, 0x1000 }, + }, + }, { + .name =3D "apb_ppcexp2", + .ports =3D { + { "scc", make_scc, &mms->scc, 0x49300000, 0x1000 }, + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, 0x49301000= , 0x1000 }, + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x49302000, 0x1000 = }, + { "uart0", make_uart, &mms->uart[0], 0x49303000, 0x1000, {= 33, 34, 43 } }, + { "uart1", make_uart, &mms->uart[1], 0x49304000, 0x1000, {= 35, 36, 44 } }, + { "uart2", make_uart, &mms->uart[2], 0x49305000, 0x1000, {= 37, 38, 45 } }, + { "uart3", make_uart, &mms->uart[3], 0x49306000, 0x1000, {= 39, 40, 46 } }, + { "uart4", make_uart, &mms->uart[4], 0x49307000, 0x1000, {= 41, 42, 47 } }, + { "uart5", make_uart, &mms->uart[5], 0x49308000, 0x1000, {= 125, 126, 127 } }, + + { /* port 9 reserved */ }, + { "clcd", make_unimp_dev, &mms->cldc, 0x4930a000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x4930b000, 0x1000 }, + }, + }, { + .name =3D "ahb_ppcexp0", + .ports =3D { + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x10= 00 }, + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x10= 00 }, + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x10= 00 }, + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x10= 00 }, + { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 4= 9 } }, + }, + }, + }; + switch (mmc->fpga_type) { case FPGA_AN505: case FPGA_AN521: @@ -903,6 +1002,10 @@ static void mps2tz_common_init(MachineState *machine) ppcs =3D an524_ppcs; num_ppcs =3D ARRAY_SIZE(an524_ppcs); break; + case FPGA_AN547: + ppcs =3D an547_ppcs; + num_ppcs =3D ARRAY_SIZE(an547_ppcs); + break; default: g_assert_not_reached(); } @@ -981,6 +1084,11 @@ static void mps2tz_common_init(MachineState *machine) =20 create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); =20 + if (mmc->fpga_type =3D=3D FPGA_AN547) { + create_unimplemented_device("U55 timing adapter 0", 0x48102000, 0x= 1000); + create_unimplemented_device("U55 timing adapter 1", 0x48103000, 0x= 1000); + } + create_non_mpc_ram(mms); =20 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, @@ -1115,6 +1223,33 @@ static void mps3tz_an524_class_init(ObjectClass *oc,= void *data) mps2tz_set_default_ram_info(mmc); } =20 +static void mps3tz_an547_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS3 with AN547 FPGA image for Cortex-M55"; + mc->default_cpus =3D 1; + mc->min_cpus =3D mc->default_cpus; + mc->max_cpus =3D mc->default_cpus; + mmc->fpga_type =3D FPGA_AN547; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m55"); + mmc->scc_id =3D 0x41055470; + mmc->sysclk_frq =3D 32 * 1000 * 1000; /* 32MHz */ + mmc->apb_periph_frq =3D 25 * 1000 * 1000; /* 25MHz */ + mmc->oscclk =3D an524_oscclk; /* same as AN524 */ + mmc->len_oscclk =3D ARRAY_SIZE(an524_oscclk); + mmc->fpgaio_num_leds =3D 10; + mmc->fpgaio_has_switches =3D true; + mmc->fpgaio_has_dbgctrl =3D true; + mmc->numirq =3D 96; + mmc->uart_overflow_irq =3D 48; + mmc->init_svtor =3D 0x00000000; + mmc->raminfo =3D an547_raminfo; + mmc->armsse_type =3D TYPE_SSE300; + mps2tz_set_default_ram_info(mmc); +} + static const TypeInfo mps2tz_info =3D { .name =3D TYPE_MPS2TZ_MACHINE, .parent =3D TYPE_MACHINE, @@ -1146,12 +1281,19 @@ static const TypeInfo mps3tz_an524_info =3D { .class_init =3D mps3tz_an524_class_init, }; =20 +static const TypeInfo mps3tz_an547_info =3D { + .name =3D TYPE_MPS3TZ_AN547_MACHINE, + .parent =3D TYPE_MPS2TZ_MACHINE, + .class_init =3D mps3tz_an547_class_init, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); type_register_static(&mps2tz_an505_info); type_register_static(&mps2tz_an521_info); type_register_static(&mps3tz_an524_info); + type_register_static(&mps3tz_an547_info); } =20 type_init(mps2tz_machine_init); --=20 2.20.1