From nobody Tue Apr 15 11:36:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615227793; cv=none; d=zohomail.com; s=zohoarc; b=b5s9+AOVwYrswqchl8z/zXDCHlipK0vUH2iEfOSCa7fLHh870M/G7oaeCAmQU+vIkWXuMyRMK9vjOgvhxZPKSnxk8x+W34CrgwGHo+YCFLmMyBctB/xDPp7nUTcXc+O8U49qCVDV3jfdm+z6QoYQUTZek7OhzCsGgo/0io6/NyE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615227793; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=s8SBcSOsjvWWNhiZ70AknwQvWC389VYvd68bkS2XFfk=; b=OAq9V1/uKWPOxWD4gj/KDw0RTfnShsYfqLlNp2Vf4LXjMgbFENznu2bkJpfX2HZf/LgRAV19CW/FYR/XftlUA+muBLzrU+mXf05+DztG6s6dRDUfvEeNfAB3f+18v2Nev1NxXKtzGUI7DUqHmlgEQFPk4Nbksc2QLXoQl+3T67Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615227793055155.65895038900544; Mon, 8 Mar 2021 10:23:13 -0800 (PST) Received: from localhost ([::1]:34028 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJKX9-0005VP-V0 for importer@patchew.org; Mon, 08 Mar 2021 13:23:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJJl9-0007CG-Dv for qemu-devel@nongnu.org; Mon, 08 Mar 2021 12:33:35 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:38800) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lJJko-00077V-KQ for qemu-devel@nongnu.org; Mon, 08 Mar 2021 12:33:35 -0500 Received: by mail-wr1-x42b.google.com with SMTP id d15so12343403wrv.5 for ; Mon, 08 Mar 2021 09:33:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=s8SBcSOsjvWWNhiZ70AknwQvWC389VYvd68bkS2XFfk=; b=DjTMPMHbke5Cjvtzg1Elp2IjsyxrHqAKTrgIEuo1vy7jbd+aLWMd1HR7vX0L6GiDgv 8xWnWeV12AwtkPqZYNIs6s9krpfEJnsH2vjvXSYm02Ok80Sg0mx68D1nMg8hkv6s0vZC 9T4M14GKWSbruNJbXZAuv0hZDTRhmYgasGIhSsJ9gxEpvdb+xoBuV/ojfic0vhtnn9Tv WoeEKJcBUq7RrEgCTWHVJ6sIeCDepiIbE9w4YM+tkDYWcfnUXPqx8WjowHzxjGad4lfo C2OpNWgHhCzyHj6wZ+HDKAuU/sEsoJri0y8h+2b0h/EbWsCh+373tDs8OKq0YbY2FlNK q4MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s8SBcSOsjvWWNhiZ70AknwQvWC389VYvd68bkS2XFfk=; b=NwJsu4MsnlOR3yMKFLZ5xcmHLo7x19LHiMRNFNXJxCPUL54hqKZ5EP1MvfAzWITdRs N0lCljYwMg7EiOrvm+Qk3lBGY8kczdDJzCQEfQb1iuMox0YsyWoV7xwtbGN+jI3sx3NR tPnsG7FGA/cRtQ44B1vc19q2KSMzPij23MBYCE0ozNfx3nm55MGnnqcsBL73ZRAm2fqt aXSHkUoOqDbCyqO+huZVT8QfEW5fV+qhbk3qYEFgJPaeskeZw9bM5ursShYjncy4Wzf6 rgH/U4ZQCQvjNQ5fCZcMJbZK8ncAHDu7SS6NOe3Mn2mMrRii5bEwggZZJaAuVMo7o+T9 n++A== X-Gm-Message-State: AOAM533LLGnIMLWC79kL+IB1aEHPsA+51BdXbcKAq4mbVBroDidWXGei cZZIXxudjMRH17tMM7hBdTkDcoeZ04uksw== X-Google-Smtp-Source: ABdhPJykUxvJ0WiqxvnWC7KCr8g8QuAkfnXuqVhynnWRckSOVleA1j0R1jrAtbuUOrcLuZYBtoD9uA== X-Received: by 2002:adf:ec46:: with SMTP id w6mr23611654wrn.213.1615224792299; Mon, 08 Mar 2021 09:33:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/54] hw/arm/armsse: Add SSE-300 support Date: Mon, 8 Mar 2021 17:32:25 +0000 Message-Id: <20210308173244.20710-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Now we have sufficiently parameterised the code, we can add SSE-300 support by adding a new entry to the armsse_variants[] array. Note that the main watchdog (unlike the s32k watchdog) in the SSE-300 is a different device from the CMSDK watchdog; we don't have a model of it so we leave it as a TYPE_UNIMPLEMENTED_DEVICE stub. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-36-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 1 + hw/arm/armsse.c | 152 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 21d239c381c..36592be62c5 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -123,6 +123,7 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, */ #define TYPE_IOTKIT "iotkit" #define TYPE_SSE200 "sse-200" +#define TYPE_SSE300 "sse-300" =20 /* We have an IRQ splitter and an OR gate input for each external PPC * and the 2 internal PPCs diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2366c49376d..e5aeb9e485f 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -337,6 +337,128 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { } }; =20 +static const ARMSSEDeviceInfo sse300_devices[] =3D { + { + .name =3D "timer0", + .type =3D TYPE_SSE_TIMER, + .index =3D 0, + .addr =3D 0x48000000, + .ppc =3D 0, + .ppc_port =3D 0, + .irq =3D 3, + }, + { + .name =3D "timer1", + .type =3D TYPE_SSE_TIMER, + .index =3D 1, + .addr =3D 0x48001000, + .ppc =3D 0, + .ppc_port =3D 1, + .irq =3D 4, + }, + { + .name =3D "timer2", + .type =3D TYPE_SSE_TIMER, + .index =3D 2, + .addr =3D 0x48002000, + .ppc =3D 0, + .ppc_port =3D 2, + .irq =3D 5, + }, + { + .name =3D "timer3", + .type =3D TYPE_SSE_TIMER, + .index =3D 3, + .addr =3D 0x48003000, + .ppc =3D 0, + .ppc_port =3D 5, + .irq =3D 27, + }, + { + .name =3D "s32ktimer", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 0, + .addr =3D 0x4802f000, + .ppc =3D 1, + .ppc_port =3D 0, + .irq =3D 2, + .slowclk =3D true, + }, + { + .name =3D "s32kwatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 0, + .addr =3D 0x4802e000, + .ppc =3D NO_PPC, + .irq =3D NMI_0, + .slowclk =3D true, + }, + { + .name =3D "watchdog", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 0, + .addr =3D 0x48040000, + .size =3D 0x2000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysinfo", + .type =3D TYPE_IOTKIT_SYSINFO, + .index =3D 0, + .addr =3D 0x48020000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysctl", + .type =3D TYPE_IOTKIT_SYSCTL, + .index =3D 0, + .addr =3D 0x58021000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "SYS_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 1, + .addr =3D 0x58022000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "CPU0CORE_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 2, + .addr =3D 0x50023000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "MGMT_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 3, + .addr =3D 0x50028000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "DEBUG_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 4, + .addr =3D 0x50029000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D NULL, + } +}; + /* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ static const bool sse200_irq_is_common[32] =3D { [0 ... 5] =3D true, @@ -352,6 +474,18 @@ static const bool sse200_irq_is_common[32] =3D { /* 30, 31: reserved */ }; =20 +static const bool sse300_irq_is_common[32] =3D { + [0 ... 5] =3D true, + /* 6, 7: per-CPU MHU interrupts */ + [8 ... 12] =3D true, + /* 13: reserved */ + [14 ... 16] =3D true, + /* 17-25: reserved */ + [26 ... 27] =3D true, + /* 28, 29: per-CPU CTI interrupts */ + /* 30, 31: reserved */ +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -389,6 +523,24 @@ static const ARMSSEInfo armsse_variants[] =3D { .devinfo =3D sse200_devices, .irq_is_common =3D sse200_irq_is_common, }, + { + .name =3D TYPE_SSE300, + .sse_version =3D ARMSSE_SSE300, + .sram_banks =3D 2, + .num_cpus =3D 1, + .sys_version =3D 0x7e00043b, + .iidr =3D 0x74a0043b, + .cpuwait_rst =3D 0, + .has_mhus =3D false, + .has_cachectrl =3D false, + .has_cpusecctrl =3D true, + .has_cpuid =3D true, + .has_cpu_pwrctrl =3D true, + .has_sse_counter =3D true, + .props =3D armsse_properties, + .devinfo =3D sse300_devices, + .irq_is_common =3D sse300_irq_is_common, + }, }; =20 static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info) --=20 2.20.1