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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=W+4bTUyGK28yi6/dxTf2egKfdicu748cNaQiFvA6QJw=; b=QcXiXBTRBEuj/GYCh99rTxcXc7xTqFrYIr8mI5JZIYPfI65gCk4ztNQUYG79CAsITO 4GztoinxBboIT7PXDBsxp6nX6ggM6RkDPJsaKGDym8X4djNXcFQwdXJSsVlEsm7wVGvJ 1CRTQUdTSJMm1zJI4Vco0/iQQpSQtHAw0gO/7BnRbjtXukA5dCT45mEj22A9QmwFeihX dP1bPKVPCmuF2n/WC+xrTIsPMjMWAYZpSf/xODHJ02t50cECzyzDFJuICobCcqPzqY/Q f1XE5YrdvprxPjs4a1T3suTkDiGGtC5G9rNjbXlUk12h2VQMWfWsQGf2vmFGylUWd4WU zRXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W+4bTUyGK28yi6/dxTf2egKfdicu748cNaQiFvA6QJw=; b=m52E/7BYhQ90XWR4m44PyXnC7nWYqVYwta4OdLtQWNQxA59ZKBGkJrKgKzFBqN8FBi ddICQSmB+9hi4jKjSquEB4QiRvBL3WR1PsyiSRTE872pduL9j4G4l8nMAgXwcXQSgOB3 tq32FCnfhwXIWhavMfDtQQtIqjlehbhkcCrIAW6On1CWUwywq2iKjETj9GuHuGxjRqG9 IAh1tA+0VF/r7nJAmd/M8fiTj1a1CZyNDbGR6b1T3iMxh/8lLoGF8d0RCMoLK0dDcJNg roNJCfUT4xe88ZSp6Kznqcq2m9QzASpum8F6SbXe8LIpxuawT2rUQgX/UmuPeGDNykWy KvdQ== X-Gm-Message-State: AOAM530NNIdxphY0QpvvKI02eo3ibn1IN6YZjZgtgsQ79NM6yiss5DOY 4j0/x6C6LKHwYJDseVhtH/61d8oy/bcOLA== X-Google-Smtp-Source: ABdhPJy3WUVtjNepMbw4RptZVf6rrjb+YwOXSI0OTIAv5jncA9I9HGNLLFJOSHAhw3SlySrPPB3nag== X-Received: by 2002:adf:f841:: with SMTP id d1mr23804336wrq.36.1615224791583; Mon, 08 Mar 2021 09:33:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/54] hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block Date: Mon, 8 Mar 2021 17:32:24 +0000 Message-Id: <20210308173244.20710-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register block. Because this block is per-CPU and does not clash with any of the SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the existing has_cachectrl, has_cpusectrl and has_cpuid, rather than trying to add per-CPU-device support to the devinfo array handling code. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-35-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index f4e2b680479..21d239c381c 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -104,6 +104,7 @@ #include "hw/misc/iotkit-sysinfo.h" #include "hw/misc/armsse-cpuid.h" #include "hw/misc/armsse-mhu.h" +#include "hw/misc/armsse-cpu-pwrctrl.h" #include "hw/misc/unimp.h" #include "hw/or-irq.h" #include "hw/clock.h" @@ -179,6 +180,8 @@ struct ARMSSE { =20 ARMSSECPUID cpuid[SSE_MAX_CPUS]; =20 + ARMSSECPUPwrCtrl cpu_pwrctrl[SSE_MAX_CPUS]; + /* * 'container' holds all devices seen by all CPUs. * 'cpu_container[i]' is the view that CPU i has: this has the diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index ec9c30e0996..2366c49376d 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -66,6 +66,7 @@ struct ARMSSEInfo { bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; + bool has_cpu_pwrctrl; bool has_sse_counter; Property *props; const ARMSSEDeviceInfo *devinfo; @@ -364,6 +365,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D false, .has_cpusecctrl =3D false, .has_cpuid =3D false, + .has_cpu_pwrctrl =3D false, .has_sse_counter =3D false, .props =3D iotkit_properties, .devinfo =3D iotkit_devices, @@ -381,6 +383,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D true, .has_cpusecctrl =3D true, .has_cpuid =3D true, + .has_cpu_pwrctrl =3D false, .has_sse_counter =3D false, .props =3D armsse_properties, .devinfo =3D sse200_devices, @@ -660,6 +663,15 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_cpu_pwrctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + char *name =3D g_strdup_printf("cpu_pwrctrl%d", i); + + object_initialize_child(obj, name, &s->cpu_pwrctrl[i], + TYPE_ARMSSE_CPU_PWRCTRL); + g_free(name); + } + } if (info->has_sse_counter) { object_initialize_child(obj, "sse-counter", &s->sse_counter, TYPE_SSE_COUNTER); @@ -1255,6 +1267,8 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * 0x50010000: L1 icache control registers * 0x50011000: CPUSECCTRL (CPU local security control registers) * 0x4001f000 and 0x5001f000: CPU_IDENTITY register block + * The SSE-300 has an extra: + * 0x40012000 and 0x50012000: CPU_PWRCTRL register block */ if (info->has_cachectrl) { for (i =3D 0; i < info->num_cpus; i++) { @@ -1301,6 +1315,18 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, = mr); } } + if (info->has_cpu_pwrctrl) { + for (i =3D 0; i < info->num_cpus; i++) { + MemoryRegion *mr; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), errp))= { + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i= ]), 0); + memory_region_add_subregion(&s->cpu_container[i], 0x40012000, = mr); + } + } =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) { return; --=20 2.20.1