From nobody Tue Apr 15 11:36:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615227503; cv=none; d=zohomail.com; s=zohoarc; b=DP7xU03JnLMyuDQ56x59tL/9C0gABBjzeHyZ+VpVrKYpkM523LPuYIrgTu+CG6l9dG9dqXgOdG6+KLqnqDBmnE3WzXvzGoxyfTX2PosLTxJHgsYYOmUJDcBUY+U1MlFtl2lJ7Adr30UHRDxfG2Ju0EVHxqXO6lLgkpNj8079VQ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615227503; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DX6cXuVeRSa75uk2S077ppA1ZFzIrTOeom78lCCe8Wo=; b=RM1i9Ts9uMy7Bbb2NrWZsb/n/HQU8MMq2+LJ2LK8GpDPkxw/6Ov8tO71ffzY3XhQYfBxUNUQJoj1ob6P4yNqKLgb7bqHuCmNRTtOjMVeBb8kA+SbwdHNIC6dgG1n6E/tI0czhPGO3AMmUDBus1ihTIUVPT1Sw0lVEiqs8JheL58= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615227503619887.7172338067478; Mon, 8 Mar 2021 10:18:23 -0800 (PST) Received: from localhost ([::1]:46314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJKSU-0006bD-7k for importer@patchew.org; Mon, 08 Mar 2021 13:18:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJJl2-00074B-A2 for qemu-devel@nongnu.org; Mon, 08 Mar 2021 12:33:29 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:35484) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lJJkl-00076i-SE for qemu-devel@nongnu.org; Mon, 08 Mar 2021 12:33:28 -0500 Received: by mail-wr1-x42a.google.com with SMTP id l12so12332422wry.2 for ; Mon, 08 Mar 2021 09:33:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DX6cXuVeRSa75uk2S077ppA1ZFzIrTOeom78lCCe8Wo=; b=mkyuJoDlr6t70kg902J81sfWmeN5nKLK/F2T9vLvuFwr0g93iqnZ278r2vV+2hNuch wwaO5xBHUM3LvWMrrFVZhNDI9YRGPl6MZ+7eZwYr/bHonfgiiXPS5ixETQYKUNiRDZ/L gPCx6TJAAAy2wj472yCreJU0XSmehasp29ahyoGGd7wTA4V910Ewm6IldX4Yf+zIq3/z iTur9crKsreS0RNPSlqGMxwIxRkJUiynjij/KOp9RBcx5Fb86+cHhL62SvGYBgrOqXUX C4Nkk+TDGtQpy7HOK1XEhKxWv81hQPbjRs1bjNI90NueK23j+icw108q1bgr0oWeagA6 eSDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DX6cXuVeRSa75uk2S077ppA1ZFzIrTOeom78lCCe8Wo=; b=RgfRz/EBNc2zJSfnwTzu4K3Y8QMv5upPs2W0yR7zZbNP2HYjbiYdoijDoyvOgqKBB1 rb0+X13O9+X7RYXmkwcpYZhXF/JK3U9se4cDH4IRHXakf6wFR9/S+TbF3bit7CW5WzMU avCd5MUbFcZnneFiFg1oV1MhlwovINwobI5YO0wNiBL5JAuEv1iId0e9+wI9s7FqJOmz 0EKgpUb0ZYpUYYJ2fTJPVye/MtGDNDgL9WLoq9sYi3sadxF4tHFDNx8KUNbfLXpZW13/ ELruo2Hd0NhrKml4i3cl9+4mEtUVLFnzhV/bIPIJOh4U6DvwBo/NFY2QmZuMb7Q0TU6e T3yw== X-Gm-Message-State: AOAM532bsx2fDRABjMXuUd35IXlPWwQxQiNdZ6UmIoEpcc9corMaDf4g DzWO+qUzKMSR1xkJpA82/7nq3ezmWPJQlQ== X-Google-Smtp-Source: ABdhPJzwwXkDT/cqbnx6cXJoSohmjzh5b5stctoKoh/svUgNw7etarqAliiXUyP4ZR1XLQ97ZCVtJA== X-Received: by 2002:a5d:65d1:: with SMTP id e17mr24306864wrw.53.1615224790350; Mon, 08 Mar 2021 09:33:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/54] hw/arm/armsse: Add support for SSE variants with a system counter Date: Mon, 8 Mar 2021 17:32:22 +0000 Message-Id: <20210308173244.20710-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The SSE-300 has a system counter device; add support for SSE variants having this device. As with the existing devices like the cache control block, CPUID block, etc, we don't try to make the MMIO addresses configurable. We can do that if and when we need to model a future SSE variant which has the counter in a different location. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-33-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 3 +++ hw/arm/armsse.c | 27 +++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 104ba8d26ec..149f17dfc88 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -97,6 +97,7 @@ #include "hw/misc/tz-mpc.h" #include "hw/timer/cmsdk-apb-timer.h" #include "hw/timer/cmsdk-apb-dualtimer.h" +#include "hw/timer/sse-counter.h" #include "hw/watchdog/cmsdk-apb-watchdog.h" #include "hw/misc/iotkit-sysctl.h" #include "hw/misc/iotkit-sysinfo.h" @@ -164,6 +165,8 @@ struct ARMSSE { =20 CMSDKAPBWatchdog cmsdk_watchdog[3]; =20 + SSECounter sse_counter; + IoTKitSysCtl sysctl; IoTKitSysCtl sysinfo; =20 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index b316fe69571..4387e98376c 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -66,6 +66,7 @@ struct ARMSSEInfo { bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; + bool has_sse_counter; Property *props; const ARMSSEDeviceInfo *devinfo; const bool *irq_is_common; @@ -363,6 +364,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D false, .has_cpusecctrl =3D false, .has_cpuid =3D false, + .has_sse_counter =3D false, .props =3D iotkit_properties, .devinfo =3D iotkit_devices, .irq_is_common =3D sse200_irq_is_common, @@ -379,6 +381,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cachectrl =3D true, .has_cpusecctrl =3D true, .has_cpuid =3D true, + .has_sse_counter =3D false, .props =3D armsse_properties, .devinfo =3D sse200_devices, .irq_is_common =3D sse200_irq_is_common, @@ -652,6 +655,11 @@ static void armsse_init(Object *obj) g_free(name); } } + if (info->has_sse_counter) { + object_initialize_child(obj, "sse-counter", &s->sse_counter, + TYPE_SSE_COUNTER); + } + object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ= ); object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate, TYPE_OR_IRQ); @@ -1000,6 +1008,25 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0, qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI"= , 0)); =20 + /* The SSE-300 has a System Counter / System Timestamp Generator */ + if (info->has_sse_counter) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->sse_counter); + + qdev_connect_clock_in(DEVICE(sbd), "CLK", s->mainclk); + if (!sysbus_realize(sbd, errp)) { + return; + } + /* + * The control frame is only in the Secure region; + * the status frame is in the NS region (and visible in the + * S region via the alias mapping). + */ + memory_region_add_subregion(&s->container, 0x58100000, + sysbus_mmio_get_region(sbd, 0)); + memory_region_add_subregion(&s->container, 0x48101000, + sysbus_mmio_get_region(sbd, 1)); + } + /* Devices behind APB PPC0: * 0x40000000: timer0 * 0x40001000: timer1 --=20 2.20.1