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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DDSbQDL/L3ru6cleh08/WLnDS9XnQiEkjmymXTHld8I=; b=tE+K7KRb/EQ57M4tZApqj7CI2hdrMHQeTsrXChPmjdrQ0mvtMlIopzzfm8aaHWIK2q b9Hvg6KU9OT210j6wIpc0Qtx1aEbfkJtWR0s/+g33bBbuDHLEo1YTpzaPBye1LqPVTnv 3Xs15gJYT6DfOheHbmIa4G3uAsbaCxeyxB9yDQKdfQ4/wj8vqn172dEG/K5cfC5/oGoP 4E6M17mgkiNh1DDHTIO0Kc+slnAGSmzMQ05BLLHPKvV8imPRIojLlT9p970QeMssAPsX KNQstXsZnmQ+6keTiFOsyPnv8tkiKKVf8WX8SOBPhJtctanFM8e2ZB/d+hHYvi8W9tDg Ry0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DDSbQDL/L3ru6cleh08/WLnDS9XnQiEkjmymXTHld8I=; b=CAMpXFrCwM6+R13azM1cxvuBZmoi62ge4bYHX0/ovftW+76q2G8KCDtkQTyWZna58O eeJyofos1q4kPNcGzAc+5wU+bo4cTOER6Oe8uDZsuRJHhM/NUZkWczK1UtiJm4s1M+e2 k0/kxpDAuhvcGyCk7V9jYcdoKiuGo70YW6rIaCacpYqCpelWwNeJjOZa9RUKESz7hrfV CAggrZSmU5+twxWWKqJ/x1M3I84w60OiboxXQ7o3ndohyyQQrohOPBoPtByuBqO7FhDq JW1cyCYKneA6JhcwkPtshiN2y39dXrBj8fkRBZ4txDMJnOQOE5LmorEQhqueT/AKIsOe 3Vcg== X-Gm-Message-State: AOAM532Rv8TkKTms2OJYhCX3deJcW8AR6bvQYuVIikTdBpBA6a5gyzv2 hmkxqQoNKc/KcvRVKGb0LPuzC8tEQhA8XQ== X-Google-Smtp-Source: ABdhPJwnQEu56ZnmWaE8jBTSAiYtJpcw9zYgAhLzqrLVGBlYbm+xDdA0JzHMDXyH04+pNvHyvUVydA== X-Received: by 2002:a1c:a958:: with SMTP id s85mr22558126wme.138.1615224789677; Mon, 08 Mar 2021 09:33:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/54] hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo Date: Mon, 8 Mar 2021 17:32:21 +0000 Message-Id: <20210308173244.20710-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The SSE-300 has a slightly different set of shared-per-CPU interrupts, allow the irq_is_common[] array to be different per SSE variant. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-32-peter.maydell@linaro.org --- hw/arm/armsse.c | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index f43f0524e28..b316fe69571 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -68,6 +68,7 @@ struct ARMSSEInfo { bool has_cpuid; Property *props; const ARMSSEDeviceInfo *devinfo; + const bool *irq_is_common; }; =20 static Property iotkit_properties[] =3D { @@ -334,6 +335,21 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { } }; =20 +/* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ +static const bool sse200_irq_is_common[32] =3D { + [0 ... 5] =3D true, + /* 6, 7: per-CPU MHU interrupts */ + [8 ... 12] =3D true, + /* 13: per-CPU icache interrupt */ + /* 14: reserved */ + [15 ... 20] =3D true, + /* 21: reserved */ + [22 ... 26] =3D true, + /* 27: reserved */ + /* 28, 29: per-CPU CTI interrupts */ + /* 30, 31: reserved */ +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -349,6 +365,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpuid =3D false, .props =3D iotkit_properties, .devinfo =3D iotkit_devices, + .irq_is_common =3D sse200_irq_is_common, }, { .name =3D TYPE_SSE200, @@ -364,6 +381,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpuid =3D true, .props =3D armsse_properties, .devinfo =3D sse200_devices, + .irq_is_common =3D sse200_irq_is_common, }, }; =20 @@ -404,21 +422,6 @@ static uint32_t armsse_sys_config_value(ARMSSE *s, con= st ARMSSEInfo *info) /* Clock frequency in HZ of the 32KHz "slow clock" */ #define S32KCLK (32 * 1000) =20 -/* Is internal IRQ n shared between CPUs in a multi-core SSE ? */ -static bool irq_is_common[32] =3D { - [0 ... 5] =3D true, - /* 6, 7: per-CPU MHU interrupts */ - [8 ... 12] =3D true, - /* 13: per-CPU icache interrupt */ - /* 14: reserved */ - [15 ... 20] =3D true, - /* 21: reserved */ - [22 ... 26] =3D true, - /* 27: reserved */ - /* 28, 29: per-CPU CTI interrupts */ - /* 30, 31: reserved */ -}; - /* * Create an alias region in @container of @size bytes starting at @base * which mirrors the memory starting at @orig. @@ -663,7 +666,7 @@ static void armsse_init(Object *obj) } if (info->num_cpus > 1) { for (i =3D 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { - if (irq_is_common[i]) { + if (info->irq_is_common[i]) { char *name =3D g_strdup_printf("cpu-irq-splitter%d", i); SplitIRQ *splitter =3D &s->cpu_irq_splitter[i]; =20 @@ -696,7 +699,7 @@ static qemu_irq armsse_get_common_irq_in(ARMSSE *s, int= irqno) ARMSSEClass *asc =3D ARM_SSE_GET_CLASS(s); const ARMSSEInfo *info =3D asc->info; =20 - assert(irq_is_common[irqno]); + assert(info->irq_is_common[irqno]); =20 if (info->num_cpus =3D=3D 1) { /* Only one CPU -- just connect directly to it */ @@ -878,7 +881,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) /* Wire up the splitters that connect common IRQs to all CPUs */ if (info->num_cpus > 1) { for (i =3D 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) { - if (irq_is_common[i]) { + if (info->irq_is_common[i]) { Object *splitter =3D OBJECT(&s->cpu_irq_splitter[i]); DeviceState *devs =3D DEVICE(splitter); int cpunum; --=20 2.20.1