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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 30/54] hw/arm/armsse: Add missing SSE-200 SYS_PPU
Date: Mon, 8 Mar 2021 17:32:20 +0000
Message-Id: <20210308173244.20710-31-peter.maydell@linaro.org>
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We forgot to implement a TYPE_UNIMPLEMENTED_DEVICE stub
for the SYS_PPU in the SSE-200, which is at 0x50022000.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-31-peter.maydell@linaro.org
---
include/hw/arm/armsse.h | 2 +-
hw/arm/armsse.c | 9 +++++++++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index eb4e937173f..104ba8d26ec 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -135,7 +135,7 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass,
=20
#define SSE_MAX_CPUS 2
=20
-#define NUM_PPUS 7
+#define NUM_PPUS 8
=20
/* Number of CPU IRQs used by the SSE itself */
#define NUM_SSE_IRQS 32
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index f72d1adafea..f43f0524e28 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -320,6 +320,15 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D {
.ppc =3D NO_PPC,
.irq =3D NO_IRQ,
},
+ {
+ .name =3D "SYS_PPU",
+ .type =3D TYPE_UNIMPLEMENTED_DEVICE,
+ .index =3D 7,
+ .addr =3D 0x50022000,
+ .size =3D 0x1000,
+ .ppc =3D NO_PPC,
+ .irq =3D NO_IRQ,
+ },
{
.name =3D NULL,
}
--=20
2.20.1