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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VzBFR3Zg7nDFsCTXNMdnPjwhZo6M/LAKlaXW7PFlGEQ=; b=s710ZIqiHsGTxMAqfwTVWT4nNi2G0anN73o53m1SeUjqrVr5W0QRaGr37a0R6XLKfB ArIRGIIMY9rbzrnAylqg9ZmSEe1ZyID5+2yah8smQFXTwYOmaDFyap7lIN0X3H2Cddht dLCB+quA1eKSfLJ1JUXahSSSH0V/BOiJCWxaML/3vN/rDJ5hIwaTumT/udQxhOQSKWay tcbReIiBR1/m8z4a6ieqKSwJIQjEeTkKeunzqKJaYx/Ao1V8zGb6o9MZvgWQUmuNBROw fWwWWhSaJCN6Crv1p3Dfv8HwokhrNejmzHYWoiv9odavYNXgSVbS7PRzQuXPnzsyHw85 NQ2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VzBFR3Zg7nDFsCTXNMdnPjwhZo6M/LAKlaXW7PFlGEQ=; b=e3i/nxrqa/+EmRNS6Ez3HUSw6HleHUHbZFocY9/cIhe/TPtiU+crZsjSfhKJ2gbvck GJAtdQ2JwWCHyCXLqaO1qEF6bQtxW+W9c+EaJ9gizZlSenFf6qtgp8gPuVRfMd+5494z ikFjyJm8D6YYJJ2Zm9S7JvbSmifPwyACAiPVE6nG0hNil0Tpu+BWAQWPn2NWDUZO3zGZ LF7SyNHMMhrrnzv6RytTkKnyor/ZzT/bMFEXLjP2GXv+CCq5Ob+dRsdctt3XuuQqJtIL WJDVPtvxy6+zMgfQXRF/PZKT1K7RbCY/KMI3YgpUXELPXgdYg9yoFtZbGF0PmT1O8o0A 9ELA== X-Gm-Message-State: AOAM5307TGxVX6dQ3a+VyNBWnKcSFVz5SLhDb2QXwtTBq/12MCdFpPJ6 1mP7SeSFR+8V+d0JlTTx07udZBAFakFckw== X-Google-Smtp-Source: ABdhPJysIneKqgLUtDzpSwfYUVmjQX8puw1YQxbbzGQVCPMr/S4F05sGDwvUZwKUqKOrsNCZhwU0AQ== X-Received: by 2002:a5d:4592:: with SMTP id p18mr25656706wrq.244.1615224788447; Mon, 08 Mar 2021 09:33:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/54] hw/arm/armsse: Move PPUs into data-driven framework Date: Mon, 8 Mar 2021 17:32:19 +0000 Message-Id: <20210308173244.20710-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Move the PPUs into the data-driven device placement framework. We don't implement them, so they are just TYPE_UNIMPLEMENTED stubs. Because the SSE-200 and the IotKit diverge here (the IoTKit does not have the PPUs) we need to separate out the ARMSSEDeviceInfo for the two variants, and only add the PPUs to the SSE-200. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-30-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 10 +- hw/arm/armsse.c | 222 +++++++++++++++++++++++++++++----------- 2 files changed, 165 insertions(+), 67 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 7416c08a802..eb4e937173f 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -135,14 +135,6 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, =20 #define SSE_MAX_CPUS 2 =20 -/* These define what each PPU in the ppu[] index is for */ -#define CPU0CORE_PPU 0 -#define CPU1CORE_PPU 1 -#define DBG_PPU 2 -#define RAM0_PPU 3 -#define RAM1_PPU 4 -#define RAM2_PPU 5 -#define RAM3_PPU 6 #define NUM_PPUS 7 =20 /* Number of CPU IRQs used by the SSE itself */ @@ -176,7 +168,7 @@ struct ARMSSE { IoTKitSysCtl sysinfo; =20 ARMSSEMHU mhu[2]; - UnimplementedDeviceState ppu[NUM_PPUS]; + UnimplementedDeviceState unimp[NUM_PPUS]; UnimplementedDeviceState cachectrl[SSE_MAX_CPUS]; UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS]; =20 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 961b2d44137..f72d1adafea 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -47,6 +47,7 @@ typedef struct ARMSSEDeviceInfo { const char *type; /* QOM type name */ unsigned int index; /* Which of the N devices of this type is this ? */ hwaddr addr; + hwaddr size; /* only needed for TYPE_UNIMPLEMENTED_DEVICE */ int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */ int ppc_port; /* Port number of this device on the PPC */ int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1, or NMI_0 or NMI_1 */ @@ -62,7 +63,6 @@ struct ARMSSEInfo { uint32_t iidr; uint32_t cpuwait_rst; bool has_mhus; - bool has_ppus; bool has_cachectrl; bool has_cpusecctrl; bool has_cpuid; @@ -94,7 +94,7 @@ static Property armsse_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 -static const ARMSSEDeviceInfo sse200_devices[] =3D { +static const ARMSSEDeviceInfo iotkit_devices[] =3D { { .name =3D "timer0", .type =3D TYPE_CMSDK_APB_TIMER, @@ -178,6 +178,153 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { } }; =20 +static const ARMSSEDeviceInfo sse200_devices[] =3D { + { + .name =3D "timer0", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 0, + .addr =3D 0x40000000, + .ppc =3D 0, + .ppc_port =3D 0, + .irq =3D 3, + }, + { + .name =3D "timer1", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 1, + .addr =3D 0x40001000, + .ppc =3D 0, + .ppc_port =3D 1, + .irq =3D 4, + }, + { + .name =3D "s32ktimer", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 2, + .addr =3D 0x4002f000, + .ppc =3D 1, + .ppc_port =3D 0, + .irq =3D 2, + .slowclk =3D true, + }, + { + .name =3D "dualtimer", + .type =3D TYPE_CMSDK_APB_DUALTIMER, + .index =3D 0, + .addr =3D 0x40002000, + .ppc =3D 0, + .ppc_port =3D 2, + .irq =3D 5, + }, + { + .name =3D "s32kwatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 0, + .addr =3D 0x5002e000, + .ppc =3D NO_PPC, + .irq =3D NMI_0, + .slowclk =3D true, + }, + { + .name =3D "nswatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 1, + .addr =3D 0x40081000, + .ppc =3D NO_PPC, + .irq =3D 1, + }, + { + .name =3D "swatchdog", + .type =3D TYPE_CMSDK_APB_WATCHDOG, + .index =3D 2, + .addr =3D 0x50081000, + .ppc =3D NO_PPC, + .irq =3D NMI_1, + }, + { + .name =3D "armsse-sysinfo", + .type =3D TYPE_IOTKIT_SYSINFO, + .index =3D 0, + .addr =3D 0x40020000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "armsse-sysctl", + .type =3D TYPE_IOTKIT_SYSCTL, + .index =3D 0, + .addr =3D 0x50021000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "CPU0CORE_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 0, + .addr =3D 0x50023000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "CPU1CORE_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 1, + .addr =3D 0x50025000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "DBG_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 2, + .addr =3D 0x50029000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "RAM0_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 3, + .addr =3D 0x5002a000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "RAM1_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 4, + .addr =3D 0x5002b000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "RAM2_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 5, + .addr =3D 0x5002c000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D "RAM3_PPU", + .type =3D TYPE_UNIMPLEMENTED_DEVICE, + .index =3D 6, + .addr =3D 0x5002d000, + .size =3D 0x1000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, + { + .name =3D NULL, + } +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -188,12 +335,11 @@ static const ARMSSEInfo armsse_variants[] =3D { .iidr =3D 0, .cpuwait_rst =3D 0, .has_mhus =3D false, - .has_ppus =3D false, .has_cachectrl =3D false, .has_cpusecctrl =3D false, .has_cpuid =3D false, .props =3D iotkit_properties, - .devinfo =3D sse200_devices, + .devinfo =3D iotkit_devices, }, { .name =3D TYPE_SSE200, @@ -204,7 +350,6 @@ static const ARMSSEInfo armsse_variants[] =3D { .iidr =3D 0, .cpuwait_rst =3D 2, .has_mhus =3D true, - .has_ppus =3D true, .has_cachectrl =3D true, .has_cpusecctrl =3D true, .has_cpuid =3D true, @@ -431,6 +576,11 @@ static void armsse_init(Object *obj) assert(devinfo->index =3D=3D 0); object_initialize_child(obj, devinfo->name, &s->sysctl, TYPE_IOTKIT_SYSCTL); + } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) { + assert(devinfo->index < ARRAY_SIZE(s->unimp)); + object_initialize_child(obj, devinfo->name, + &s->unimp[devinfo->index], + TYPE_UNIMPLEMENTED_DEVICE); } else { g_assert_not_reached(); } @@ -463,26 +613,6 @@ static void armsse_init(Object *obj) object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); } - if (info->has_ppus) { - for (i =3D 0; i < info->num_cpus; i++) { - char *name =3D g_strdup_printf("CPU%dCORE_PPU", i); - int ppuidx =3D CPU0CORE_PPU + i; - - object_initialize_child(obj, name, &s->ppu[ppuidx], - TYPE_UNIMPLEMENTED_DEVICE); - g_free(name); - } - object_initialize_child(obj, "DBG_PPU", &s->ppu[DBG_PPU], - TYPE_UNIMPLEMENTED_DEVICE); - for (i =3D 0; i < info->sram_banks; i++) { - char *name =3D g_strdup_printf("RAM%d_PPU", i); - int ppuidx =3D RAM0_PPU + i; - - object_initialize_child(obj, name, &s->ppu[ppuidx], - TYPE_UNIMPLEMENTED_DEVICE); - g_free(name); - } - } if (info->has_cachectrl) { for (i =3D 0; i < info->num_cpus; i++) { char *name =3D g_strdup_printf("cachectrl%d", i); @@ -568,17 +698,6 @@ static qemu_irq armsse_get_common_irq_in(ARMSSE *s, in= t irqno) } } =20 -static void map_ppu(ARMSSE *s, int ppuidx, const char *name, hwaddr addr) -{ - /* Map a PPU unimplemented device stub */ - DeviceState *dev =3D DEVICE(&s->ppu[ppuidx]); - - qdev_prop_set_string(dev, "name", name); - qdev_prop_set_uint64(dev, "size", 0x1000); - sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->ppu[ppuidx]), 0, addr); -} - static void armsse_realize(DeviceState *dev, Error **errp) { ARMSSE *s =3D ARM_SSE(dev); @@ -941,6 +1060,15 @@ static void armsse_realize(DeviceState *dev, Error **= errp) return; } mr =3D sysbus_mmio_get_region(sbd, 0); + } else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) { + sbd =3D SYS_BUS_DEVICE(&s->unimp[devinfo->index]); + + qdev_prop_set_string(DEVICE(sbd), "name", devinfo->name); + qdev_prop_set_uint64(DEVICE(sbd), "size", devinfo->size); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); } else { g_assert_not_reached(); } @@ -1158,28 +1286,6 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) memory_region_add_subregion(&s->container, devinfo->addr, mr); } =20 - if (info->has_ppus) { - /* CPUnCORE_PPU for each CPU */ - for (i =3D 0; i < info->num_cpus; i++) { - char *name =3D g_strdup_printf("CPU%dCORE_PPU", i); - - map_ppu(s, CPU0CORE_PPU + i, name, 0x50023000 + i * 0x2000); - /* - * We don't support CPU debug so don't create the - * CPU0DEBUG_PPU at 0x50024000 and 0x50026000. - */ - g_free(name); - } - map_ppu(s, DBG_PPU, "DBG_PPU", 0x50029000); - - for (i =3D 0; i < info->sram_banks; i++) { - char *name =3D g_strdup_printf("RAM%d_PPU", i); - - map_ppu(s, RAM0_PPU + i, name, 0x5002a000 + i * 0x1000); - g_free(name); - } - } - for (i =3D 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) { Object *splitter =3D OBJECT(&s->ppc_irq_splitter[i]); =20 --=20 2.20.1