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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QFfMyiBhaGCd5vnrl1Fd6DmKH+l7p58EQ9KdLB+f7Bc=; b=b3xWueesLGwVCL2tDFBfGPJFHjgJUw9jaZMongkB6oDW8TeO5/D/KztwsQlC77pyvd y4YtOgjSbb4hAphDXNzrxQOWu75oC+LCFB4Ft3LuYiwg90HrVSYpmF3rpfYWS0JT7BsE AnXnxm4ivMjoj981Z+FVcCnfWdaGiFpYNRmoLuznGhRKWFlHUCdFaRav3fKv2F1oOD7D FRA88oXq71vQK4hKh984O1zYTjkCcW/RSv2u39uZVPI5qTshRFLgHIIqUzd3Qku4oEfI G3c8+aguRc+nRV/JGqIHCDOwBav6/18w0wNfMt/9vGdyIJFQWqVC0P/+D7eviuBujuwO 2CkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QFfMyiBhaGCd5vnrl1Fd6DmKH+l7p58EQ9KdLB+f7Bc=; b=AxuRHpEb3vthfs32JN12zQ30kyFGyeADO4QvyI1syv7h0LO8nCHN/+xfWzv8aKmFNt 9No+mbWhrM4Vdq9w9Wf9JHHTifgsr+rIWHtKtSB7RL8cGE95AYDwDpe/7N0HMRwGiRvZ 40TWEHqWwrlBeTADR2j0NJ9rHPGpCSZCDMrpw3/iMIaNdG4Rimo7o/Stq4VAI+957yNW gDqk5iRpsXvMPfWU7hyRvjNSNyIOLiNH4aWvhVrTJsIGyrxeg84BRW5b02skW+eYluan 0NvBMTgS7mBnD7PvVF0HMH/JpuwYgRjqHMQnSuyN1/zPDiudk+JRRxz/KBqwjwqcdUBp dEeA== X-Gm-Message-State: AOAM5334ypWpu74UIgKQyHmjKgm/x10eqUJpcrW7SCG3WEMEIM6kn2yp +75XA5lXWvmJWXtCFownSrGbH5ekPG0d7w== X-Google-Smtp-Source: ABdhPJxtY/9Bl0nVmTN7UnRQ+4FC4uQSi/9m6PVl42GCtSGkh/cx9wax6ubT0OzJgvNfWSF7pskyAA== X-Received: by 2002:a5d:468e:: with SMTP id u14mr24142921wrq.359.1615224787619; Mon, 08 Mar 2021 09:33:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/54] hw/arm/armsse: Move sysctl register block into data-driven framework Date: Mon, 8 Mar 2021 17:32:18 +0000 Message-Id: <20210308173244.20710-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Move the sysctl register block into the data-driven device placement framework. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-29-peter.maydell@linaro.org --- hw/arm/armsse.c | 44 ++++++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 91f30b1fdc4..961b2d44137 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -165,6 +165,14 @@ static const ARMSSEDeviceInfo sse200_devices[] =3D { .ppc =3D NO_PPC, .irq =3D NO_IRQ, }, + { + .name =3D "armsse-sysctl", + .type =3D TYPE_IOTKIT_SYSCTL, + .index =3D 0, + .addr =3D 0x50021000, + .ppc =3D NO_PPC, + .irq =3D NO_IRQ, + }, { .name =3D NULL, } @@ -419,6 +427,10 @@ static void armsse_init(Object *obj) assert(devinfo->index =3D=3D 0); object_initialize_child(obj, devinfo->name, &s->sysinfo, TYPE_IOTKIT_SYSINFO); + } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) { + assert(devinfo->index =3D=3D 0); + object_initialize_child(obj, devinfo->name, &s->sysctl, + TYPE_IOTKIT_SYSCTL); } else { g_assert_not_reached(); } @@ -447,8 +459,6 @@ static void armsse_init(Object *obj) g_free(name); } =20 - object_initialize_child(obj, "armsse-sysctl", &s->sysctl, - TYPE_IOTKIT_SYSCTL); if (info->has_mhus) { object_initialize_child(obj, "mhu0", &s->mhu[0], TYPE_ARMSSE_MHU); object_initialize_child(obj, "mhu1", &s->mhu[1], TYPE_ARMSSE_MHU); @@ -915,6 +925,22 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) return; } mr =3D sysbus_mmio_get_region(sbd, 0); + } else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) { + /* System control registers */ + sbd =3D SYS_BUS_DEVICE(&s->sysctl); + + object_property_set_int(OBJECT(&s->sysctl), "sse-version", + info->sse_version, &error_abort); + object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", + info->cpuwait_rst, &error_abort); + object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", + s->init_svtor, &error_abort); + object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", + s->init_svtor, &error_abort); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); } else { g_assert_not_reached(); } @@ -1132,20 +1158,6 @@ static void armsse_realize(DeviceState *dev, Error *= *errp) memory_region_add_subregion(&s->container, devinfo->addr, mr); } =20 - /* System control registers */ - object_property_set_int(OBJECT(&s->sysctl), "sse-version", - info->sse_version, &error_abort); - object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST", - info->cpuwait_rst, &error_abort); - object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST", - s->init_svtor, &error_abort); - object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST", - s->init_svtor, &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysctl), errp)) { - return; - } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctl), 0, 0x50021000); - if (info->has_ppus) { /* CPUnCORE_PPU for each CPU */ for (i =3D 0; i < info->num_cpus; i++) { --=20 2.20.1