From nobody Tue Apr 15 10:55:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615226913; cv=none; d=zohomail.com; s=zohoarc; b=K6rW1L7FbJoZdgmQxyslOI0m9WNLWfXQqmOjAHGBnm4wEWozsmO1p2qkMFGxMQgQQN7PBLaUXif/RQi0AoM86US0O4hBKRAO4M2YGm2njtlq84/Ko8fPX7ULjMi5gnuY2x3ZnvECtHmbeI7gVry7TTtVLSqMsB7br932LNeOoAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615226913; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pcbo91ZW7y7gpWeGAiM+MiGzgSfPEWZH4AyPuFVDBM4=; b=nN6Zx0qe2/Mkzsd8PFuV3LM15W/9NGsmc3i+C+LiDXQRYbXvu/kXWxxri+bSWG5DVZdpx7GobDdcLRJJKoVMZWd26jkKISteLHrIuyw+7RRpd7MF8++HBIpgNJaMuh76QE9BDc5o8y5qPdKs/2q6b2SZabN23km4qp1uD67AxQw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615226913746782.571978484036; Mon, 8 Mar 2021 10:08:33 -0800 (PST) Received: from localhost ([::1]:48964 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJKIy-0003gK-GQ for importer@patchew.org; Mon, 08 Mar 2021 13:08:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJJkv-0006oR-Bx for qemu-devel@nongnu.org; Mon, 08 Mar 2021 12:33:21 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:54572) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lJJkg-00075n-4s for qemu-devel@nongnu.org; Mon, 08 Mar 2021 12:33:21 -0500 Received: by mail-wm1-x32b.google.com with SMTP id u187so2487wmg.4 for ; Mon, 08 Mar 2021 09:33:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pcbo91ZW7y7gpWeGAiM+MiGzgSfPEWZH4AyPuFVDBM4=; b=wz6TIaMkxoWUu5ttRu1pedX3nn2SJsZQEO8Q5CwPECHoKwaUARGcLcpcI115ovcgTK lxswUlb/B1RTwmCM+bnfuxCXdvxq1+DCLgduPb4seDRBXmZwE5kkRIq7WgH5A/6zTbYu Ca4gwf7rFu6yZ/t/Z99/fDH8VTV8/MdqIM8TOvrDz4y1z0rrAJo8gtyjRTzJmABirO5B j9XD+y8DCJaR6hSmhPj3n3rC/LYrpiR8u1+v5k4iL48jP+U4Uy1Dj9k+QRyvzQTwU9os CksctbzPLjtxGo5s2+BjWupfQg/R1Ds5LZ7HxC0yXZv+uL95V7bundx8ZFuGx4TK6Kz/ DZiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pcbo91ZW7y7gpWeGAiM+MiGzgSfPEWZH4AyPuFVDBM4=; b=qm1MX/bI5jdfRbZnLC3f0NlBcc8D1dgLncShz+mO8A17QiqqWyIAUoKKBuSj1jVrDX R5vgDpjWsabnvWXXk9r8VrYqED5zLX+Zp06mrwMGe+yG67MAUGOMN+hneefhbI7f1ibk SRB5o07YQg1pMrAzY5nTgSZKW2KQBGoKZa7qPoauIzX3UwNUEVauJRUc8CF156vUPiDu 4Rk96MS9Djs9nJxxk8qVV/wRDG8MBFYB50bXsI5fP9bE1efDDlBFm1RwF68tFlipL7Y7 cOlQV6aSQdGSZnd2/5sIohO46t+3MGiD0w7tUEbgpYOTUQN06VQ05FQq1ojE2XQhjUvO pgzw== X-Gm-Message-State: AOAM533F+JmqK3TCmHYmkvf9rlDAkDrow899fLT2UCkX59dNqwYV1XMs m/Owq8lAv0wCd3tt9yCc4RGTcvqJVmqRxg== X-Google-Smtp-Source: ABdhPJyM6XM93KsWYyxDgblIpP2njdqvy+RJSadLUJWD2tu4t38KQ7ragLsaBrfCahtumSm9EMKWcA== X-Received: by 2002:a05:600c:1992:: with SMTP id t18mr3034283wmq.125.1615224783907; Mon, 08 Mar 2021 09:33:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/54] hw/arm/armsse: Add framework for data-driven device placement Date: Mon, 8 Mar 2021 17:32:13 +0000 Message-Id: <20210308173244.20710-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The SSE-300 is mostly the same as the SSE-200, but it has moved some of the devices in the memory map and uses different device types in some cases. To accommodate this, add a framework where the placement and wiring of some devices can be specified in a data table. This commit adds the framework for this data-driven device placement, and makes the CMSDK APB timer devices use it. Subsequent commits will convert the other devices which differ between SSE-200 and SSE-300. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-24-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 3 +- hw/arm/armsse.c | 147 +++++++++++++++++++++++++++++++++------- 2 files changed, 125 insertions(+), 25 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index e34263fed8b..c1f4df295a4 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -158,8 +158,7 @@ struct ARMSSE { IoTKitSecCtl secctl; TZPPC apb_ppc[NUM_INTERNAL_PPCS]; TZMPC mpc[IOTS_NUM_MPC]; - CMSDKAPBTimer timer0; - CMSDKAPBTimer timer1; + CMSDKAPBTimer timer[2]; CMSDKAPBTimer s32ktimer; qemu_or_irq ppc_irq_orgate; SplitIRQ sec_resp_splitter; diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 5ae6ce344ee..22dd437a4ba 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -24,6 +24,27 @@ #include "hw/irq.h" #include "hw/qdev-clock.h" =20 +/* + * The SSE-300 puts some devices in different places to the + * SSE-200 (and original IoTKit). We use an array of these structs + * to define how each variant lays out these devices. (Parts of the + * SoC that are the same for all variants aren't handled via these + * data structures.) + */ + +#define NO_IRQ -1 +#define NO_PPC -1 + +typedef struct ARMSSEDeviceInfo { + const char *name; /* name to use for the QOM object; NULL terminates l= ist */ + const char *type; /* QOM type name */ + unsigned int index; /* Which of the N devices of this type is this ? */ + hwaddr addr; + int ppc; /* Index of APB PPC this device is wired up to, or NO_PPC */ + int ppc_port; /* Port number of this device on the PPC */ + int irq; /* NO_IRQ, or 0..NUM_SSE_IRQS-1 */ +} ARMSSEDeviceInfo; + struct ARMSSEInfo { const char *name; uint32_t sse_version; @@ -38,6 +59,7 @@ struct ARMSSEInfo { bool has_cpusecctrl; bool has_cpuid; Property *props; + const ARMSSEDeviceInfo *devinfo; }; =20 static Property iotkit_properties[] =3D { @@ -64,6 +86,30 @@ static Property armsse_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +static const ARMSSEDeviceInfo sse200_devices[] =3D { + { + .name =3D "timer0", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 0, + .addr =3D 0x40000000, + .ppc =3D 0, + .ppc_port =3D 0, + .irq =3D 3, + }, + { + .name =3D "timer1", + .type =3D TYPE_CMSDK_APB_TIMER, + .index =3D 1, + .addr =3D 0x40001000, + .ppc =3D 0, + .ppc_port =3D 1, + .irq =3D 4, + }, + { + .name =3D NULL, + } +}; + static const ARMSSEInfo armsse_variants[] =3D { { .name =3D TYPE_IOTKIT, @@ -79,6 +125,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpusecctrl =3D false, .has_cpuid =3D false, .props =3D iotkit_properties, + .devinfo =3D sse200_devices, }, { .name =3D TYPE_SSE200, @@ -94,6 +141,7 @@ static const ARMSSEInfo armsse_variants[] =3D { .has_cpusecctrl =3D true, .has_cpuid =3D true, .props =3D armsse_properties, + .devinfo =3D sse200_devices, }, }; =20 @@ -250,6 +298,7 @@ static void armsse_init(Object *obj) ARMSSE *s =3D ARM_SSE(obj); ARMSSEClass *asc =3D ARM_SSE_GET_CLASS(obj); const ARMSSEInfo *info =3D asc->info; + const ARMSSEDeviceInfo *devinfo; int i; =20 assert(info->sram_banks <=3D MAX_SRAM_BANKS); @@ -290,6 +339,18 @@ static void armsse_init(Object *obj) } } =20 + for (devinfo =3D info->devinfo; devinfo->name; devinfo++) { + assert(devinfo->ppc =3D=3D NO_PPC || devinfo->ppc < ARRAY_SIZE(s->= apb_ppc)); + if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { + assert(devinfo->index < ARRAY_SIZE(s->timer)); + object_initialize_child(obj, devinfo->name, + &s->timer[devinfo->index], + TYPE_CMSDK_APB_TIMER); + } else { + g_assert_not_reached(); + } + } + object_initialize_child(obj, "secctl", &s->secctl, TYPE_IOTKIT_SECCTL); =20 for (i =3D 0; i < ARRAY_SIZE(s->apb_ppc); i++) { @@ -312,8 +373,6 @@ static void armsse_init(Object *obj) object_initialize_child(obj, name, splitter, TYPE_SPLIT_IRQ); g_free(name); } - object_initialize_child(obj, "timer0", &s->timer0, TYPE_CMSDK_APB_TIME= R); - object_initialize_child(obj, "timer1", &s->timer1, TYPE_CMSDK_APB_TIME= R); object_initialize_child(obj, "s32ktimer", &s->s32ktimer, TYPE_CMSDK_APB_TIMER); object_initialize_child(obj, "dualtimer", &s->dualtimer, @@ -453,6 +512,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) ARMSSE *s =3D ARM_SSE(dev); ARMSSEClass *asc =3D ARM_SSE_GET_CLASS(dev); const ARMSSEInfo *info =3D asc->info; + const ARMSSEDeviceInfo *devinfo; int i; MemoryRegion *mr; Error *err =3D NULL; @@ -736,25 +796,53 @@ static void armsse_realize(DeviceState *dev, Error **= errp) * it to the appropriate PPC port; then we can realize the PPC and * map its upstream ends to the right place in the container. */ - qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) { - return; - } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer0), 0, - armsse_get_common_irq_in(s, 3)); - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer0), 0); - object_property_set_link(OBJECT(&s->apb_ppc[0]), "port[0]", OBJECT(mr), - &error_abort); + for (devinfo =3D info->devinfo; devinfo->name; devinfo++) { + SysBusDevice *sbd; + qemu_irq irq; =20 - qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) { - return; + if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) { + sbd =3D SYS_BUS_DEVICE(&s->timer[devinfo->index]); + + qdev_connect_clock_in(DEVICE(sbd), "pclk", s->mainclk); + if (!sysbus_realize(sbd, errp)) { + return; + } + mr =3D sysbus_mmio_get_region(sbd, 0); + } else { + g_assert_not_reached(); + } + + switch (devinfo->irq) { + case NO_IRQ: + irq =3D NULL; + break; + case 0 ... NUM_SSE_IRQS - 1: + irq =3D armsse_get_common_irq_in(s, devinfo->irq); + break; + default: + g_assert_not_reached(); + } + + if (irq) { + sysbus_connect_irq(sbd, 0, irq); + } + + /* + * Devices connected to a PPC are connected to the port here; + * we will map the upstream end of that port to the right address + * in the container later after the PPC has been realized. + * Devices not connected to a PPC can be mapped immediately. + */ + if (devinfo->ppc !=3D NO_PPC) { + TZPPC *ppc =3D &s->apb_ppc[devinfo->ppc]; + g_autofree char *portname =3D g_strdup_printf("port[%d]", + devinfo->ppc_port); + object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), + &error_abort); + } else { + memory_region_add_subregion(&s->container, devinfo->addr, mr); + } } - sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0, - armsse_get_common_irq_in(s, 4)); - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0); - object_property_set_link(OBJECT(&s->apb_ppc[0]), "port[1]", OBJECT(mr), - &error_abort); =20 qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) { @@ -813,10 +901,6 @@ static void armsse_realize(DeviceState *dev, Error **e= rrp) sbd_apb_ppc0 =3D SYS_BUS_DEVICE(&s->apb_ppc[0]); dev_apb_ppc0 =3D DEVICE(&s->apb_ppc[0]); =20 - mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 0); - memory_region_add_subregion(&s->container, 0x40000000, mr); - mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 1); - memory_region_add_subregion(&s->container, 0x40001000, mr); mr =3D sysbus_mmio_get_region(sbd_apb_ppc0, 2); memory_region_add_subregion(&s->container, 0x40002000, mr); if (info->has_mhus) { @@ -947,6 +1031,23 @@ static void armsse_realize(DeviceState *dev, Error **= errp) qdev_get_gpio_in_named(dev_apb_ppc1, "cfg_sec_resp", 0)); =20 + /* + * Now both PPCs are realized we can map the upstream ends of + * ports which correspond to entries in the devinfo array. + * The ports which are connected to non-devinfo devices have + * already been mapped. + */ + for (devinfo =3D info->devinfo; devinfo->name; devinfo++) { + SysBusDevice *ppc_sbd; + + if (devinfo->ppc =3D=3D NO_PPC) { + continue; + } + ppc_sbd =3D SYS_BUS_DEVICE(&s->apb_ppc[devinfo->ppc]); + mr =3D sysbus_mmio_get_region(ppc_sbd, devinfo->ppc_port); + memory_region_add_subregion(&s->container, devinfo->addr, mr); + } + if (!object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION", info->sys_version, errp)) { return; --=20 2.20.1