From nobody Tue Apr 15 10:55:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1615227141; cv=none; d=zohomail.com; s=zohoarc; b=SOB7vBZWULpJjn2wMMuZtyFBT4iieI97j4LrZkkWYToybiJSh2O58yOMaUAYccWU/DlGrPeKYktk/bqqGBcH6P2aBNhzZhAsXZgIG92ibA+gYXOLgc7ZMxiCp+jJPLnH5ru3HiDqIbqwwWA/3T6hyFlUpI9TH6pJSnsXj98NB/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615227141; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HxD8fhdwI5EWLnRxldyHFahFN0HnsrlK2jQE3T7tBOs=; b=nYPFQzZjPalEf4MdoHcpm/hPvHcyYOY5AjDH0SuFgPCzR9wti/V0MH89lCSsgEFHQGSFXU06PSPpr6DVL7ByyfV0mv37cM6/dSTjMsemLLz9O8omqkUA6PAD2tS0Z7JiGtTg1KW4aSI14uzPv7jNCFUIgw5ASjjhS4xjIhyJL3w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615227141723171.4271489779793; Mon, 8 Mar 2021 10:12:21 -0800 (PST) Received: from localhost ([::1]:58186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lJKMe-0007Z1-Lf for importer@patchew.org; Mon, 08 Mar 2021 13:12:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53826) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lJJl1-000744-E4 for qemu-devel@nongnu.org; Mon, 08 Mar 2021 12:33:28 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:40086) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lJJkf-00075c-FX for qemu-devel@nongnu.org; Mon, 08 Mar 2021 12:33:27 -0500 Received: by mail-wr1-x431.google.com with SMTP id l11so8934171wrp.7 for ; Mon, 08 Mar 2021 09:33:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id i10sm18628217wrs.11.2021.03.08.09.33.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 09:33:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HxD8fhdwI5EWLnRxldyHFahFN0HnsrlK2jQE3T7tBOs=; b=SyVvmpSukfv5ifdAl8vJI7aY+cxu8Jz/O7ouKlfPfoahX0A1U/Jv5oAUwznURYSWrz Osx79Mjk9vsmRZYBdAINfIO++j906bn+AqlA+t5v6Qllbh6k7uryIYJIEVWBR5LApEnJ 5hq8y9aBRgZyLXj35YxirP/OOHFsHxQztrWO+SbFDsN17P4PUFTZllSeRZ2zpKK0TWfh 0/HpEd5pBf1Iq8Sfj/ZkS8PnfND52p6I8SstB52QCaFLuCt5GMGwmKEo6OnnQLK3D0zB +gVPrqcWoc0JDDTEcnPURlakKJWyIQV69J8vWjdENT0pOPoTjX5+qw3VgKA2IKKbxf8I YMEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HxD8fhdwI5EWLnRxldyHFahFN0HnsrlK2jQE3T7tBOs=; b=oH1Wg2We0cnbCbOEvrHssjviro1JORXsLAld/x00AScXKjgkygw7fjlqfrSm5vqHZm 4/HAcYtPYlwYXtjrBPLwBVd9tM1HJaN8HSRp6RLtkAfsbcIrd7WoLHrr0Cwq+QYm6tW9 PZbFEUwVCgfwRHnRM3XsQ1n9nmIrFhZTkKY47MZv9X+kFPtH8Soa0MYf2na2MovcFnCC mkHxLmkiLOU0yaalmV26N4n98FwnfCRxRH47xCp5qf/JLWd4c/RSPPZtyi/vZF9tEuPH lKWIsA8bhQNmHt15wvMYvzbTSIBcv4VqjXWnv0hKbY1EcjZLrxVWNtpogYViFPfk/7nM dmGg== X-Gm-Message-State: AOAM5332974Jot3BEDZIaPh1LQca2y78xRkQV/+1+m0iMCtK8w1fVs19 ZPBqPH9VUsnnINIOqXSKq7d0Jw90NfxaJg== X-Google-Smtp-Source: ABdhPJz8vQm9S/52d+jxzj9lh95PcszSg/7p3+IRW8fV+R0YWOmZ1edY4BK8u/IhfNS84nEJvTFG6g== X-Received: by 2002:a5d:4d01:: with SMTP id z1mr23877807wrt.133.1615224783058; Mon, 08 Mar 2021 09:33:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/54] hw/arm/armsse: Add a define for number of IRQs used by the SSE itself Date: Mon, 8 Mar 2021 17:32:12 +0000 Message-Id: <20210308173244.20710-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210308173244.20710-1-peter.maydell@linaro.org> References: <20210308173244.20710-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The SSE uses 32 interrupts for its own devices, and then passes through its expansion IRQ inputs to the CPU's interrupts 33 and upward. Add a define for the number of IRQs the SSE uses for itself, instead of hardcoding 32. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210219144617.4782-23-peter.maydell@linaro.org --- include/hw/arm/armsse.h | 5 ++++- hw/arm/armsse.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 771150b0a94..e34263fed8b 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -145,6 +145,9 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass, #define RAM3_PPU 6 #define NUM_PPUS 7 =20 +/* Number of CPU IRQs used by the SSE itself */ +#define NUM_SSE_IRQS 32 + struct ARMSSE { /*< private >*/ SysBusDevice parent_obj; @@ -165,7 +168,7 @@ struct ARMSSE { qemu_or_irq mpc_irq_orgate; qemu_or_irq nmi_orgate; =20 - SplitIRQ cpu_irq_splitter[32]; + SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS]; =20 CMSDKAPBDualTimer dualtimer; =20 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 2b25fca1ca2..5ae6ce344ee 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -531,7 +531,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) int j; char *gpioname; =20 - qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32); + qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IR= QS); /* * In real hardware the initial Secure VTOR is set from the INITSV= TOR* * registers in the IoT Kit System Control Register block. In QEMU @@ -602,7 +602,7 @@ static void armsse_realize(DeviceState *dev, Error **er= rp) /* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and u= p */ s->exp_irqs[i] =3D g_new(qemu_irq, s->exp_numirq); for (j =3D 0; j < s->exp_numirq; j++) { - s->exp_irqs[i][j] =3D qdev_get_gpio_in(cpudev, j + 32); + s->exp_irqs[i][j] =3D qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQ= S); } if (i =3D=3D 0) { gpioname =3D g_strdup("EXP_IRQ"); --=20 2.20.1