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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In all cases restricted to 64-bit hosts, tcg_read_r is identical. We retain the 64-bit symbol for the single case of INDEX_op_qemu_st_i64. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------ 1 file changed, 42 insertions(+), 51 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index cef12f263d..9efe69d05f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ul= ong *regs, TCGReg index) return regs[index]; } =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 -static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) -{ - return tci_read_reg(regs, index); -} -#endif - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -146,9 +139,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *re= gs, static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint64_t value =3D tci_read_reg64(regs, **tb_ptr); - *tb_ptr +=3D 1; - return value; + return tci_read_r(regs, tb_ptr); } #endif =20 @@ -390,8 +381,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; @@ -672,7 +663,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_mov_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i64: @@ -696,7 +687,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 =3D tci_read_r64(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) =3D t0; @@ -706,62 +697,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; =20 @@ -769,41 +760,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); - t2 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); + t2 =3D tci_read_r(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); @@ -811,8 +802,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r64(regs, &tb_ptr); - t1 =3D tci_read_r64(regs, &tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -882,21 +873,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSt= ate *env, #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif --=20 2.25.1