From nobody Fri May 17 17:06:01 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1615043885; cv=none; d=zohomail.com; s=zohoarc; b=gKxkGTMsL3zWhiPPv+a6+UFoaxmsPdWySYrs/FXkCPkiyTy3Qa1wwVscq3uAoE9cMqSmWlP3Pw1bLMXVsNakhuYJyEKbHBWCDGJcbuokI/SimIkpgp4JjRVVPGAL3Vipze0+5Uv78rHKQNKNUAJ3016mbPAKEf+7Xpf3hqiL+uI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615043885; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:MIME-Version:Message-ID:Sender:Subject:To; bh=+3Mxcfb7HBGAtUHh1Jxqt2KxxyAmNH4FZkf2tSgW9rE=; b=KpVY2hSWAxnOT7hKvdBWGr2tuqLzpImVP42603sHCi3Lm3u6833X0kHUGsGTEuSJ8Wfpiwg/di4QPR37hE1nZrKNTokCSU7uwQCcpgyIEKUKlPU9i/v1JHzXuojDLyRBsWplK+j1kG1HAwgwkK0qjs+cNq8sZZfxvTKFK/cwTOk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.zohomail.com with SMTPS id 1615043885876818.7612943063422; Sat, 6 Mar 2021 07:18:05 -0800 (PST) Received: by mail-wr1-f43.google.com with SMTP id d15so5839404wrv.5 for ; Sat, 06 Mar 2021 07:18:05 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 75sm10416576wma.23.2021.03.06.07.18.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 07:18:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=+3Mxcfb7HBGAtUHh1Jxqt2KxxyAmNH4FZkf2tSgW9rE=; b=QdQO5w4I7oONMHFDszWjZast+TZ1nGPXmksVqL8e8x7mkUUMXkm5xW6tx7cEMSlkyT jd4SQXu+d2qmPj9anyfeioA5dCUz43TOOpo+x5+C6+g0b+648FoAujh3DhZdaQ34T78M jU5UbbPSdcVVEsqS/DCJgn96whY8qlTEkVL6pwz0CVMRw++XdbU4ZiopwmK+STcCvIpy 3qr6cRKw3a4kGYPeGoUm04v/kWKGQWBeK58xsOsFQi0T0DD8ecG9FDJ8T7jdWPDz0YAI 9NVcVAUW61S5IzcKcA0p67CQuhDMk34bdOntSmMrTmpLDV5Auq4I0/eO9MPwsch6bnNL Fudw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=+3Mxcfb7HBGAtUHh1Jxqt2KxxyAmNH4FZkf2tSgW9rE=; b=X+R/jErmL/kf3t4P9HoXkFuRyCP9jCI7OqUnHz4SUjOsvMLkZ1tVhD2zkRsYwh0hxC SosZ9CWXudk20G4dtBQyE92hihvJnP+7xWi9ZzKudkVhw1QiRWoYYq69jFJ9VJOh3rEg NUsJiGJZdIU4LUlxRQ4cxqo/A8b8vh+/jm4z3Ezlg0iVt4Ky1B1yQoXtQA5fnCsO4rL/ wzUM/8o6e49fooDlnNC+s1FI6o6yF59WaOBEVBfSgi8hrZWSLO78/tAkKXPVGXnixbJI Kx3wMSUNkOloJPYdrd6zZRskVNPa3LqtA3h47cw6lqI7Gba6k5mvn1oKQam8apkIl/jU MeZA== X-Gm-Message-State: AOAM5326QtywX2qx4OEuPlPhBy/hO8bAT6/vBnpRoqWFPHUA/dzvD37K PclG3+MJRKggf/0ekxiOxYA= X-Google-Smtp-Source: ABdhPJyL+ws+CdZP5TKCpp0ZFMyGXSEfohTyU5zO2AHAWNequGJw6n++PfRnWKhjflEXI3KTY0aYrg== X-Received: by 2002:adf:f1c4:: with SMTP id z4mr14982343wro.404.1615043883832; Sat, 06 Mar 2021 07:18:03 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Rebecca Cran , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3] target/arm: Restrict v7A TCG cpus to TCG accel Date: Sat, 6 Mar 2021 16:18:00 +0100 Message-Id: <20210306151801.2388182-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). A KVM-only build won't be able to run TCG cpus, move the v7A CPU definitions to cpu_tcg.c. Reported-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v3: Rebased on ed84a60ca80 ("target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU") Based-on: target-arm.next --- target/arm/cpu.c | 335 ------------------------------------------- target/arm/cpu_tcg.c | 318 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 318 insertions(+), 335 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6facb66f4d2..ae04884408c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1922,331 +1922,6 @@ static ObjectClass *arm_cpu_class_by_name(const cha= r *cpu_model) return oc; } =20 -/* CPU models. These are not needed for the AArch64 linux-user build. */ -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - -static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { - { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2AUXCR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void cortex_a8_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a8"; - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_EL3); - cpu->midr =3D 0x410fc080; - cpu->reset_fpsid =3D 0x410330c0; - cpu->isar.mvfr0 =3D 0x11110222; - cpu->isar.mvfr1 =3D 0x00011111; - cpu->ctr =3D 0x82048004; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; - cpu->isar.id_dfr0 =3D 0x400; - cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x31100003; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01202000; - cpu->isar.id_mmfr3 =3D 0x11; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x12112111; - cpu->isar.id_isar2 =3D 0x21232031; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; - cpu->isar.dbgdidr =3D 0x15141000; - cpu->clidr =3D (1 << 27) | (2 << 24) | 3; - cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ - cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ - cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ - cpu->reset_auxcr =3D 2; - define_arm_cp_regs(cpu, cortexa8_cp_reginfo); -} - -static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { - /* - * power_control should be set to maximum latency. Again, - * default to 0 and set by private hook - */ - { .name =3D "A9_PWRCTL", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_control) }, - { .name =3D "A9_DIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D = 0, .opc2 =3D 1, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_diagnostic) }, - { .name =3D "A9_PWRDIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_diagnostic) }, - { .name =3D "NEONBUSY", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - /* TLB lockdown control */ - { .name =3D "TLB_LOCKR", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 2, - .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, - { .name =3D "TLB_LOCKW", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 4, - .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, - { .name =3D "TLB_VA", .cp =3D 15, .crn =3D 15, .crm =3D 5, .opc1 =3D 5= , .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - { .name =3D "TLB_PA", .cp =3D 15, .crn =3D 15, .crm =3D 6, .opc1 =3D 5= , .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - { .name =3D "TLB_ATTR", .cp =3D 15, .crn =3D 15, .crm =3D 7, .opc1 =3D= 5, .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - REGINFO_SENTINEL -}; - -static void cortex_a9_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a9"; - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_EL3); - /* - * Note that A9 supports the MP extensions even for - * A9UP and single-core A9MP (which are both different - * and valid configurations; we don't model A9UP). - */ - set_feature(&cpu->env, ARM_FEATURE_V7MP); - set_feature(&cpu->env, ARM_FEATURE_CBAR); - cpu->midr =3D 0x410fc090; - cpu->reset_fpsid =3D 0x41033090; - cpu->isar.mvfr0 =3D 0x11110222; - cpu->isar.mvfr1 =3D 0x01111111; - cpu->ctr =3D 0x80038003; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; - cpu->isar.id_dfr0 =3D 0x000; - cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x00100103; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01230000; - cpu->isar.id_mmfr3 =3D 0x00002111; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; - cpu->isar.dbgdidr =3D 0x35141000; - cpu->clidr =3D (1 << 27) | (1 << 24) | 3; - cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ - cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ - define_arm_cp_regs(cpu, cortexa9_cp_reginfo); -} - -#ifndef CONFIG_USER_ONLY -static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - MachineState *ms =3D MACHINE(qdev_get_machine()); - - /* - * Linux wants the number of processors from here. - * Might as well set the interrupt-controller bit too. - */ - return ((ms->smp.cpus - 1) << 24) | (1 << 23); -} -#endif - -static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, - .writefn =3D arm_cp_write_ignore, }, -#endif - { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void cortex_a7_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a7"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A7; - cpu->midr =3D 0x410fc075; - cpu->reset_fpsid =3D 0x41023075; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x11111111; - cpu->ctr =3D 0x84448003; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x02010555; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; - /* - * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but - * table 4-41 gives 0x02101110, which includes the arm div insns. - */ - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; - cpu->isar.dbgdidr =3D 0x3515f005; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ -} - -static void cortex_a15_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a15"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; - cpu->midr =3D 0x412fc0f1; - cpu->reset_fpsid =3D 0x410430f0; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x11111111; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x02010555; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; - cpu->isar.dbgdidr =3D 0x3515f021; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); -} - -#ifndef TARGET_AARCH64 -/* - * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; - * this only needs to handle 32 bits, and need not care about KVM. - */ -static void arm_max_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cortex_a15_initfn(obj); - - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - -#ifdef CONFIG_USER_ONLY - /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. - */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - } -#endif -} -#endif - -#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ - -static const ARMCPUInfo arm_cpus[] =3D { -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, - { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, - { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, - { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, -#ifndef TARGET_AARCH64 - { .name =3D "max", .initfn =3D arm_max_initfn }, -#endif -#ifdef CONFIG_USER_ONLY - { .name =3D "any", .initfn =3D arm_max_initfn }, -#endif -#endif -}; - static Property arm_cpu_properties[] =3D { DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), @@ -2390,21 +2065,11 @@ static const TypeInfo arm_cpu_type_info =3D { =20 static void arm_cpu_register_types(void) { - const size_t cpu_count =3D ARRAY_SIZE(arm_cpus); - type_register_static(&arm_cpu_type_info); =20 #ifdef CONFIG_KVM type_register_static(&host_arm_cpu_type_info); #endif - - if (cpu_count) { - size_t i; - - for (i =3D 0; i < cpu_count; ++i) { - arm_cpu_register(&arm_cpus[i]); - } - } } =20 type_init(arm_cpu_register_types) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index fb07a336939..046e476f65f 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -15,6 +15,9 @@ #endif /* CONFIG_TCG */ #include "internals.h" #include "target/arm/idau.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/boards.h" +#endif =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -255,6 +258,236 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr =3D 1; } =20 +static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { + { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2AUXCR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void cortex_a8_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a8"; + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->midr =3D 0x410fc080; + cpu->reset_fpsid =3D 0x410330c0; + cpu->isar.mvfr0 =3D 0x11110222; + cpu->isar.mvfr1 =3D 0x00011111; + cpu->ctr =3D 0x82048004; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x1031; + cpu->isar.id_pfr1 =3D 0x11; + cpu->isar.id_dfr0 =3D 0x400; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x31100003; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01202000; + cpu->isar.id_mmfr3 =3D 0x11; + cpu->isar.id_isar0 =3D 0x00101111; + cpu->isar.id_isar1 =3D 0x12112111; + cpu->isar.id_isar2 =3D 0x21232031; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x00111142; + cpu->isar.dbgdidr =3D 0x15141000; + cpu->clidr =3D (1 << 27) | (2 << 24) | 3; + cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ + cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ + cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ + cpu->reset_auxcr =3D 2; + define_arm_cp_regs(cpu, cortexa8_cp_reginfo); +} + +static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { + /* + * power_control should be set to maximum latency. Again, + * default to 0 and set by private hook + */ + { .name =3D "A9_PWRCTL", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_control) }, + { .name =3D "A9_DIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D = 0, .opc2 =3D 1, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_diagnostic) }, + { .name =3D "A9_PWRDIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_diagnostic) }, + { .name =3D "NEONBUSY", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + /* TLB lockdown control */ + { .name =3D "TLB_LOCKR", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 2, + .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, + { .name =3D "TLB_LOCKW", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 4, + .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, + { .name =3D "TLB_VA", .cp =3D 15, .crn =3D 15, .crm =3D 5, .opc1 =3D 5= , .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + { .name =3D "TLB_PA", .cp =3D 15, .crn =3D 15, .crm =3D 6, .opc1 =3D 5= , .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + { .name =3D "TLB_ATTR", .cp =3D 15, .crn =3D 15, .crm =3D 7, .opc1 =3D= 5, .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + REGINFO_SENTINEL +}; + +static void cortex_a9_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a9"; + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); + /* + * Note that A9 supports the MP extensions even for + * A9UP and single-core A9MP (which are both different + * and valid configurations; we don't model A9UP). + */ + set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_CBAR); + cpu->midr =3D 0x410fc090; + cpu->reset_fpsid =3D 0x41033090; + cpu->isar.mvfr0 =3D 0x11110222; + cpu->isar.mvfr1 =3D 0x01111111; + cpu->ctr =3D 0x80038003; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x1031; + cpu->isar.id_pfr1 =3D 0x11; + cpu->isar.id_dfr0 =3D 0x000; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x00100103; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01230000; + cpu->isar.id_mmfr3 =3D 0x00002111; + cpu->isar.id_isar0 =3D 0x00101111; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x00111142; + cpu->isar.dbgdidr =3D 0x35141000; + cpu->clidr =3D (1 << 27) | (1 << 24) | 3; + cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ + cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ + define_arm_cp_regs(cpu, cortexa9_cp_reginfo); +} + +#ifndef CONFIG_USER_ONLY +static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + /* + * Linux wants the number of processors from here. + * Might as well set the interrupt-controller bit too. + */ + return ((ms->smp.cpus - 1) << 24) | (1 << 23); +} +#endif + +static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { +#ifndef CONFIG_USER_ONLY + { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, + .writefn =3D arm_cp_write_ignore, }, +#endif + { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void cortex_a7_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a7"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A7; + cpu->midr =3D 0x410fc075; + cpu->reset_fpsid =3D 0x41023075; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x11111111; + cpu->ctr =3D 0x84448003; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x02010555; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + * table 4-41 gives 0x02101110, which includes the arm div insns. + */ + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x10011142; + cpu->isar.dbgdidr =3D 0x3515f005; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ +} + +static void cortex_a15_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a15"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; + cpu->midr =3D 0x412fc0f1; + cpu->reset_fpsid =3D 0x410430f0; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x11111111; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x02010555; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x10011142; + cpu->isar.dbgdidr =3D 0x3515f021; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); +} + static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -695,6 +928,81 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) cc->gdb_core_xml_file =3D "arm-m-profile.xml"; } =20 +#ifndef TARGET_AARCH64 +/* + * -cpu max: a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; + * this only needs to handle 32 bits, and need not care about KVM. + */ +static void arm_max_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cortex_a15_initfn(obj); + + /* old-style VFP short-vector support */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + +#ifdef CONFIG_USER_ONLY + /* + * We don't set these in system emulation mode for the moment, + * since we don't correctly set (all of) the ID registers to + * advertise them. + */ + set_feature(&cpu->env, ARM_FEATURE_V8); + { + uint32_t t; + + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; + } +#endif /* CONFIG_USER_ONLY */ +} +#endif /* !TARGET_AARCH64 */ + static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "arm926", .initfn =3D arm926_initfn }, { .name =3D "arm946", .initfn =3D arm946_initfn }, @@ -708,6 +1016,10 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "arm1136", .initfn =3D arm1136_initfn }, { .name =3D "arm1176", .initfn =3D arm1176_initfn }, { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, + { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, + { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, + { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, + { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, @@ -738,6 +1050,12 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "pxa270-b1", .initfn =3D pxa270b1_initfn }, { .name =3D "pxa270-c0", .initfn =3D pxa270c0_initfn }, { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, +#ifndef TARGET_AARCH64 + { .name =3D "max", .initfn =3D arm_max_initfn }, +#endif +#ifdef CONFIG_USER_ONLY + { .name =3D "any", .initfn =3D arm_max_initfn }, +#endif }; =20 static const TypeInfo idau_interface_type_info =3D { --=20 2.26.2