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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/49] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU
Date: Fri, 5 Mar 2021 17:14:31 +0000
Message-Id: <20210305171515.1038-6-peter.maydell@linaro.org>
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From: Rebecca Cran <rebecca@nuviainc.com>
Enable FEAT_SSBS for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-4-rebecca@nuviainc.com
[PMM: fix typo causing compilation failure]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b8bc89e71fc..058672c9776 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2217,6 +2217,10 @@ static void arm_max_initfn(Object *obj)
t =3D cpu->isar.id_pfr0;
t =3D FIELD_DP32(t, ID_PFR0, DIT, 1);
cpu->isar.id_pfr0 =3D t;
+
+ t =3D cpu->isar.id_pfr2;
+ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1);
+ cpu->isar.id_pfr2 =3D t;
}
#endif
}
--=20
2.20.1