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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/49] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
Date: Fri, 5 Mar 2021 17:14:30 +0000
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From: Rebecca Cran <rebecca@nuviainc.com>
Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-3-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu64.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c255f1bcc39..f0a9e968c9c 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -674,6 +674,7 @@ static void aarch64_max_initfn(Object *obj)
=20
t =3D cpu->isar.id_aa64pfr1;
t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1);
+ t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
/*
* Begin with full support for MTE. This will be downgraded to MTE=
=3D0
* during realize if the board provides no tag memory, much like
@@ -723,6 +724,10 @@ static void aarch64_max_initfn(Object *obj)
u =3D FIELD_DP32(u, ID_PFR0, DIT, 1);
cpu->isar.id_pfr0 =3D u;
=20
+ u =3D cpu->isar.id_pfr2;
+ u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1);
+ cpu->isar.id_pfr2 =3D u;
+
u =3D cpu->isar.id_mmfr3;
u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->isar.id_mmfr3 =3D u;
--=20
2.20.1