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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 41/49] hw/arm/mps2-tz: Make RAM arrangement board-specific
Date: Fri, 5 Mar 2021 17:15:07 +0000
Message-Id: <20210305171515.1038-42-peter.maydell@linaro.org>
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The AN505 and AN521 have the same layout of RAM; the AN524 does not.
Replace the current hard-coding of where the RAM is and which parts
of it are behind which MPCs with a data-driven approach.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-17-peter.maydell@linaro.org
---
hw/arm/mps2-tz.c | 175 +++++++++++++++++++++++++++++++++++++----------
1 file changed, 138 insertions(+), 37 deletions(-)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index d20b2068868..26a52b72eec 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -66,12 +66,35 @@
#include "qom/object.h"
=20
#define MPS2TZ_NUMIRQ_MAX 92
+#define MPS2TZ_RAM_MAX 4
=20
typedef enum MPS2TZFPGAType {
FPGA_AN505,
FPGA_AN521,
} MPS2TZFPGAType;
=20
+/*
+ * Define the layout of RAM in a board, including which parts are
+ * behind which MPCs.
+ * mrindex specifies the index into mms->ram[] to use for the backing RAM;
+ * -1 means "use the system RAM".
+ */
+typedef struct RAMInfo {
+ const char *name;
+ uint32_t base;
+ uint32_t size;
+ int mpc; /* MPC number, -1 for "not behind an MPC" */
+ int mrindex;
+ int flags;
+} RAMInfo;
+
+/*
+ * Flag values:
+ * IS_ALIAS: this RAM area is an alias to the upstream end of the
+ * MPC specified by its .mpc value
+ */
+#define IS_ALIAS 1
+
struct MPS2TZMachineClass {
MachineClass parent;
MPS2TZFPGAType fpga_type;
@@ -82,6 +105,7 @@ struct MPS2TZMachineClass {
uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */
bool fpgaio_has_switches; /* Does FPGAIO have SWITCH register? */
int numirq; /* Number of external interrupts */
+ const RAMInfo *raminfo;
const char *armsse_type;
};
=20
@@ -89,12 +113,11 @@ struct MPS2TZMachineState {
MachineState parent;
=20
ARMSSE iotkit;
- MemoryRegion ssram[3];
- MemoryRegion ssram1_m;
+ MemoryRegion ram[MPS2TZ_RAM_MAX];
MPS2SCC scc;
MPS2FPGAIO fpgaio;
TZPPC ppc[5];
- TZMPC ssram_mpc[3];
+ TZMPC mpc[3];
PL022State spi[5];
ArmSbconI2CState i2c[4];
UnimplementedDeviceState i2s_audio;
@@ -126,6 +149,77 @@ static const uint32_t an505_oscclk[] =3D {
25000000,
};
=20
+static const RAMInfo an505_raminfo[] =3D { {
+ .name =3D "ssram-0",
+ .base =3D 0x00000000,
+ .size =3D 0x00400000,
+ .mpc =3D 0,
+ .mrindex =3D 0,
+ }, {
+ .name =3D "ssram-1",
+ .base =3D 0x28000000,
+ .size =3D 0x00200000,
+ .mpc =3D 1,
+ .mrindex =3D 1,
+ }, {
+ .name =3D "ssram-2",
+ .base =3D 0x28200000,
+ .size =3D 0x00200000,
+ .mpc =3D 2,
+ .mrindex =3D 2,
+ }, {
+ .name =3D "ssram-0-alias",
+ .base =3D 0x00400000,
+ .size =3D 0x00400000,
+ .mpc =3D 0,
+ .mrindex =3D 3,
+ .flags =3D IS_ALIAS,
+ }, {
+ /* Use the largest bit of contiguous RAM as our "system memory" */
+ .name =3D "mps.ram",
+ .base =3D 0x80000000,
+ .size =3D 16 * MiB,
+ .mpc =3D -1,
+ .mrindex =3D -1,
+ }, {
+ .name =3D NULL,
+ },
+};
+
+static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mp=
c)
+{
+ MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms);
+ const RAMInfo *p;
+
+ for (p =3D mmc->raminfo; p->name; p++) {
+ if (p->mpc =3D=3D mpc && !(p->flags & IS_ALIAS)) {
+ return p;
+ }
+ }
+ /* if raminfo array doesn't have an entry for each MPC this is a bug */
+ g_assert_not_reached();
+}
+
+static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms,
+ const RAMInfo *raminfo)
+{
+ /* Return an initialized MemoryRegion for the RAMInfo. */
+ MemoryRegion *ram;
+
+ if (raminfo->mrindex < 0) {
+ /* Means this RAMInfo is for QEMU's "system memory" */
+ MachineState *machine =3D MACHINE(mms);
+ return machine->ram;
+ }
+
+ assert(raminfo->mrindex < MPS2TZ_RAM_MAX);
+ ram =3D &mms->ram[raminfo->mrindex];
+
+ memory_region_init_ram(ram, NULL, raminfo->name,
+ raminfo->size, &error_fatal);
+ return ram;
+}
+
/* Create an alias of an entire original MemoryRegion @orig
* located at @base in the memory map.
*/
@@ -290,35 +384,23 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms=
, void *opaque,
const int *irqs)
{
TZMPC *mpc =3D opaque;
- int i =3D mpc - &mms->ssram_mpc[0];
- MemoryRegion *ssram =3D &mms->ssram[i];
+ int i =3D mpc - &mms->mpc[0];
MemoryRegion *upstream;
- char *mpcname =3D g_strdup_printf("%s-mpc", name);
- static uint32_t ramsize[] =3D { 0x00400000, 0x00200000, 0x00200000 };
- static uint32_t rambase[] =3D { 0x00000000, 0x28000000, 0x28200000 };
+ const RAMInfo *raminfo =3D find_raminfo_for_mpc(mms, i);
+ MemoryRegion *ram =3D mr_for_raminfo(mms, raminfo);
=20
- memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
-
- object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
- object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram),
+ object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC);
+ object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram),
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
/* Map the upstream end of the MPC into system memory */
upstream =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
- memory_region_add_subregion(get_system_memory(), rambase[i], upstream);
+ memory_region_add_subregion(get_system_memory(), raminfo->base, upstre=
am);
/* and connect its interrupt to the IoTKit */
qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
qdev_get_gpio_in_named(DEVICE(&mms->iotkit=
),
"mpcexp_status", i)=
);
=20
- /* The first SSRAM is a special case as it has an alias; accesses to
- * the alias region at 0x00400000 must also go to the MPC upstream.
- */
- if (i =3D=3D 0) {
- make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x0040000=
0);
- }
-
- g_free(mpcname);
/* Return the register interface MR for our caller to map behind the P=
PC */
return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
}
@@ -415,6 +497,28 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms,=
void *opaque,
return sysbus_mmio_get_region(s, 0);
}
=20
+static void create_non_mpc_ram(MPS2TZMachineState *mms)
+{
+ /*
+ * Handle the RAMs which are either not behind MPCs or which are
+ * aliases to another MPC.
+ */
+ const RAMInfo *p;
+ MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms);
+
+ for (p =3D mmc->raminfo; p->name; p++) {
+ if (p->flags & IS_ALIAS) {
+ SysBusDevice *mpc_sbd =3D SYS_BUS_DEVICE(&mms->mpc[p->mpc]);
+ MemoryRegion *upstream =3D sysbus_mmio_get_region(mpc_sbd, 1);
+ make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->ba=
se);
+ } else if (p->mpc =3D=3D -1) {
+ /* RAM not behind an MPC */
+ MemoryRegion *mr =3D mr_for_raminfo(mms, p);
+ memory_region_add_subregion(get_system_memory(), p->base, mr);
+ }
+ }
+}
+
static void mps2tz_common_init(MachineState *machine)
{
MPS2TZMachineState *mms =3D MPS2TZ_MACHINE(machine);
@@ -499,24 +603,17 @@ static void mps2tz_common_init(MachineState *machine)
qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0,
qdev_get_gpio_in(dev_splitter, 0));
=20
- /* The IoTKit sets up much of the memory layout, including
+ /*
+ * The IoTKit sets up much of the memory layout, including
* the aliases between secure and non-secure regions in the
- * address space. The FPGA itself contains:
- *
- * 0x00000000..0x003fffff SSRAM1
- * 0x00400000..0x007fffff alias of SSRAM1
- * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3
- * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices
- * 0x80000000..0x80ffffff 16MB PSRAM
- */
-
- /* The FPGA images have an odd combination of different RAMs,
+ * address space, and also most of the devices in the system.
+ * The FPGA itself contains various RAMs and some additional devices.
+ * The FPGA images have an odd combination of different RAMs,
* because in hardware they are different implementations and
* connected to different buses, giving varying performance/size
* tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
- * call the 16MB our "system memory", as it's the largest lump.
+ * call the largest lump our "system memory".
*/
- memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
=20
/*
* The overflow IRQs for all UARTs are ORed together.
@@ -549,9 +646,9 @@ static void mps2tz_common_init(MachineState *machine)
const PPCInfo an505_ppcs[] =3D { {
.name =3D "apb_ppcexp0",
.ports =3D {
- { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1=
000 },
- { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1=
000 },
- { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1=
000 },
+ { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x100=
0 },
+ { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x100=
0 },
+ { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x100=
0 },
},
}, {
.name =3D "apb_ppcexp1",
@@ -684,6 +781,8 @@ static void mps2tz_common_init(MachineState *machine)
=20
create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000);
=20
+ create_non_mpc_ram(mms);
+
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400=
000);
}
=20
@@ -734,6 +833,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, vo=
id *data)
mmc->fpgaio_num_leds =3D 2;
mmc->fpgaio_has_switches =3D false;
mmc->numirq =3D 92;
+ mmc->raminfo =3D an505_raminfo;
mmc->armsse_type =3D TYPE_IOTKIT;
}
=20
@@ -755,6 +855,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, vo=
id *data)
mmc->fpgaio_num_leds =3D 2;
mmc->fpgaio_has_switches =3D false;
mmc->numirq =3D 92;
+ mmc->raminfo =3D an505_raminfo; /* AN521 is the same as AN505 here */
mmc->armsse_type =3D TYPE_SSE200;
}
=20
--=20
2.20.1