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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/49] target/arm: Add support for FEAT_SSBS,
Speculative Store Bypass Safe
Date: Fri, 5 Mar 2021 17:14:29 +0000
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From: Rebecca Cran <rebecca@nuviainc.com>
Add support for FEAT_SSBS. SSBS (Speculative Store Bypass Safe) is an
optional feature in ARMv8.0, and mandatory in ARMv8.5.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210216224543.16142-2-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 15 ++++++++++++++-
target/arm/internals.h | 6 ++++++
target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++
target/arm/translate-a64.c | 12 ++++++++++++
4 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index efa1618c4d5..193a49ec7fa 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1206,6 +1206,7 @@ void pmu_init(ARMCPU *cpu);
#define SCTLR_TE (1U << 30) /* AArch32 only */
#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
+#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
@@ -1213,7 +1214,7 @@ void pmu_init(ARMCPU *cpu);
#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
-#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */
+#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
=20
#define CPTR_TCPAC (1U << 31)
#define CPTR_TTA (1U << 20)
@@ -1250,6 +1251,7 @@ void pmu_init(ARMCPU *cpu);
#define CPSR_IL (1U << 20)
#define CPSR_DIT (1U << 21)
#define CPSR_PAN (1U << 22)
+#define CPSR_SSBS (1U << 23)
#define CPSR_J (1U << 24)
#define CPSR_IT_0_1 (3U << 25)
#define CPSR_Q (1U << 27)
@@ -1312,6 +1314,7 @@ void pmu_init(ARMCPU *cpu);
#define PSTATE_A (1U << 8)
#define PSTATE_D (1U << 9)
#define PSTATE_BTYPE (3U << 10)
+#define PSTATE_SSBS (1U << 12)
#define PSTATE_IL (1U << 20)
#define PSTATE_SS (1U << 21)
#define PSTATE_PAN (1U << 22)
@@ -3915,6 +3918,11 @@ static inline bool isar_feature_aa32_dit(const ARMIS=
ARegisters *id)
return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) !=3D 0;
}
=20
+static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0;
+}
+
/*
* 64-bit feature tests via id registers.
*/
@@ -4169,6 +4177,11 @@ static inline bool isar_feature_aa64_dit(const ARMIS=
ARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0;
}
=20
+static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 05cebc8597c..f11bd326962 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -987,6 +987,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t=
features,
if (isar_feature_aa32_dit(id)) {
valid |=3D CPSR_DIT;
}
+ if (isar_feature_aa32_ssbs(id)) {
+ valid |=3D CPSR_SSBS;
+ }
=20
return valid;
}
@@ -1008,6 +1011,9 @@ static inline uint32_t aarch64_pstate_valid_mask(cons=
t ARMISARegisters *id)
if (isar_feature_aa64_dit(id)) {
valid |=3D PSTATE_DIT;
}
+ if (isar_feature_aa64_ssbs(id)) {
+ valid |=3D PSTATE_SSBS;
+ }
if (isar_feature_aa64_mte(id)) {
valid |=3D PSTATE_TCO;
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0e1a3b94211..fedcf2e739e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4450,6 +4450,24 @@ static const ARMCPRegInfo dit_reginfo =3D {
.readfn =3D aa64_dit_read, .writefn =3D aa64_dit_write
};
=20
+static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ return env->pstate & PSTATE_SSBS;
+}
+
+static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ env->pstate =3D (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS);
+}
+
+static const ARMCPRegInfo ssbs_reginfo =3D {
+ .name =3D "SSBS", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 6,
+ .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW,
+ .readfn =3D aa64_ssbs_read, .writefn =3D aa64_ssbs_write
+};
+
static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
const ARMCPRegInfo *ri,
bool isread)
@@ -8244,6 +8262,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_dit, cpu)) {
define_one_arm_cp_reg(cpu, &dit_reginfo);
}
+ if (cpu_isar_feature(aa64_ssbs, cpu)) {
+ define_one_arm_cp_reg(cpu, &ssbs_reginfo);
+ }
=20
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu=
)) {
define_arm_cp_regs(cpu, vhe_reginfo);
@@ -9463,6 +9484,14 @@ static void take_aarch32_exception(CPUARMState *env,=
int new_mode,
env->uncached_cpsr &=3D ~(CPSR_IL | CPSR_J);
env->daif |=3D mask;
=20
+ if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) {
+ if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) {
+ env->uncached_cpsr |=3D CPSR_SSBS;
+ } else {
+ env->uncached_cpsr &=3D ~CPSR_SSBS;
+ }
+ }
+
if (new_mode =3D=3D ARM_CPU_MODE_HYP) {
env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0;
env->elr_el[2] =3D env->regs[15];
@@ -9973,6 +10002,14 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *=
cs)
new_mode |=3D PSTATE_TCO;
}
=20
+ if (cpu_isar_feature(aa64_ssbs, cpu)) {
+ if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) {
+ new_mode |=3D PSTATE_SSBS;
+ } else {
+ new_mode &=3D ~PSTATE_SSBS;
+ }
+ }
+
pstate_write(env, PSTATE_DAIF | new_mode);
env->aarch64 =3D 1;
aarch64_restore_sp(env, new_el);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b23a8975d54..3aebdb4af9e 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1703,6 +1703,18 @@ static void handle_msr_i(DisasContext *s, uint32_t i=
nsn,
tcg_temp_free_i32(t1);
break;
=20
+ case 0x19: /* SSBS */
+ if (!dc_isar_feature(aa64_ssbs, s)) {
+ goto do_unallocated;
+ }
+ if (crm & 1) {
+ set_pstate_bits(PSTATE_SSBS);
+ } else {
+ clear_pstate_bits(PSTATE_SSBS);
+ }
+ /* Don't need to rebuild hflags since SSBS is a nop */
+ break;
+
case 0x1a: /* DIT */
if (!dc_isar_feature(aa64_dit, s)) {
goto do_unallocated;
--=20
2.20.1