From nobody Wed May 7 14:30:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1614967310; cv=none; d=zohomail.com; s=zohoarc; b=WarjR5K6L/MLAHQsYOsRBMyHPyhSn1ie3rcOAjJaJ2XUOgKgVB6+auhzQ4VNJ0h3PyfqtCFUlD/lYX/ucTSs8SkakXqKgM+mcQT8aBIu184i9w6GI+GqXy5g7FGVQ5Fs4kid99Ztvz8Lids5JSNkpBkapHVwnlLfXGEBg9JCI5o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614967310; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=odnFnvFATXhoBTl+xewJBMMPG98LsTMI0yC98xqMSes=; b=EC1xyGKIfHUegV2q2Adc1r/JqS66t/zW5DdwUGHCfr1+a1MDrl8bBMDFH/1mXacgRmi0Dh1RACIRatC4bV3kSP0cVibTW8OBwf/TTfmmyQlvvuDM1d9uwLS7lEaWNxqU9DdD0FsVgnD3vtlxH6eYWWkrlg3JZ3yotQit7933V+0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from=<peter.maydell@linaro.org> (p=none dis=none) header.from=<peter.maydell@linaro.org> Return-Path: <qemu-devel-bounces+importer=patchew.org@nongnu.org> Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614967310301654.6575594682779; Fri, 5 Mar 2021 10:01:50 -0800 (PST) Received: from localhost ([::1]:58054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from <qemu-devel-bounces+importer=patchew.org@nongnu.org>) id 1lIElp-0004AY-Iv for importer@patchew.org; Fri, 05 Mar 2021 13:01:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38464) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>) id 1lIE3V-0007Em-TS for qemu-devel@nongnu.org; Fri, 05 Mar 2021 12:16:07 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:39313) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>) id 1lIE3E-0007gk-7b for qemu-devel@nongnu.org; Fri, 05 Mar 2021 12:16:01 -0500 Received: by mail-wr1-x430.google.com with SMTP id b18so2899134wrn.6 for <qemu-devel@nongnu.org>; Fri, 05 Mar 2021 09:15:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id m132sm5942357wmf.45.2021.03.05.09.15.40 for <qemu-devel@nongnu.org> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Mar 2021 09:15:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=odnFnvFATXhoBTl+xewJBMMPG98LsTMI0yC98xqMSes=; b=nVSLp0pz/0P9aSP6BMl+H2YPpRyp6f/k2sgflOsXBZoeZPcgchYLwCYW4ryjP85r45 KzwZldVj2B07XUNlbbju76rJorxVRoZ1iwk3dxjd74IgmUBDsglN/lCvMYR0TKXDDcNe Ry/NwV69z/xLKodRneJD3OfCmIyi4Tr1/MU2ofZauIEPmxrJu9H1bJMifRQUAv75uw/r kazY/c5Sy5akMb2Pkd7jSPFBGgd7papOfHSFLxxd1QV5y8NYn0ps23WNxQNzYJtsBnLe zk2aZFZ1zU+MHcEP3M085xv3dTglQF5BFUVsM0tbf26v6XT7Y22OsRWkI4aTIJokO5Bk +LEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=odnFnvFATXhoBTl+xewJBMMPG98LsTMI0yC98xqMSes=; b=nZxxcPT7tnX+Q+4ATWGsMfvUE6ckJytLjdqsHXWiO9ZWrMAhqdQLICnQQ5qcXaHlst u/tzTl6uwr4riTmblm2/5+T3m+/BZUDH8hrkMPLcyfM/90OqK3XHmTkwvOV5LeL/n6nK Tzndfg9e7T8UugMWPggLeVR3aYvp4w1BqkoHmtDl5lXfUXZVXBs932dPcU/8Ln9akDpP /a4MCAk9WNRMGIG3pbFqQC+31gKsTh3Z73hc284Xh7ZjWWVuu4o9ZbR4acJ5vjBHHU40 7CFBLrSA5WjswGv6iiONxXOTDFwIgDiQDdr8o7JGBrBZKFl8g4FKmZjWiCtGdBeGgGJd 3tkQ== X-Gm-Message-State: AOAM532gdHlQuA7o8FFlQsmGAZ0cota52kfK+DeXYc1A+6mzkh+BxlsH E/yASL9vtcLoXe7r+WbwZGcuNghAGTHf2g== X-Google-Smtp-Source: ABdhPJwvgfXkXh6fI7oUOmQdg9z6NcWa++KYPJTUGSV3eE5oDnS4MS/w+rbQ0/HSnMdu4VSkVJ9qZw== X-Received: by 2002:a05:6000:1546:: with SMTP id 6mr10279747wry.398.1614964540537; Fri, 05 Mar 2021 09:15:40 -0800 (PST) From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 33/49] hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type Date: Fri, 5 Mar 2021 17:14:59 +0000 Message-Id: <20210305171515.1038-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210305171515.1038-1-peter.maydell@linaro.org> References: <20210305171515.1038-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+importer=patchew.org@nongnu.org> X-ZohoMail-DKIM: pass (identity @linaro.org) In the mps2-tz board code, we handle devices whose interrupt lines must be wired to all CPUs by creating IRQ splitter devices for the AN521, because it has 2 CPUs, but wiring the device IRQ directly to the SSE/IoTKit input for the AN505, which has only 1 CPU. We can avoid making an explicit check on the board type constant by instead creating and using the IRQ splitters for any board with more than 1 CPU. This avoids having to add extra cases to the conditionals every time we add new boards. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210215115138.20465-9-peter.maydell@linaro.org --- hw/arm/mps2-tz.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 87a05d2c19d..bfda944000e 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -139,17 +139,14 @@ static void make_ram_alias(MemoryRegion *mr, const ch= ar *name, static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ - MPS2TZMachineClass *mmc =3D MPS2TZ_MACHINE_GET_CLASS(mms); + MachineClass *mc =3D MACHINE_GET_CLASS(mms); =20 assert(irqno < MPS2TZ_NUMIRQ); =20 - switch (mmc->fpga_type) { - case FPGA_AN505: - return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irq= no); - case FPGA_AN521: + if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); - default: - g_assert_not_reached(); + } else { + return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irq= no); } } =20 @@ -437,10 +434,12 @@ static void mps2tz_common_init(MachineState *machine) sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); =20 /* - * The AN521 needs us to create splitters to feed the IRQ inputs - * for each CPU in the SSE-200 from each device in the board. + * If this board has more than one CPU, then we need to create splitte= rs + * to feed the IRQ inputs for each CPU in the SSE from each device in = the + * board. If there is only one CPU, we can just wire the device IRQ + * directly to the SSE's IRQ input. */ - if (mmc->fpga_type =3D=3D FPGA_AN521) { + if (mc->max_cpus > 1) { for (i =3D 0; i < MPS2TZ_NUMIRQ; i++) { char *name =3D g_strdup_printf("mps2-irq-splitter%d", i); SplitIRQ *splitter =3D &mms->cpu_irq_splitter[i]; --=20 2.20.1