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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 15/49] target/arm/cpu: Update coding style to make
checkpatch.pl happy
Date: Fri, 5 Mar 2021 17:14:41 +0000
Message-Id: <20210305171515.1038-16-peter.maydell@linaro.org>
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From: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
We will move this code in the next commit. Clean it up
first to avoid checkpatch.pl errors.
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Message-id: 20210221222617.2579610-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2666d4363d0..6facb66f4d2 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1972,7 +1972,8 @@ static void cortex_a8_initfn(Object *obj)
}
=20
static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D {
- /* power_control should be set to maximum latency. Again,
+ /*
+ * power_control should be set to maximum latency. Again,
* default to 0 and set by private hook
*/
{ .name =3D "A9_PWRCTL", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =
=3D 0, .opc2 =3D 0,
@@ -2009,7 +2010,8 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_EL3);
- /* Note that A9 supports the MP extensions even for
+ /*
+ * Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
*/
@@ -2046,7 +2048,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, con=
st ARMCPRegInfo *ri)
{
MachineState *ms =3D MACHINE(qdev_get_machine());
=20
- /* Linux wants the number of processors from here.
+ /*
+ * Linux wants the number of processors from here.
* Might as well set the interrupt-controller bit too.
*/
return ((ms->smp.cpus - 1) << 24) | (1 << 23);
@@ -2093,7 +2096,8 @@ static void cortex_a7_initfn(Object *obj)
cpu->isar.id_mmfr1 =3D 0x40000000;
cpu->isar.id_mmfr2 =3D 0x01240000;
cpu->isar.id_mmfr3 =3D 0x02102211;
- /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
+ /*
+ * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
* table 4-41 gives 0x02101110, which includes the arm div insns.
*/
cpu->isar.id_isar0 =3D 0x02101110;
--=20
2.20.1