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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id t14sm5422872wru.64.2021.03.05.08.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Mar 2021 08:21:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wPcnqGU4UTHM8Jk/Lrqw/LIFbJVS4CYQnfKcUElhSEw=; b=aLJjVx8mUzS2bizwLYi+Xa6EajYA53wSDFn7GVS1jSOYnZEXDJuwUHMjoCZlCoRhRU WAXLaTTASD0vFKT29VN8G/5tpmFC1J2GcAU01HgkrcqvWqq6M7yhEdP3lLEVshneoKHQ 7H6ZZYPF9fxbna3T5X3GakxUiKmgBUkmJBnVtm3Xj86d5jcCEsPa7ueWIq4gkIPyfyI6 03DYRAwV/TJY7LuGPXeeku1d+UTnOakTS7v8jrpI7znrIcOBNENxz2MgQe7ErY5lPRjB YjkcxUl1e4Js36fUD4YtNRBeygJi8FXO22rwLwUudmQ0ATeYbl3YaWELW0Z2/m3Nxwmr RKhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wPcnqGU4UTHM8Jk/Lrqw/LIFbJVS4CYQnfKcUElhSEw=; b=Ezs6vbIp6ehzszYr5NQD0yinV1Svzglfr04lXJNbomHULPhwXelNX9LPuAUyWy2jb6 U3laY70d5pTdckkOdouMzAVB0YMEe3dbxpzEMmCTPUdv+elJN3OtTOH+qry1U/FzvtRV ecw+R++gdjEH049GTkyjB3sAjOn8Hq2sC7dEBpTgDndpQ6uj+vshd+uyMPvYUS8cS5bR i/iMsRzldoxvwPdJnIkpbHsHpv1AZGdJ/EuB9u8mYfzY9vO91nYlG4JH/blc+3PPw+P1 9E6sutN+7qCdR1qnzvcCcG1FqFFXpQPogwT1d7lm45NJ4BvYn1o+SUZRcZP0rymJCa0h oFdw== X-Gm-Message-State: AOAM532GK0PsvSRkw/SK3N+wXJRJ7kFnnnr64fzVV8fz1x3k20dq+vvH XbIDVKo8da6rDXNJp7UC2+I= X-Google-Smtp-Source: ABdhPJyxntFx1LgxJiEpTvmXcEslXLMHAqvEVXjR+fBT+qB/NRotYpobdXDvpHDNG2SKQIFW9M+Q8g== X-Received: by 2002:a1c:dd44:: with SMTP id u65mr9723008wmg.87.1614961283506; Fri, 05 Mar 2021 08:21:23 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aurelien Jarno , Aleksandar Rikalo Subject: [PATCH 3/6] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats Date: Fri, 5 Mar 2021 17:21:04 +0100 Message-Id: <20210305162107.2233203-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210305162107.2233203-1-f4bug@amsat.org> References: <20210305162107.2233203-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Fix the following typos: - GT_PCI1_CFGDATA is not a timer register but a PCI one, - zero-padding flag is out of the format Fixes: 641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of de= bug printf()") Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/gt64xxx_pci.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 99b1690af19..8ff31380d74 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -463,7 +463,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Read-only registers, do nothing */ qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Read-only register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -473,7 +473,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Read-only registers, do nothing */ qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Read-only register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -515,7 +515,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Not implemented */ qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented device register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -528,7 +528,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Read-only registers, do nothing */ qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Read-only register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -565,7 +565,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Not implemented */ qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented DMA register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -578,7 +578,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* Not implemented */ qemu_log_mask(LOG_UNIMP, "gt64120: Unimplemented timer register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; =20 @@ -621,8 +621,8 @@ static void gt64120_writel(void *opaque, hwaddr addr, case GT_PCI1_CFGDATA: /* not implemented */ qemu_log_mask(LOG_UNIMP, - "gt64120: Unimplemented timer register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "gt64120: Unimplemented PCI register write " + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; case GT_PCI0_CFGADDR: @@ -682,7 +682,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, default: qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Illegal register write " - "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n", + "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n", saddr << 2, size, size << 1, val); break; } @@ -958,7 +958,7 @@ static uint64_t gt64120_readl(void *opaque, val =3D s->regs[saddr]; qemu_log_mask(LOG_GUEST_ERROR, "gt64120: Illegal register read " - "reg:0x03%x size:%u value:0x%0*x\n", + "reg:0x%03x size:%u value:0x%0*x\n", saddr << 2, size, size << 1, val); break; } --=20 2.26.2