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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id i26sm1289891wmb.18.2021.03.04.14.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sZzqDSzbsexD9Zh3aq/wd1p0b53KS/Yn8zf4kVHZSu8=; b=pZ6S1AEWRk7U9b63+cejO+/j9dwOxzbhBvb/obwzh3d8QeY5JA7h7LT5i53dILRgqi BVTqFHfXSNGXLmcRGw5Hi6i4U6iU9W7CO7nOcC2ohPO1noOUzcj6PoSeQWb6g+gueQO7 3g4z6jr4jKb28VZVuUILRZV7iEnGjGda05d8N89Ay+Cxp4KppuDempl3wlXk4tgZNvJ2 zevCyH7Ny/uYfEK5PxTo4fJ3MQ9DuriYqWJ9yc3p+VQSFk+VfUBwdcTYNRwaPJxpzfd/ LinY5lXzDUN5x7Vk/ejifGcZpYJZQK4k1sstoXZmSBmv+sfv0C7HsfjF2HsFSw8l0QQM GEFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sZzqDSzbsexD9Zh3aq/wd1p0b53KS/Yn8zf4kVHZSu8=; b=c//Rgqjr5znrBMnxXew4gsJYlQJ55xoSNE0v002wkm30oXKYFCkgpGtPEqHU4wEO1S WoZkTg4lJVum3P45BC6FvK+7crRVkRie4CwOm/5Kkc4sXGUlDAdEDJyFSEyU/vd7Dg9Z 1BxRIQp4DcJVBUPHdrXriHyCWiFnTg8uy9giJq/khOVPDkMkzkYafurFZvGxL1UdMoBz Z9n/V0/SDDoOvHfLgEIyrCNlJMmr76eChKWSl78PQ9QNkuOxoWSTp1MSPR6pU1IA2Gtp zVQNCe0m5BtX03ku5jdMynMLSME3XIpZIB+4fb8KhdWdAkpTAuL+HUzq1A8phkuLLIR7 ivOQ== X-Gm-Message-State: AOAM5323gE2UI6KOPaf16Gi3xU446jDeibb1RXlzT2H40LqfNm8w7+Mf FRfKrEpOWOKYWkeCm9v/5ME= X-Google-Smtp-Source: ABdhPJytszF6Gh7yIRnn5zIm8ZcLxWTULeMm+RZerO6Mj2TnpXYLHT76N4M87apDUrJ+R7srJ2unTw== X-Received: by 2002:adf:f889:: with SMTP id u9mr6073330wrp.180.1614896611296; Thu, 04 Mar 2021 14:23:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , David Gibson , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Thomas Huth , Laurent Vivier , Cornelia Huck , Greg Kurz , Paolo Bonzini , qemu-arm@nongnu.org, Eduardo Habkost , Peter Maydell , Richard Henderson , qemu-riscv@nongnu.org, Claudio Fontana , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG Date: Thu, 4 Mar 2021 23:23:16 +0100 Message-Id: <20210304222323.1954755-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration to CONFIG_TCG. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Claudio Fontana Reviewed-by: David Hildenbrand --- include/sysemu/tcg.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index 00349fb18a7..fddde2b6b9a 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -8,13 +8,15 @@ #ifndef SYSEMU_TCG_H #define SYSEMU_TCG_H =20 +#ifndef CONFIG_TCG +#define tcg_enabled() 0 +#else + void tcg_exec_init(unsigned long tb_size, int splitwx); =20 -#ifdef CONFIG_TCG extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) -#else -#define tcg_enabled() 0 -#endif + +#endif /* CONFIG_TCG */ =20 #endif --=20 2.26.2 From nobody Fri May 17 11:58:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614896618; cv=none; d=zohomail.com; s=zohoarc; b=H1bTBN0E3PaSX63SSkuJm0h2itQrYZhXWYE1kPNekIHuTqbWpjVR06L6mWEaCFJNaTvgnWXlzQ5A2fZ/x5deNKvCk37natcS31xH/7rGXqX5MSfrsJCJowigcNPbgiu+tLu3XF+4cskEAJ4mkrNxi82uXBpajzqt8sHEeohabVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614896618; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OUZUt6DUDETGfeYoWkRPY1ImgFxPl3GPkcbxoc9krNo=; b=D6wdboiUzx1AWQvH0QJR6pHSb2dfs3TZ3SPjOL5ZI4muBi2xffPXW3Dgyi0OS09MheXIOWc6SRSUMfD9gHgCytK6JsVxAPNU0VRM88XFNG/iBe1gf1NuDE1oVEMNhwBqCS/fKfCO4InvnC1o6L/a75A0dP4iIhPujpMOqzk5jaM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.zohomail.com with SMTPS id 1614896618089710.356313536179; Thu, 4 Mar 2021 14:23:38 -0800 (PST) Received: by mail-wm1-f47.google.com with SMTP id k66so11159513wmf.1 for ; Thu, 04 Mar 2021 14:23:37 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id d13sm1058581wro.23.2021.03.04.14.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OUZUt6DUDETGfeYoWkRPY1ImgFxPl3GPkcbxoc9krNo=; b=UWQyP0l8uyZKNzmMYvUOIW1n9rnYeebf87oLY66bGNcJPc/WT9d+sCaWgS5LOEasCZ KCQZLazOPSW9RjHHtS8Nnuq4iUGbzC2rSjtt1hRvs9xdL4RvNLN4+kQtbjABSCugpnoO TSnqXY3R26ztLy+AG3I9AJzYoD2HEhJsphdG6OhnVAp2Xlj4GE3h9Mi7x6VsZXoLyQ6z 76lZEtmKUvnt673nEJGgiFYHerS5bq+9vt5Hk9FOK+P4pfYwdGUIoBbgAkstYXmnQ8w1 6JF9AvG/e5MoSDh+q0MF8+tJ5R33fwIdskaXZ+P3Ha4oKozJ9M0+/SLav6vd9xCP/7IO CdJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=OUZUt6DUDETGfeYoWkRPY1ImgFxPl3GPkcbxoc9krNo=; b=LxyFifSL+g1pKobw3NKmzGeIK4YhSpivMQuDFtZB0Jvo4FGMkKyYmDddX+NWX1BTFS cIvYL+QKZg0i/DHRUQ0GN6pEAgCsZbaOLCV53Er11ZcZejLzwpezk+CTgfGqB/Pwrn2l KpY7FRqL2z+1oSc9nSnbvjEKK3nubgHgaMFwunoCzdGIBgtKMFQyZzgUnOvKl0tRuG1Q ggIlLpPyGntr9dez1ztxLih3XCjWO6omrdkhKs68WRMCbkjHVhLeh2FHXuO1RHMFsmZd ILM0Zkyn5gesmqOih7eJInBj69uwzwM1x/zxNaZ9eaKHBcjHdr0tx96ZopTHT79dsB7w VgcA== X-Gm-Message-State: AOAM532yJeZoHz7jNn14s1xjWggW7zmFcfb9qWqSGm5oEPJE/efqvpAK 605GMKOI2mFceny+PIhbNVI= X-Google-Smtp-Source: ABdhPJxtwTdTVXcDZSftstwccFkSDRQ/eq3WDttHC5Vx/OfQwqayes3YoV41fMb5TqwzjbWn/uResQ== X-Received: by 2002:a05:600c:4ba2:: with SMTP id e34mr5923244wmp.121.1614896616354; Thu, 04 Mar 2021 14:23:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , David Gibson , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Thomas Huth , Laurent Vivier , Cornelia Huck , Greg Kurz , Paolo Bonzini , qemu-arm@nongnu.org, Eduardo Habkost , Peter Maydell , Richard Henderson , qemu-riscv@nongnu.org, Claudio Fontana , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum Subject: [RFC PATCH v2 2/8] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG Date: Thu, 4 Mar 2021 23:23:17 +0100 Message-Id: <20210304222323.1954755-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) qemu_tcg_mttcg_enabled() shouldn't not be used outside of TCG, restrict its declaration. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Claudio Fontana --- include/hw/core/cpu.h | 9 --------- include/sysemu/tcg.h | 9 +++++++++ accel/tcg/cpu-exec.c | 1 + tcg/tcg.c | 1 + 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e3648338dfe..1376e496a3f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -454,15 +454,6 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cp= u) } } =20 -/** - * qemu_tcg_mttcg_enabled: - * Check whether we are running MultiThread TCG or not. - * - * Returns: %true if we are in MTTCG mode %false otherwise. - */ -extern bool mttcg_enabled; -#define qemu_tcg_mttcg_enabled() (mttcg_enabled) - /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index fddde2b6b9a..c16c13c3c69 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -17,6 +17,15 @@ void tcg_exec_init(unsigned long tb_size, int splitwx); extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) =20 +/** + * qemu_tcg_mttcg_enabled: + * Check whether we are running MultiThread TCG or not. + * + * Returns: %true if we are in MTTCG mode %false otherwise. + */ +extern bool mttcg_enabled; +#define qemu_tcg_mttcg_enabled() (mttcg_enabled) + #endif /* CONFIG_TCG */ =20 #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 16e4fe3ccd8..7e67ade35b9 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -39,6 +39,7 @@ #include "hw/i386/apic.h" #endif #include "sysemu/cpus.h" +#include "sysemu/tcg.h" #include "exec/cpu-all.h" #include "sysemu/cpu-timers.h" #include "sysemu/replay.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 63a12b197bf..4a4dac0bb3e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -65,6 +65,7 @@ #include "elf.h" #include "exec/log.h" #include "sysemu/sysemu.h" +#include "sysemu/tcg.h" =20 /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ --=20 2.26.2 From nobody Fri May 17 11:58:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614896623; cv=none; d=zohomail.com; s=zohoarc; b=EUAL72uj16XWTH+AlkMTsv5IpoL9vqPJNfCji1DqL13i52u3Y2soG50oM3g6CKBtWBo/7MveKIRIaC+A4k/t00UYMJAxZVpDBA42ZE4Lrs/6nvI3ayzlJO9x3KKUvkSCP5R1n12R7g6A+t0Myl9OIXlD7MgAQZZyBJ6qAb1xWxA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614896623; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Sy2H6EddRIKWB1GSb3aR2E61qw1Oji422a4IED5nUFk=; b=ItbtNbNl3r7zJ7yoFk/d/DfLJj1Dq1MiN7NR/nHVXc6DtJhpECb3qxmC+ERAbt38zReS87FODOWTQMICcifctjRtc1Mh41u+MUMp1Z0VdxU/5djYGbjtt6toHPuevQ+UeJcn6liN85nD8eDaOmREFtRvS+3yC3VYCJfyzAwmZIU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.zohomail.com with SMTPS id 1614896622998915.8448852318055; Thu, 4 Mar 2021 14:23:42 -0800 (PST) Received: by mail-wr1-f45.google.com with SMTP id a18so21168372wrc.13 for ; Thu, 04 Mar 2021 14:23:42 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id y9sm907051wrm.88.2021.03.04.14.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sy2H6EddRIKWB1GSb3aR2E61qw1Oji422a4IED5nUFk=; b=mhBQEJUjEnB/YIfFNMe++iCNWz0lJM5t4I45IW7gGw6pz4iPRjTY1kAOLOwqDZL7ot Wx6nDJEaMvdheasiN9HYKocpqofzOsYa6I9yN1m8YReMdvKynY8+wujDG65Dj6IX098p k6JYfFDivampkjG3tsfEA1KmoNyGSfrG/M8MigxnAEPnhKwY4+/zP1jjPXo7acXe4AYA TOwZP3ZM17VgTe1jvAEzCBdzewFmVfSuRLmAClJ3jCN6LTWOnBm1hmpgbip1RqQ0BYyP xBrgN+hVJKOAwXYAwIDNGgunDGyGfP/KSz6SAnwFUq9yzlHIYY38BES3bHNHoQAUNUie JDhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Sy2H6EddRIKWB1GSb3aR2E61qw1Oji422a4IED5nUFk=; b=nsX95dB+t+KMl/MAIoRpYtG8ABa5XGEtv0clsFFwjwrG4ExpYtwUsITKxbY2rLXt0D bR3kDVXDcMXrrTCIOAPs10bvLc2rjdPeumQT/BfQ8mdo5WJdncicwsHvWRAHu8AaxYSi qtStqx3ry8iZMdagQXxZD6UxYf5BuUo4/rjDl0wKoUyioVzTBsVWLnUtkplIiBVObHBU MoGXyzK7fuX5jFVVgob7poj4kTFQQ2PM7kUUmobG5l2RdWgyIJn7ZMB8r0vQaoPslcZD lcNBEYkH9nUlPlYGacZIp1T7gITgQJVGgVIXmOOPZNPlS//veh39NPMu9j6jO6RI7KhL tZBw== X-Gm-Message-State: AOAM532ekettb/sE77Ylv62Jbla7+e9eqS4FX/Dh2NPFKIPRjDKq0zK7 HCHV6fdFJuTcTaOnLWRk2d0= X-Google-Smtp-Source: ABdhPJwlQm7jfaSajGyc50qshmJurkslHzterzoVGYe4xgchSIPRbdA//wesm2yYXPzLC2j1BiGmUg== X-Received: by 2002:adf:ed49:: with SMTP id u9mr6088176wro.337.1614896621247; Thu, 04 Mar 2021 14:23:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , David Gibson , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Thomas Huth , Laurent Vivier , Cornelia Huck , Greg Kurz , Paolo Bonzini , qemu-arm@nongnu.org, Eduardo Habkost , Peter Maydell , Richard Henderson , qemu-riscv@nongnu.org, Claudio Fontana , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 3/8] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work Date: Thu, 4 Mar 2021 23:23:18 +0100 Message-Id: <20210304222323.1954755-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) There is only one CPUClass::has_work() ARM handler: arm_cpu_has_work(). Avoid a dereference by declaring it in "internals.h" and call it directly in the WFI helper. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Claudio Fontana --- target/arm/internals.h | 1 + target/arm/cpu.c | 2 +- target/arm/op_helper.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 05cebc8597c..1930be08828 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -172,6 +172,7 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); =20 +bool arm_cpu_has_work(CPUState *cs); #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5e018b2a732..6d2d9f2100f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -76,7 +76,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, } #endif /* CONFIG_TCG */ =20 -static bool arm_cpu_has_work(CPUState *cs) +bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 65cb37d088f..a4da6f4fde8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -289,7 +289,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) CPUState *cs =3D env_cpu(env); int target_el =3D check_wfx_trap(env, false); =20 - if (cpu_has_work(cs)) { + if (arm_cpu_has_work(cs)) { /* Don't bother to go into our "low power state" if * we would just wake up immediately. */ --=20 2.26.2 From nobody Fri May 17 11:58:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614896628; cv=none; d=zohomail.com; s=zohoarc; b=WJYbdHVUtrhAfAxDs/1QysyJ7dJawen2Hfki/1zMWd34HFXdw26TPaaGnwR+K3yptRsnRaULZkHI6kZwGCFoMVgNDgpDfVsnyDr6UksDUq3BFUN/xgW3BaRSgnMt85+XzwB8h+VGpzvlpKsHLTTCrVrJU8V5FTFoDlOVEQCs0qI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614896628; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+rqeUSg2fiW/MftHzeY++j7Aj9yk8dsEiDYp+lRnH1c=; b=N9ropveizfOZisC1MHmLdhMZh7/4UoxmAv5kJvCOGpFhmKy07UfxfXj9TS5JmW9KRCosfj1SX6VJVDXyWlQKq1keIiwc9xJJ5t6Ysz6v/UHC7NAKZCJCe4vbFnpAWTEMsDMqiUjEWwzpxg9JWkDMjqMB6jcMpssUIRdstKWhvfM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.zohomail.com with SMTPS id 1614896628155302.1037513805386; Thu, 4 Mar 2021 14:23:48 -0800 (PST) Received: by mail-wm1-f44.google.com with SMTP id l22so9389927wme.1 for ; Thu, 04 Mar 2021 14:23:47 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 3sm1162274wry.72.2021.03.04.14.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+rqeUSg2fiW/MftHzeY++j7Aj9yk8dsEiDYp+lRnH1c=; b=OOdbFZ3AqgZkXVIv+J10pQn1XsyaoAYbkMORcRS7S/KbOJ4VSw3ZqOa1gcj+mFkYT5 CeTJC7kMsKIUKqtrc1cLSs6ag0pKQhWPXeeMcMCS1lLITsEV9RHZqjiY9Op/96wgtTNK tZGghF+IwTdq8Y15SeAXpDmHCfMruYiMABL1XpvuU0w1twQWFe/dlMy7YYBP5WDTtaQw 2yRhfHQX2R60nsIyMO1UBSAdOKL23MyEnKqe9fgZ4hs/5KLUXXObr7VJXjhl3qVumlTU eu34/v9omzWDN4/dDT++xEXPKyAz6IzjVIa1qytss59q5pBSZqFhgtu/btW0SUsQRze0 oL2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+rqeUSg2fiW/MftHzeY++j7Aj9yk8dsEiDYp+lRnH1c=; b=sPV0CFLTnCFts9rjS+63Ou8EmZOUV3c4rDi2sOdAG6AshmLJihAt1/UEutwGDlPSdn BU0ltG/c3RlIX5mqs+ToqO4LW7SDPNcpMD8tFL0zNabGKIBLtCtwsGC4yDzGQo/MBZXf VHq1aTBlsTif+1UIXg9L09p1FIEUZ0Jyq65TLzovxAygEt/MQiImSfiA+dKUD4hUKP5j N8DKaa9fdLhkgp5LhcwLZKKN8LOku0UsbKRUBYSGHqLlYj2rYI+BFwK3jg+fTFKzxzGC qpJQC98eftmbokAtgtKLsFSHqOXcQv8iYMLblrNPBOK1PBT4KirZOVgcIMG9CsfSKQZE fTCg== X-Gm-Message-State: AOAM531mbVRWhKwZBjCzhHP0LhIf1glVU/bbob/apooIa9qeopnBgJKP k0slL6UsAK2/Z7pZSQdOv1M= X-Google-Smtp-Source: ABdhPJzOo7zZJspFMey4e0BrxmgD6sGrw/fGdi9w+8Brl5uG9ELjlvTZp8m6kGMO6R1vYn8QLdFc4A== X-Received: by 2002:a05:600c:2f08:: with SMTP id r8mr5905655wmn.95.1614896626435; Thu, 04 Mar 2021 14:23:46 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , David Gibson , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Thomas Huth , Laurent Vivier , Cornelia Huck , Greg Kurz , Paolo Bonzini , qemu-arm@nongnu.org, Eduardo Habkost , Peter Maydell , Richard Henderson , qemu-riscv@nongnu.org, Claudio Fontana , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 4/8] target/s390x: Move s390_cpu_has_work to excp_helper.c Date: Thu, 4 Mar 2021 23:23:19 +0100 Message-Id: <20210304222323.1954755-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We will restrict the s390_cpu_has_work() function to TCG. First declare it in "internal.h" and move it to excp_helper.c. Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/s390x/internal.h | 1 + target/s390x/cpu.c | 17 ----------------- target/s390x/excp_helper.c | 18 ++++++++++++++++++ 3 files changed, 19 insertions(+), 17 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 11515bb6173..7184e38631c 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -263,6 +263,7 @@ ObjectClass *s390_cpu_class_by_name(const char *name); =20 =20 /* excp_helper.c */ +bool s390_cpu_has_work(CPUState *cs); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index feaf2a6d08f..d57f69e7f7d 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -56,23 +56,6 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr =3D value; } =20 -static bool s390_cpu_has_work(CPUState *cs) -{ - S390CPU *cpu =3D S390_CPU(cs); - - /* STOPPED cpus can never wake up */ - if (s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_LOAD && - s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_OPERATING) { - return false; - } - - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - - return s390_cpu_has_int(cpu); -} - #if !defined(CONFIG_USER_ONLY) /* S390CPUClass::load_normal() */ static void s390_cpu_load_normal(CPUState *s) diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index ce16af394b1..64923ffb83a 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -28,12 +28,30 @@ #include "hw/s390x/ioinst.h" #include "exec/address-spaces.h" #include "tcg_s390x.h" +#include "qapi/qapi-types-machine.h" #ifndef CONFIG_USER_ONLY #include "sysemu/sysemu.h" #include "hw/s390x/s390_flic.h" #include "hw/boards.h" #endif =20 +bool s390_cpu_has_work(CPUState *cs) +{ + S390CPU *cpu =3D S390_CPU(cs); + + /* STOPPED cpus can never wake up */ + if (s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_LOAD && + s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_OPERATING) { + return false; + } + + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + + return s390_cpu_has_int(cpu); +} + void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra) { --=20 2.26.2 From nobody Fri May 17 11:58:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614896633; cv=none; d=zohomail.com; s=zohoarc; b=iHuBvOseND8HMaIZYwJ9oUM48qCvIpaLBj11zboIzmmkS+SV7vmlV/3kPGOkm1+7DC5r9IUjdka+9TFhhfH8hoOdVtqRp+93P+YE1IuH8JfnWg8R3UmdY06BeZvqOUModA122fsFn/0sBZwji6z5LcdYhvfKOt+3o6/JIMu+wHc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614896633; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D6LLQzNZyfmEhNL83oc33kVYOp47IlGJ59yVOiNpnRg=; b=FPnj/0Uhw8xlw6TmeA9x/Obu0I36S0q2W+sAvLCGl5DajnHaA3r1yw07M+Cc29LuJaN/rE/ZAOj3/WFNimg7GUkBGxfGCWFhaY2ZZ5FRAzQ2EiCqPgrL/NAUQUD9U4CJWxEcoFLAmKeb59ET1DLtCJ/AyjGiQ4RPxqN+6dIppDE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.zohomail.com with SMTPS id 1614896633108145.01886830205956; Thu, 4 Mar 2021 14:23:53 -0800 (PST) Received: by mail-wm1-f48.google.com with SMTP id k66so11159915wmf.1 for ; Thu, 04 Mar 2021 14:23:52 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id m9sm1035239wro.52.2021.03.04.14.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D6LLQzNZyfmEhNL83oc33kVYOp47IlGJ59yVOiNpnRg=; b=ZEreaPaFQBeiuBRNQ2OdnjMAh9JP6F2sp+ucDXyAI7serdBvnEP0GeJdpO1aAGOIeI mIVkrONeWtvTb1SMlHLcC3sGhPN3obe0dPFCNXlQDxIXdWO3p3i0+75JNV1bSQ3SXq+Z YHhbanE6DrpECs+Gf7JQFnk1TcIRvJF8JXp6USUYHyeIUAUv1YMCAxZOBy6LY6sh2+vb v4Nd21MM9wbNeiCvo7RmagK5R3DNdDj4WFkWsU+1u17WCATCjnuqddqsP8euBUJlYwbE 4lHfmE2bwxDXaii4j1U2dCT4sO84hu9SR1qdIVEDLB0K9amKQ6g8RbArTEXXP6kLsuc7 n2GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=D6LLQzNZyfmEhNL83oc33kVYOp47IlGJ59yVOiNpnRg=; b=U6/SrlmUWmEOTkkh7V218TqYjxBBChWCRHoeuIQwA7nnS9t2GD9/xDl+i4DLc9vP4R VrpmfataT4Hm9AvkgHO/6WrFxfup6xPgWd6Y0U1SBXiJ8JC2R943IKtuFEJiF6RUlK7l QnRqARY7aiL8zuzHFxcOark5fk2IbcTIiFSuwuNLF+P8t6ibdzC/QCF1bGOOiuFzYYxR JfogAzxZaw6mFJElov9DN00PL9z1SThdS2sQPFGsTj8r76mOBIqnN340JEUxXqsuNjdU OchkAcPx3qdBYOIrMC3pUeUMNlkAMmPTAUFpq4PCplPc6NBJukExGPKZiDmVNNhnWh7c N9dQ== X-Gm-Message-State: AOAM533JfQeKLJdaCDqKeoOaU3u3VbyH2lFhub8QB6K2LFZc+3wDrHZM HZ2vyrt2L90ogsV8c4diikk= X-Google-Smtp-Source: ABdhPJwnMQsUEYN2vxJhPn71ExiDnnAWuGzag6QAtfQlcdTNm3SuZmB5gnJwAeak8v++6xxILl5L3w== X-Received: by 2002:a1c:6309:: with SMTP id x9mr5873815wmb.62.1614896631437; Thu, 04 Mar 2021 14:23:51 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , David Gibson , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Thomas Huth , Laurent Vivier , Cornelia Huck , Greg Kurz , Paolo Bonzini , qemu-arm@nongnu.org, Eduardo Habkost , Peter Maydell , Richard Henderson , qemu-riscv@nongnu.org, Claudio Fontana , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs Date: Thu, 4 Mar 2021 23:23:20 +0100 Message-Id: <20210304222323.1954755-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) POWER CPUs have specific CPUClass::has_work() handlers. In preparation of moving this field to TCGCPUOps, we need to duplicate the current ppc_tcg_ops structure for the POWER cpus. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/translate_init.c.inc | 69 +++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 80239077e0b..fe76d0b3773 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -48,6 +48,11 @@ /* #define PPC_DUMP_SPR_ACCESSES */ /* #define USE_APPLE_GDB */ =20 +static const struct TCGCPUOps power7_tcg_ops; +static const struct TCGCPUOps power8_tcg_ops; +static const struct TCGCPUOps power9_tcg_ops; +static const struct TCGCPUOps power10_tcg_ops; + /* * Generic callbacks: * do nothing but store/retrieve spr value @@ -8685,6 +8690,9 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; +#ifdef CONFIG_TCG + cc->tcg_ops =3D &power7_tcg_ops; +#endif /* CONFIG_TCG */ } =20 static void init_proc_POWER8(CPUPPCState *env) @@ -8863,6 +8871,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; +#ifdef CONFIG_TCG + cc->tcg_ops =3D &power8_tcg_ops; +#endif /* CONFIG_TCG */ } =20 #ifdef CONFIG_SOFTMMU @@ -9081,6 +9092,9 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; +#ifdef CONFIG_TCG + cc->tcg_ops =3D &power9_tcg_ops; +#endif /* CONFIG_TCG */ } =20 #ifdef CONFIG_SOFTMMU @@ -9292,6 +9306,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; +#ifdef CONFIG_TCG + cc->tcg_ops =3D &power10_tcg_ops; +#endif /* CONFIG_TCG */ } =20 #if !defined(CONFIG_USER_ONLY) @@ -10851,6 +10868,58 @@ static const struct TCGCPUOps ppc_tcg_ops =3D { .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .tlb_fill =3D ppc_cpu_tlb_fill, =20 +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D ppc_cpu_do_interrupt, + .cpu_exec_enter =3D ppc_cpu_exec_enter, + .cpu_exec_exit =3D ppc_cpu_exec_exit, + .do_unaligned_access =3D ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + +static const struct TCGCPUOps power7_tcg_ops =3D { + .initialize =3D ppc_translate_init, + .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, + .tlb_fill =3D ppc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D ppc_cpu_do_interrupt, + .cpu_exec_enter =3D ppc_cpu_exec_enter, + .cpu_exec_exit =3D ppc_cpu_exec_exit, + .do_unaligned_access =3D ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + +static const struct TCGCPUOps power8_tcg_ops =3D { + .initialize =3D ppc_translate_init, + .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, + .tlb_fill =3D ppc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D ppc_cpu_do_interrupt, + .cpu_exec_enter =3D ppc_cpu_exec_enter, + .cpu_exec_exit =3D ppc_cpu_exec_exit, + .do_unaligned_access =3D ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + +static const struct TCGCPUOps power9_tcg_ops =3D { + .initialize =3D ppc_translate_init, + .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, + .tlb_fill =3D ppc_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt =3D ppc_cpu_do_interrupt, + .cpu_exec_enter =3D ppc_cpu_exec_enter, + .cpu_exec_exit =3D ppc_cpu_exec_exit, + .do_unaligned_access =3D ppc_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + +static const struct TCGCPUOps power10_tcg_ops =3D { + .initialize =3D ppc_translate_init, + .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, + .tlb_fill =3D ppc_cpu_tlb_fill, + #ifndef CONFIG_USER_ONLY .do_interrupt =3D ppc_cpu_do_interrupt, .cpu_exec_enter =3D ppc_cpu_exec_enter, --=20 2.26.2 From nobody Fri May 17 11:58:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614896638; cv=none; d=zohomail.com; s=zohoarc; b=DEeeKC2s6vMjwmEV6KYicRyQTjULQZW54GTEZCzxQxcJo4xQ29aA2TYNipz6ylOLxuTcp3sOedPaYx1sNCeoiC8S5Ha/tZY45+2P0u74MnROxNndHDNmerP/pXgDImAHpuj4v8v7TvDp2kRPFmvy9AQWqMxjuzdP7ulnZzJqtQA= ARC-Message-Signature: i=1; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id j12sm1165596wrt.27.2021.03.04.14.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:23:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zTTkw6DpezJcV9ta0hw/wRNRNKjGMDk4hmoteXF2Vxs=; b=hvqFY9/8x2pQ3MdLFvz9iIu5R1VUd7sy7YKrg48MftwYJzQStGNpMagbf/ibcJtbsS XwMp3hHqRmtfVrMPBBQDd1vlpCwXpxjWamEvUSlS/G7NT4eCaEshL3K+OwE40c3588/m 50TiCJYqL7y8Ez0+9t43ZY3RJpwiVrGzZ7u94im5FDNBfSmpjkGTH5KiQuIF5Yc6Z2Bc WsUOkX/KedqBhzkGeO2/xO1TKURwjQ6X91NvLNkZ0/WhdN5Ws1MQ3DmWzQVdQE6HPb0x OdYsOgznLGyHSDXvKBheVqDG15OBVEpabtX2QNTIBCPgXltANzN1n/5VYgNPLFdlMPQr hZEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zTTkw6DpezJcV9ta0hw/wRNRNKjGMDk4hmoteXF2Vxs=; b=VsJaNT9ncPsvGpyxd231gAGJhGhKEkoiBZ9shUcXhhR0ps9CabWTVNAJoOgAgxak+1 LXpM7QXEdmSFKsMYdAUM5IW6ezGh6nqgE7ZoltjD5xIv5JRcJEudJM++vEeGQrYTgrvE yjZopBTABdvliHxR0dMXxBc8tpJQKVKa9YS+9TEINdCRT2CKS5aGaIGvWyLnsncEAumq qq5xncC6jPYIsh09/lBRUlTumrN0hqmfx80v+XXBJAjE9+5t/h4SrLltkNM0paRnbG5E DQ6IDmFKdvjw0GWBaNPdo+mA5VXbfx1vfMqS1dGD1z/xyHq1ZJgh+Rz89wSt/AD+6WEQ cGfg== X-Gm-Message-State: AOAM530+G0TI9VThObqKJiD+UCUrbn6Q/fw+byFb9j8PMq+vffHBwMrN tQMzMZYbZGM2abNSCHpe2DDK73VShU0= X-Google-Smtp-Source: ABdhPJx8klgY2qVo7VdLbu0491Gt8xseOQ7+EflJJtemygc1y7YGsLshyoZBnw2q0r4/3MVoDqd5BQ== X-Received: by 2002:a5d:400f:: with SMTP id n15mr5930136wrp.89.1614896636541; Thu, 04 Mar 2021 14:23:56 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , David Gibson , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Thomas Huth , Laurent Vivier , Cornelia Huck , Greg Kurz , Paolo Bonzini , qemu-arm@nongnu.org, Eduardo Habkost , Peter Maydell , Richard Henderson , qemu-riscv@nongnu.org, Claudio Fontana , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Marcel Apfelbaum Subject: [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h' Date: Thu, 4 Mar 2021 23:23:21 +0100 Message-Id: <20210304222323.1954755-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We can only check if a vCPU has work with TCG. Move the cpu_has_work() prototype to "sysemu/tcg.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- RFC: could another accelerator do that? can we rename this tcg_vcpu_has_work()? --- include/hw/core/cpu.h | 16 ---------------- include/sysemu/tcg.h | 11 +++++++++++ accel/tcg/cpu-exec.c | 7 +++++++ softmmu/cpus.c | 1 + 4 files changed, 19 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1376e496a3f..66109bcca35 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename); */ const char *parse_cpu_option(const char *cpu_option); =20 -/** - * cpu_has_work: - * @cpu: The vCPU to check. - * - * Checks whether the CPU has work to do. - * - * Returns: %true if the CPU has work, %false otherwise. - */ -static inline bool cpu_has_work(CPUState *cpu) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - g_assert(cc->has_work); - return cc->has_work(cpu); -} - /** * qemu_cpu_is_self: * @cpu: The vCPU to check against. diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index c16c13c3c69..3d46b0a7a93 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -10,6 +10,7 @@ =20 #ifndef CONFIG_TCG #define tcg_enabled() 0 +#define cpu_has_work(cpu) false #else =20 void tcg_exec_init(unsigned long tb_size, int splitwx); @@ -26,6 +27,16 @@ extern bool tcg_allowed; extern bool mttcg_enabled; #define qemu_tcg_mttcg_enabled() (mttcg_enabled) =20 +/** + * cpu_has_work: + * @cpu: The vCPU to check. + * + * Checks whether the CPU has work to do. + * + * Returns: %true if the CPU has work, %false otherwise. + */ +bool cpu_has_work(CPUState *cpu); + #endif /* CONFIG_TCG */ =20 #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 7e67ade35b9..b9ce36e59e2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu, return tb; } =20 +bool cpu_has_work(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + return cc->has_work(cpu); +} + static inline bool cpu_handle_halt(CPUState *cpu) { if (cpu->halted) { diff --git a/softmmu/cpus.c b/softmmu/cpus.c index a7ee431187a..548ab9236f1 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -42,6 +42,7 @@ #include "sysemu/runstate.h" #include "sysemu/cpu-timers.h" #include "sysemu/whpx.h" +#include "sysemu/tcg.h" #include "hw/boards.h" #include "hw/hw.h" =20 --=20 2.26.2 From nobody Fri May 17 11:58:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614896644; cv=none; d=zohomail.com; s=zohoarc; b=SUpSKas5OsJU3h7xfV1mMzt8NgcQaDkV5hsGZiikUga30OyA6q1ErSg833zdt9C+wdNwHrWbmE1tWQBErLbB9cGVuEhA+Z4gdk84kYpygdXpuByzY5YiDU5Tk3vX3hApg+wOpzWdPBeSeIX1qJUH0aX+TxC7ualu3aJ6ELaYxMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614896644; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nHP7+H+pUpBFPq7GhPyMRNWKOjnIMPvaEGxuyNvHJzs=; b=KDE6U5xsQAvSNCexPxsr3ycelsHd4K3JxrrlRa67q9yqwedgTdFymTwjQMmdSbH8BzE5jyikF+kex04VD+p3nHsqR0KRMfJhrFAeC/HZfJXM+lsFBfXkiOpLUtGatfoibGuO/4xjtDS6hfPMK0GE4jatcznjrN5cgG+hut4yJQk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1614896644929413.14537735934584; Thu, 4 Mar 2021 14:24:04 -0800 (PST) Received: by mail-wm1-f50.google.com with SMTP id l22so9390344wme.1 for ; Thu, 04 Mar 2021 14:24:04 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id m132sm1400938wmf.45.2021.03.04.14.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:24:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nHP7+H+pUpBFPq7GhPyMRNWKOjnIMPvaEGxuyNvHJzs=; b=I3dGCnIMFZALivYxWDyIIZvhm8Lr/tUBMUiRV+I2DYDZ+ri/NKGJesaPU4RimErCNZ bp7OB4m0wdRpmsWyaGzrcZBAczwWqP5jbtOYLAzvm/4yexC0ZKvC//m8hdOJr+kBSgGM 1FfSRwiKihAD7hk9GT50rvMAEh3+7qhyW7xiJ4cQpLFde4Ma7runXu0WIgeG7k+ndLTS 1dLkIySzW0pfquwAdwywSFQ+AcqY/HdNSqlXCPgotq+sEeBgeO0w+uzR56Glm7eMtqBy cTubW6Qa45wbPyPTU8JlpVVEMH7pk/mGmPjeW4keIKv+Z0szWlaYENOT/2wwicP8kV3N aFdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nHP7+H+pUpBFPq7GhPyMRNWKOjnIMPvaEGxuyNvHJzs=; b=auFKzi68AbeN76A5HTUkcESbH/eaDInUWTXnsuYmVXEfDtxKvIbrkEP96wKMRISI1U ab4HvOkzCir3OZPaq0OgwwhWSs+AhTUf4oQW7y60AIIYBCdxVBzrCEYwQ+IbnJpHoXAA ZJKOnqOknbszAQtSviMfa5Usd4A+I7MAC60Cl1gwXjP6gfOC6aMr9868zkVPzm/pp1zF unxQkZMIRBA361NLvdd3shamYzJzki9zJ8n19CR9Vd78F2uN0mgz99Zn02pmdPDtxZG1 TJyBYkHGqocyHcxum+bzMrAw7cdxlWKqQsVisWcTAXQTvhOeWGlowp6TSPbdy0FgCuSu T4dw== X-Gm-Message-State: AOAM531TarBQU7jhrC4h6md0ZZKoBCm/fPyAu22viieTAus3QUQmcTO0 rDif2PATNLocNQXWz4nGEBw= X-Google-Smtp-Source: ABdhPJxsxA17v1Gnk1btW5Iksqs5ErEa/VKmfoXpmRBTcwvAgs1B6TGV/Jbl7FGEmLku5rGipnyNTg== X-Received: by 2002:a1c:4b0a:: with SMTP id y10mr5736938wma.141.1614896642933; Thu, 04 Mar 2021 14:24:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , David Gibson , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Thomas Huth , Laurent Vivier , Cornelia Huck , Greg Kurz , Paolo Bonzini , qemu-arm@nongnu.org, Eduardo Habkost , Peter Maydell , Richard Henderson , qemu-riscv@nongnu.org, Claudio Fontana , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Taylor Simpson , Marcel Apfelbaum , Michael Rolnik , Sarah Harris , "Edgar E. Iglesias" , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov Subject: [RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps Date: Thu, 4 Mar 2021 23:23:22 +0100 Message-Id: <20210304222323.1954755-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We can only check if a vCPU has work with TCG. Restrict the has_work() handler to TCG by moving it to the TCGCPUOps structure, and adapt all the targets. cpu_common_has_work() is removed as being inlined in cpu_has_work(). Reviewed-by: Taylor Simpson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v2: - finished PPC - check cc->tcg_ops->has_work non-null (thuth) --- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 4 ++++ accel/tcg/cpu-exec.c | 6 +++++- hw/core/cpu.c | 6 ------ target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 3 ++- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 7 +------ target/i386/tcg/tcg-cpu.c | 6 ++++++ target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 10 +++++----- 29 files changed, 44 insertions(+), 42 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 66109bcca35..8efea289e7e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -86,7 +86,6 @@ struct AccelCPUClass; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @has_work: Callback for checking if there is work to do. * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. Non-configurab= le * CPUs can use the default implementation of this method. This method sho= uld @@ -149,7 +148,6 @@ struct CPUClass { void (*parse_features)(const char *typename, char *str, Error **errp); =20 int reset_dump_flags; - bool (*has_work)(CPUState *cpu); bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 72d791438c2..f5d44ba59f3 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -19,6 +19,10 @@ struct TCGCPUOps { * Called when the first CPU is realized. */ void (*initialize)(void); + /** + * @has_work: Callback for checking if there is work to do + */ + bool (*has_work)(CPUState *cpu); /** * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b9ce36e59e2..4e73550f981 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -451,7 +451,11 @@ bool cpu_has_work(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - return cc->has_work(cpu); + if (cc->tcg_ops->has_work) { + return cc->tcg_ops->has_work(cpu); + } + + return false; } =20 static inline bool cpu_handle_halt(CPUState *cpu) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..3110867c3a3 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -261,11 +261,6 @@ static void cpu_common_reset(DeviceState *dev) } } =20 -static bool cpu_common_has_work(CPUState *cs) -{ - return false; -} - ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) { CPUClass *cc =3D CPU_CLASS(object_class_by_name(typename)); @@ -397,7 +392,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) =20 k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; - k->has_work =3D cpu_common_has_work; k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->write_elf32_qemunote =3D cpu_common_write_elf32_qemunote; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index e50ae7bef06..57e88bbe7fd 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -210,6 +210,7 @@ static void alpha_cpu_initfn(Object *obj) =20 static const struct TCGCPUOps alpha_tcg_ops =3D { .initialize =3D alpha_translate_init, + .has_work =3D alpha_cpu_has_work, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .tlb_fill =3D alpha_cpu_tlb_fill, =20 @@ -230,7 +231,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) &acc->parent_realize); =20 cc->class_by_name =3D alpha_cpu_class_by_name; - cc->has_work =3D alpha_cpu_has_work; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6d2d9f2100f..7181deee84a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2263,6 +2263,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) #ifdef CONFIG_TCG static const struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, + .has_work =3D arm_cpu_has_work, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, @@ -2291,7 +2292,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); =20 cc->class_by_name =3D arm_cpu_class_by_name; - cc->has_work =3D arm_cpu_has_work; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; cc->gdb_read_register =3D arm_cpu_gdb_read_register; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 7d0ab606ae1..7416aa805d0 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -188,6 +188,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) =20 static const struct TCGCPUOps avr_tcg_ops =3D { .initialize =3D avr_cpu_tcg_init, + .has_work =3D avr_cpu_has_work, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, .tlb_fill =3D avr_cpu_tlb_fill, @@ -208,7 +209,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) =20 cc->class_by_name =3D avr_cpu_class_by_name; =20 - cc->has_work =3D avr_cpu_has_work; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 4586302ba39..eef76a211f1 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -197,6 +197,7 @@ static void cris_cpu_initfn(Object *obj) =20 static const struct TCGCPUOps crisv10_tcg_ops =3D { .initialize =3D cris_initialize_crisv10_tcg, + .has_work =3D cris_cpu_has_work, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .tlb_fill =3D cris_cpu_tlb_fill, =20 @@ -207,6 +208,7 @@ static const struct TCGCPUOps crisv10_tcg_ops =3D { =20 static const struct TCGCPUOps crisv32_tcg_ops =3D { .initialize =3D cris_initialize_tcg, + .has_work =3D cris_cpu_has_work, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .tlb_fill =3D cris_cpu_tlb_fill, =20 @@ -286,7 +288,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); =20 cc->class_by_name =3D cris_cpu_class_by_name; - cc->has_work =3D cris_cpu_has_work; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a13a941ed5b..cda63537d32 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -268,6 +268,7 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr addres= s, int size, =20 static const struct TCGCPUOps hexagon_tcg_ops =3D { .initialize =3D hexagon_translate_init, + .has_work =3D hexagon_cpu_has_work, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, .tlb_fill =3D hexagon_tlb_fill, }; @@ -284,7 +285,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void= *data) device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_rese= t); =20 cc->class_by_name =3D hexagon_cpu_class_by_name; - cc->has_work =3D hexagon_cpu_has_work; cc->dump_state =3D hexagon_dump_state; cc->set_pc =3D hexagon_cpu_set_pc; cc->gdb_read_register =3D hexagon_gdb_read_register; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5f1822b5fe6..b9437f4c534 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -135,6 +135,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 static const struct TCGCPUOps hppa_tcg_ops =3D { .initialize =3D hppa_translate_init, + .has_work =3D hppa_cpu_has_work, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .tlb_fill =3D hppa_cpu_tlb_fill, @@ -155,7 +156,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) &acc->parent_realize); =20 cc->class_by_name =3D hppa_cpu_class_by_name; - cc->has_work =3D hppa_cpu_has_work; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 50008431c35..464e136a072 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7171,6 +7171,7 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip =3D value; } =20 +/* FIXME TCG only? */ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -7213,11 +7214,6 @@ int x86_cpu_pending_interrupt(CPUState *cs, int inte= rrupt_request) return 0; } =20 -static bool x86_cpu_has_work(CPUState *cs) -{ - return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; -} - static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu =3D X86_CPU(cs); @@ -7404,7 +7400,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; - cc->has_work =3D x86_cpu_has_work; =20 #ifdef CONFIG_TCG tcg_cpu_common_class_init(cc); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6a35aa664dc..fee8487135d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -57,10 +57,16 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, cpu->env.eip =3D tb->pc - tb->cs_base; } =20 +static bool x86_cpu_has_work(CPUState *cs) +{ + return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; +} + #include "hw/core/tcg-cpu-ops.h" =20 static const struct TCGCPUOps x86_tcg_ops =3D { .initialize =3D tcg_x86_init, + .has_work =3D x86_cpu_has_work, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 4ad253a50ec..5d18255ac83 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -214,6 +214,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 static const struct TCGCPUOps lm32_tcg_ops =3D { .initialize =3D lm32_translate_init, + .has_work =3D lm32_cpu_has_work, .cpu_exec_interrupt =3D lm32_cpu_exec_interrupt, .tlb_fill =3D lm32_cpu_tlb_fill, .debug_excp_handler =3D lm32_debug_excp_handler, @@ -234,7 +235,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset); =20 cc->class_by_name =3D lm32_cpu_class_by_name; - cc->has_work =3D lm32_cpu_has_work; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; cc->gdb_read_register =3D lm32_cpu_gdb_read_register; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 9b2f651213b..9c38138215f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -506,6 +506,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 static const struct TCGCPUOps m68k_tcg_ops =3D { .initialize =3D m68k_tcg_init, + .has_work =3D m68k_cpu_has_work, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .tlb_fill =3D m68k_cpu_tlb_fill, =20 @@ -526,7 +527,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D m68k_cpu_class_by_name; - cc->has_work =3D m68k_cpu_has_work; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4e086ab5465..809f42b5e0d 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -356,6 +356,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 static const struct TCGCPUOps mb_tcg_ops =3D { .initialize =3D mb_tcg_init, + .has_work =3D mb_cpu_has_work, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .tlb_fill =3D mb_cpu_tlb_fill, @@ -378,7 +379,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D mb_cpu_class_by_name; - cc->has_work =3D mb_cpu_has_work; =20 cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 81030c5c407..a189710904a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -688,6 +688,7 @@ static Property mips_cpu_properties[] =3D { */ static const struct TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, + .has_work =3D mips_cpu_has_work, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .tlb_fill =3D mips_cpu_tlb_fill, @@ -713,7 +714,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) device_class_set_props(dc, mips_cpu_properties); =20 cc->class_by_name =3D mips_cpu_class_by_name; - cc->has_work =3D mips_cpu_has_work; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->gdb_read_register =3D mips_cpu_gdb_read_register; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index c3de71b82fe..942804de21b 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -98,6 +98,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) =20 static const struct TCGCPUOps moxie_tcg_ops =3D { .initialize =3D moxie_translate_init, + .has_work =3D moxie_cpu_has_work, .tlb_fill =3D moxie_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY @@ -117,7 +118,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D moxie_cpu_class_by_name; =20 - cc->has_work =3D moxie_cpu_has_work; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 0de93cdd98f..cfd9f002436 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -211,6 +211,7 @@ static Property nios2_properties[] =3D { =20 static const struct TCGCPUOps nios2_tcg_ops =3D { .initialize =3D nios2_tcg_init, + .has_work =3D nios2_cpu_has_work, .cpu_exec_interrupt =3D nios2_cpu_exec_interrupt, .tlb_fill =3D nios2_cpu_tlb_fill, =20 @@ -232,7 +233,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); =20 cc->class_by_name =3D nios2_cpu_class_by_name; - cc->has_work =3D nios2_cpu_has_work; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 52aef277232..674e1ac0d23 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -178,6 +178,7 @@ static void openrisc_any_initfn(Object *obj) =20 static const struct TCGCPUOps openrisc_tcg_ops =3D { .initialize =3D openrisc_translate_init, + .has_work =3D openrisc_cpu_has_work, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .tlb_fill =3D openrisc_cpu_tlb_fill, =20 @@ -197,7 +198,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_res= et); =20 cc->class_by_name =3D openrisc_cpu_class_by_name; - cc->has_work =3D openrisc_cpu_has_work; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6f9822bc0a1..a5de166bb3f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -584,6 +584,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 static const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, + .has_work =3D riscv_cpu_has_work, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .tlb_fill =3D riscv_cpu_tlb_fill, @@ -607,7 +608,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D riscv_cpu_class_by_name; - cc->has_work =3D riscv_cpu_has_work; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 28d2becc32c..f5f967ff509 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -177,6 +177,7 @@ static void rx_cpu_init(Object *obj) =20 static const struct TCGCPUOps rx_tcg_ops =3D { .initialize =3D rx_translate_init, + .has_work =3D rx_cpu_has_work, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, .tlb_fill =3D rx_cpu_tlb_fill, @@ -198,7 +199,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) &rcc->parent_reset); =20 cc->class_by_name =3D rx_cpu_class_by_name; - cc->has_work =3D rx_cpu_has_work; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d57f69e7f7d..d2f897bf41a 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -465,6 +465,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 static const struct TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, + .has_work =3D s390_cpu_has_work, .tlb_fill =3D s390_cpu_tlb_fill, =20 #if !defined(CONFIG_USER_ONLY) @@ -493,7 +494,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) #endif scc->reset =3D s390_cpu_reset; cc->class_by_name =3D s390_cpu_class_by_name, - cc->has_work =3D s390_cpu_has_work; cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; cc->gdb_read_register =3D s390_cpu_gdb_read_register; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 9d77f9cfdae..8bac001bfa4 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -227,6 +227,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { =20 static const struct TCGCPUOps superh_tcg_ops =3D { .initialize =3D sh4_translate_init, + .has_work =3D superh_cpu_has_work, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .tlb_fill =3D superh_cpu_tlb_fill, @@ -250,7 +251,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset= ); =20 cc->class_by_name =3D superh_cpu_class_by_name; - cc->has_work =3D superh_cpu_has_work; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; cc->gdb_read_register =3D superh_cpu_gdb_read_register; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ccabe189c4a..761813ce96b 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -853,6 +853,7 @@ static Property sparc_cpu_properties[] =3D { =20 static const struct TCGCPUOps sparc_tcg_ops =3D { .initialize =3D sparc_tcg_init, + .has_work =3D sparc_cpu_has_work, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .tlb_fill =3D sparc_cpu_tlb_fill, @@ -879,7 +880,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; - cc->has_work =3D sparc_cpu_has_work; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index c7f8a898caf..3bc89e736b3 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -138,6 +138,7 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int= interrupt_request) =20 static const struct TCGCPUOps tilegx_tcg_ops =3D { .initialize =3D tilegx_tcg_init, + .has_work =3D tilegx_cpu_has_work, .cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt, .tlb_fill =3D tilegx_cpu_tlb_fill, =20 @@ -158,7 +159,6 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset= ); =20 cc->class_by_name =3D tilegx_cpu_class_by_name; - cc->has_work =3D tilegx_cpu_has_work; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; cc->gdb_num_core_regs =3D 0; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 5b500b575bd..b493e3ede85 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -146,6 +146,7 @@ static void tc27x_initfn(Object *obj) =20 static const struct TCGCPUOps tricore_tcg_ops =3D { .initialize =3D tricore_tcg_init, + .has_work =3D tricore_cpu_has_work, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .tlb_fill =3D tricore_cpu_tlb_fill, }; @@ -161,7 +162,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_rese= t); cc->class_by_name =3D tricore_cpu_class_by_name; - cc->has_work =3D tricore_cpu_has_work; =20 cc->gdb_read_register =3D tricore_cpu_gdb_read_register; cc->gdb_write_register =3D tricore_cpu_gdb_write_register; diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index a732b08748d..55569018296 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -124,6 +124,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { =20 static const struct TCGCPUOps uc32_tcg_ops =3D { .initialize =3D uc32_translate_init, + .has_work =3D uc32_cpu_has_work, .cpu_exec_interrupt =3D uc32_cpu_exec_interrupt, .tlb_fill =3D uc32_cpu_tlb_fill, =20 @@ -142,7 +143,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) &ucc->parent_realize); =20 cc->class_by_name =3D uc32_cpu_class_by_name; - cc->has_work =3D uc32_cpu_has_work; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index badc3a26aa2..849a664a679 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -185,6 +185,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { =20 static const struct TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, + .has_work =3D xtensa_cpu_has_work, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .tlb_fill =3D xtensa_cpu_tlb_fill, .debug_excp_handler =3D xtensa_breakpoint_handler, @@ -208,7 +209,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset= ); =20 cc->class_by_name =3D xtensa_cpu_class_by_name; - cc->has_work =3D xtensa_cpu_has_work; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index fe76d0b3773..1558de804c9 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -8633,7 +8633,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER7; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER7; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -8806,7 +8805,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->pcr_supported =3D PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_= 2_05; pcc->init_proc =3D init_proc_POWER8; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER8; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -9026,7 +9024,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER9; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER9; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -9241,7 +9238,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->init_proc =3D init_proc_POWER10; pcc->check_pow =3D check_pow_nocheck; - cc->has_work =3D cpu_has_work_POWER10; pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB= | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | @@ -10865,6 +10861,7 @@ static Property ppc_cpu_properties[] =3D { =20 static const struct TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, + .has_work =3D ppc_cpu_has_work, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .tlb_fill =3D ppc_cpu_tlb_fill, =20 @@ -10878,6 +10875,7 @@ static const struct TCGCPUOps ppc_tcg_ops =3D { =20 static const struct TCGCPUOps power7_tcg_ops =3D { .initialize =3D ppc_translate_init, + .has_work =3D cpu_has_work_POWER7, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .tlb_fill =3D ppc_cpu_tlb_fill, =20 @@ -10891,6 +10889,7 @@ static const struct TCGCPUOps power7_tcg_ops =3D { =20 static const struct TCGCPUOps power8_tcg_ops =3D { .initialize =3D ppc_translate_init, + .has_work =3D cpu_has_work_POWER8, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .tlb_fill =3D ppc_cpu_tlb_fill, =20 @@ -10904,6 +10903,7 @@ static const struct TCGCPUOps power8_tcg_ops =3D { =20 static const struct TCGCPUOps power9_tcg_ops =3D { .initialize =3D ppc_translate_init, + .has_work =3D cpu_has_work_POWER9, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .tlb_fill =3D ppc_cpu_tlb_fill, =20 @@ -10917,6 +10917,7 @@ static const struct TCGCPUOps power9_tcg_ops =3D { =20 static const struct TCGCPUOps power10_tcg_ops =3D { .initialize =3D ppc_translate_init, + .has_work =3D cpu_has_work_POWER10, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .tlb_fill =3D ppc_cpu_tlb_fill, =20 @@ -10946,7 +10947,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); =20 cc->class_by_name =3D ppc_cpu_class_by_name; - cc->has_work =3D ppc_cpu_has_work; cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; cc->set_pc =3D ppc_cpu_set_pc; --=20 2.26.2 From nobody Fri May 17 11:58:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) client-ip=209.85.128.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614896649; cv=none; d=zohomail.com; s=zohoarc; b=TdJKmwf70Rz+O+qE6eUfjEskZkFhYjvRiUfxt7DJ3NMC6ZjKPAp/XaGtmMCR6kcn/EeSQFv2AK0UNpS2ziGPLNEQO+bmp01Ck2UTU6vOADrxCpI3CSVsWY0U7t7//2LCg61GWqV0HI2L7bM5ywjT+hwY60ihNSKNutUdtNoE9r4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id n66sm1250102wmn.25.2021.03.04.14.24.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Mar 2021 14:24:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fX6hEXkHOn0EDIH5ppgTAZxEG1tZNK4v7KhIUlmGx5M=; b=NmsARctxdUkxORvwpGrzrQBVLeNzc5ZUXeZNDaRJMDGsGYiiepheAAeenQx8XJkWG0 V6DQv6qOlw9kCHbaM40nZ95uRgDrFEM74p3NtTXaUFxeYzPtYEY+/8buH8VD1g6Z64z9 Y1/j5YnIRV8TWYzbnM/G+CHCU0nnPlfO6OYaqxsPrCdpPwwHEJOD8EWrxWcxdemXwK9D JnXOiRmTvl6H4cteMVFBQ3+TLc0ueTbXcQSZKsK/wQALoWndsvwOe4023JDnq+Lioxxk W94rxO+oT/+zmHb+qDgrOD8V6m0EzWs6IeHb8lETIoqONVLMTDwHxelhMvZjiMlKN24u XLlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fX6hEXkHOn0EDIH5ppgTAZxEG1tZNK4v7KhIUlmGx5M=; b=aAhs7mUcVebnWi/EkTnUXGzgPTPLwQHwrby7PS+0gkETTJkDm6GPaHhKBWy+TZqYYA nCbHSWeWZPWcEsjyXSqrDbkkE2YEpUc9FV45QFBhk66VoZz3cBsZMy/PMQodlz6ArhlY p8nAHRc5Zalaqjrh05qHcPiIMTjPhvrHdnWaJVdbdy5dNfVfN+aj7LueGEjQqPKBBcPh OE3T584FFOfz1LqJ2OavCNEFOQ1rDISniqZmQAs5cJC2N4eLqgvu/RllvcLJELKIHRW2 BFXZehr56yZ/WuindC+O0aajgxP5Ls1q9z0QLG2kN8b6Qh+cirgZb94ueTUNwIDUB1u9 VsiA== X-Gm-Message-State: AOAM531adLBQvNkB2njwTBDfG7R2u9Y7BpitfT/QJrdE8ZlyKhcwZqg4 +tW3sKeZwcU1u8qGxcVFtXY= X-Google-Smtp-Source: ABdhPJzosXqnrg30Glb/e8pVNWp2DurBv7xYuCw8ER1o1ANc+KLu/D+uVw2qnceBEynPCG5A6WFV0A== X-Received: by 2002:a7b:c5cc:: with SMTP id n12mr5768799wmk.123.1614896647799; Thu, 04 Mar 2021 14:24:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , David Gibson , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, Thomas Huth , Laurent Vivier , Cornelia Huck , Greg Kurz , Paolo Bonzini , qemu-arm@nongnu.org, Eduardo Habkost , Peter Maydell , Richard Henderson , qemu-riscv@nongnu.org, Claudio Fontana , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 8/8] target/arm: Restrict arm_cpu_has_work() to TCG Date: Thu, 4 Mar 2021 23:23:23 +0100 Message-Id: <20210304222323.1954755-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org> References: <20210304222323.1954755-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) arm_cpu_has_work() is only used from TCG. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 2 +- target/arm/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1930be08828..db81db9bf57 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -172,8 +172,8 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); =20 -bool arm_cpu_has_work(CPUState *cs); #ifdef CONFIG_TCG +bool arm_cpu_has_work(CPUState *cs); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7181deee84a..02db969c00f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -74,7 +74,6 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, env->regs[15] =3D tb->pc; } } -#endif /* CONFIG_TCG */ =20 bool arm_cpu_has_work(CPUState *cs) { @@ -86,6 +85,7 @@ bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_EXITTB); } +#endif /* CONFIG_TCG */ =20 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) --=20 2.26.2