From nobody Fri Oct 25 19:22:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1614896206; cv=none; d=zohomail.com; s=zohoarc; b=JZhuQF7LCxkLH5eS4YmEefyirKyjSgZ3ngbHsq5ej+ip9Z3apUboyMZVFv0D2U59CzWaVPla75JYtHVwR2ouOUs7zxb6XWm21IUlZ/rmz7rdFGVzyA0t8RwpcfzN8cuvgH9a2kdTVoh1a3qCS7McW2fzo3r8hdrpWSSjyLNi2V0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614896206; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=neCwaY0J6x1vFz3OKNZ7RlpIDmg6UrQxZHb6hU1rf/Y=; b=BLyio1F3y+bICVwISx1kTC1/ABA+/rFpFvnljiwyORG7LNyw2RyavcA03ECbuQP+8iBWqAFiqaDq6dtkHcTVKayBX8YaENVPqo0QpSuhfzr5FF8HK0HI46gwBn3YHgCLOf6ab1y2a637S2OITI2KRFGYbbe8RrywOoYzYj1J1Lg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614896206004786.3887300328826; Thu, 4 Mar 2021 14:16:46 -0800 (PST) Received: from localhost ([::1]:41924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwGy-0003S8-IK for importer@patchew.org; Thu, 04 Mar 2021 17:16:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwBw-0004j0-O5 for qemu-devel@nongnu.org; Thu, 04 Mar 2021 17:11:32 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:39922 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwBu-0005Yx-GJ for qemu-devel@nongnu.org; Thu, 04 Mar 2021 17:11:32 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lHwBn-0008MJ-Sy; Thu, 04 Mar 2021 22:11:28 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, pbonzini@redhat.com, fam@euphon.net, laurent@vivier.eu Date: Thu, 4 Mar 2021 22:10:24 +0000 Message-Id: <20210304221103.6369-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210304221103.6369-1-mark.cave-ayland@ilande.co.uk> References: <20210304221103.6369-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 03/42] esp: QOMify the internal ESP device state X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Make this new QOM device state a child device of both the sysbus-esp and es= p-pci implementations. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Laurent Vivier --- hw/scsi/esp-pci.c | 50 ++++++++++++++++++++++++++++++++----------- hw/scsi/esp.c | 47 ++++++++++++++++++++++++++++++++++------ include/hw/scsi/esp.h | 5 +++++ 3 files changed, 82 insertions(+), 20 deletions(-) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 4d7c2cab56..27a0d36e0b 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -79,8 +79,10 @@ struct PCIESPState { =20 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) { + ESPState *s =3D ESP(&pci->esp); + trace_esp_pci_dma_idle(val); - esp_dma_enable(&pci->esp, 0, 0); + esp_dma_enable(s, 0, 0); } =20 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) @@ -91,14 +93,18 @@ static void esp_pci_handle_blast(PCIESPState *pci, uint= 32_t val) =20 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val) { + ESPState *s =3D ESP(&pci->esp); + trace_esp_pci_dma_abort(val); - if (pci->esp.current_req) { - scsi_req_cancel(pci->esp.current_req); + if (s->current_req) { + scsi_req_cancel(s->current_req); } } =20 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val) { + ESPState *s =3D ESP(&pci->esp); + trace_esp_pci_dma_start(val); =20 pci->dma_regs[DMA_WBC] =3D pci->dma_regs[DMA_STC]; @@ -109,7 +115,7 @@ static void esp_pci_handle_start(PCIESPState *pci, uint= 32_t val) | DMA_STAT_DONE | DMA_STAT_ABORT | DMA_STAT_ERROR | DMA_STAT_PWDN); =20 - esp_dma_enable(&pci->esp, 0, 1); + esp_dma_enable(s, 0, 1); } =20 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t v= al) @@ -155,11 +161,12 @@ static void esp_pci_dma_write(PCIESPState *pci, uint3= 2_t saddr, uint32_t val) =20 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) { + ESPState *s =3D ESP(&pci->esp); uint32_t val; =20 val =3D pci->dma_regs[saddr]; if (saddr =3D=3D DMA_STAT) { - if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) { + if (s->rregs[ESP_RSTAT] & STAT_INT) { val |=3D DMA_STAT_SCSIINT; } if (!(pci->sbac & SBAC_STATUS)) { @@ -176,6 +183,7 @@ static void esp_pci_io_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { PCIESPState *pci =3D opaque; + ESPState *s =3D ESP(&pci->esp); =20 if (size < 4 || addr & 3) { /* need to upgrade request: we only support 4-bytes accesses */ @@ -183,7 +191,7 @@ static void esp_pci_io_write(void *opaque, hwaddr addr, int shift; =20 if (addr < 0x40) { - current =3D pci->esp.wregs[addr >> 2]; + current =3D s->wregs[addr >> 2]; } else if (addr < 0x60) { current =3D pci->dma_regs[(addr - 0x40) >> 2]; } else if (addr < 0x74) { @@ -203,7 +211,7 @@ static void esp_pci_io_write(void *opaque, hwaddr addr, =20 if (addr < 0x40) { /* SCSI core reg */ - esp_reg_write(&pci->esp, addr >> 2, val); + esp_reg_write(s, addr >> 2, val); } else if (addr < 0x60) { /* PCI DMA CCB */ esp_pci_dma_write(pci, (addr - 0x40) >> 2, val); @@ -220,11 +228,12 @@ static uint64_t esp_pci_io_read(void *opaque, hwaddr = addr, unsigned int size) { PCIESPState *pci =3D opaque; + ESPState *s =3D ESP(&pci->esp); uint32_t ret; =20 if (addr < 0x40) { /* SCSI core reg */ - ret =3D esp_reg_read(&pci->esp, addr >> 2); + ret =3D esp_reg_read(s, addr >> 2); } else if (addr < 0x60) { /* PCI DMA CCB */ ret =3D esp_pci_dma_read(pci, (addr - 0x40) >> 2); @@ -306,7 +315,9 @@ static const MemoryRegionOps esp_pci_io_ops =3D { static void esp_pci_hard_reset(DeviceState *dev) { PCIESPState *pci =3D PCI_ESP(dev); - esp_hard_reset(&pci->esp); + ESPState *s =3D ESP(&pci->esp); + + esp_hard_reset(s); pci->dma_regs[DMA_CMD] &=3D ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_I= NTE_P | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK); pci->dma_regs[DMA_WBC] &=3D ~0xffff; @@ -353,9 +364,13 @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error= **errp) { PCIESPState *pci =3D PCI_ESP(dev); DeviceState *d =3D DEVICE(dev); - ESPState *s =3D &pci->esp; + ESPState *s =3D ESP(&pci->esp); uint8_t *pci_conf; =20 + if (!qdev_realize(DEVICE(s), NULL, errp)) { + return; + } + pci_conf =3D dev->config; =20 /* Interrupt pin A */ @@ -374,11 +389,19 @@ static void esp_pci_scsi_realize(PCIDevice *dev, Erro= r **errp) scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL); } =20 -static void esp_pci_scsi_uninit(PCIDevice *d) +static void esp_pci_scsi_exit(PCIDevice *d) { PCIESPState *pci =3D PCI_ESP(d); + ESPState *s =3D ESP(&pci->esp); + + qemu_free_irq(s->irq); +} + +static void esp_pci_init(Object *obj) +{ + PCIESPState *pci =3D PCI_ESP(obj); =20 - qemu_free_irq(pci->esp.irq); + object_initialize_child(obj, "esp", &pci->esp, TYPE_ESP); } =20 static void esp_pci_class_init(ObjectClass *klass, void *data) @@ -387,7 +410,7 @@ static void esp_pci_class_init(ObjectClass *klass, void= *data) PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->realize =3D esp_pci_scsi_realize; - k->exit =3D esp_pci_scsi_uninit; + k->exit =3D esp_pci_scsi_exit; k->vendor_id =3D PCI_VENDOR_ID_AMD; k->device_id =3D PCI_DEVICE_ID_AMD_SCSI; k->revision =3D 0x10; @@ -401,6 +424,7 @@ static void esp_pci_class_init(ObjectClass *klass, void= *data) static const TypeInfo esp_pci_info =3D { .name =3D TYPE_AM53C974_DEVICE, .parent =3D TYPE_PCI_DEVICE, + .instance_init =3D esp_pci_init, .instance_size =3D sizeof(PCIESPState), .class_init =3D esp_pci_class_init, .interfaces =3D (InterfaceInfo[]) { diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 93312a68d9..6f8a1d1224 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -827,20 +827,22 @@ static void sysbus_esp_mem_write(void *opaque, hwaddr= addr, uint64_t val, unsigned int size) { SysBusESPState *sysbus =3D opaque; + ESPState *s =3D ESP(&sysbus->esp); uint32_t saddr; =20 saddr =3D addr >> sysbus->it_shift; - esp_reg_write(&sysbus->esp, saddr, val); + esp_reg_write(s, saddr, val); } =20 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, unsigned int size) { SysBusESPState *sysbus =3D opaque; + ESPState *s =3D ESP(&sysbus->esp); uint32_t saddr; =20 saddr =3D addr >> sysbus->it_shift; - return esp_reg_read(&sysbus->esp, saddr); + return esp_reg_read(s, saddr); } =20 static const MemoryRegionOps sysbus_esp_mem_ops =3D { @@ -854,7 +856,7 @@ static void sysbus_esp_pdma_write(void *opaque, hwaddr = addr, uint64_t val, unsigned int size) { SysBusESPState *sysbus =3D opaque; - ESPState *s =3D &sysbus->esp; + ESPState *s =3D ESP(&sysbus->esp); uint32_t dmalen; uint8_t *buf =3D get_pdma_buf(s); =20 @@ -891,7 +893,7 @@ static uint64_t sysbus_esp_pdma_read(void *opaque, hwad= dr addr, unsigned int size) { SysBusESPState *sysbus =3D opaque; - ESPState *s =3D &sysbus->esp; + ESPState *s =3D ESP(&sysbus->esp); uint8_t *buf =3D get_pdma_buf(s); uint64_t val =3D 0; =20 @@ -939,7 +941,7 @@ static const struct SCSIBusInfo esp_scsi_info =3D { static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) { SysBusESPState *sysbus =3D SYSBUS_ESP(opaque); - ESPState *s =3D &sysbus->esp; + ESPState *s =3D ESP(&sysbus->esp); =20 switch (irq) { case 0: @@ -955,7 +957,11 @@ static void sysbus_esp_realize(DeviceState *dev, Error= **errp) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); SysBusESPState *sysbus =3D SYSBUS_ESP(dev); - ESPState *s =3D &sysbus->esp; + ESPState *s =3D ESP(&sysbus->esp); + + if (!qdev_realize(DEVICE(s), NULL, errp)) { + return; + } =20 sysbus_init_irq(sbd, &s->irq); sysbus_init_irq(sbd, &s->irq_data); @@ -977,7 +983,16 @@ static void sysbus_esp_realize(DeviceState *dev, Error= **errp) static void sysbus_esp_hard_reset(DeviceState *dev) { SysBusESPState *sysbus =3D SYSBUS_ESP(dev); - esp_hard_reset(&sysbus->esp); + ESPState *s =3D ESP(&sysbus->esp); + + esp_hard_reset(s); +} + +static void sysbus_esp_init(Object *obj) +{ + SysBusESPState *sysbus =3D SYSBUS_ESP(obj); + + object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); } =20 static const VMStateDescription vmstate_sysbus_esp_scsi =3D { @@ -1003,13 +1018,31 @@ static void sysbus_esp_class_init(ObjectClass *klas= s, void *data) static const TypeInfo sysbus_esp_info =3D { .name =3D TYPE_SYSBUS_ESP, .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_init =3D sysbus_esp_init, .instance_size =3D sizeof(SysBusESPState), .class_init =3D sysbus_esp_class_init, }; =20 +static void esp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + /* internal device for sysbusesp/pciespscsi, not user-creatable */ + dc->user_creatable =3D false; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); +} + +static const TypeInfo esp_info =3D { + .name =3D TYPE_ESP, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(ESPState), + .class_init =3D esp_class_init, +}; + static void esp_register_types(void) { type_register_static(&sysbus_esp_info); + type_register_static(&esp_info); } =20 type_init(esp_register_types) diff --git a/include/hw/scsi/esp.h b/include/hw/scsi/esp.h index 8a0740e953..af23f813cb 100644 --- a/include/hw/scsi/esp.h +++ b/include/hw/scsi/esp.h @@ -22,7 +22,12 @@ enum pdma_origin_id { ASYNC, }; =20 +#define TYPE_ESP "esp" +OBJECT_DECLARE_SIMPLE_TYPE(ESPState, ESP) + struct ESPState { + DeviceState parent_obj; + uint8_t rregs[ESP_REGS]; uint8_t wregs[ESP_REGS]; qemu_irq irq; --=20 2.20.1