From nobody Fri Oct 25 19:37:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1614897183; cv=none; d=zohomail.com; s=zohoarc; b=Esfe6V2dwC3H3JT+7jzsTjXEewjpX/LLDUt0RiSvwxiL2v9y7XG/Sw5CQsdOoxy6YLxHc9Gtx0dbyoZOyEwkt4YBdgfd4XLwRZNGvJmbZ52k5drVLRpiudzIWTc21RFcSSJCst2eS0kHF2oRygvaTBvbf1q1Ulm+USXkHu09f0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614897183; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jh5BssQZ6DP5lUiy8OCfwK/hdzneapXxW/IYZWA31l4=; b=SuKMsm+47lSw2HCx5HwDSdsqN6n7gT748ZQkPVDYHIwM4e7P2kPohBO6E4Jnq8q5BUZcwG1/mj9cGkuHsez8vjuC/8ERIRWuTuoE86sO0aqy7R9XieKu1BUgNMVwhzrr7NDgQkJp4n6kyGspbKQLOLNcbPk24eYWMUjVQQdE7KU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614897183148400.4707316701558; Thu, 4 Mar 2021 14:33:03 -0800 (PST) Received: from localhost ([::1]:41212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHwWk-0002Ha-1M for importer@patchew.org; Thu, 04 Mar 2021 17:33:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53942) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwEb-00013I-4x for qemu-devel@nongnu.org; Thu, 04 Mar 2021 17:14:17 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:40218 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHwEZ-0006bN-7B for qemu-devel@nongnu.org; Thu, 04 Mar 2021 17:14:16 -0500 Received: from host86-148-34-47.range86-148.btcentralplus.com ([86.148.34.47] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lHwEL-0008MJ-GI; Thu, 04 Mar 2021 22:14:03 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, pbonzini@redhat.com, fam@euphon.net, laurent@vivier.eu Date: Thu, 4 Mar 2021 22:10:53 +0000 Message-Id: <20210304221103.6369-33-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210304221103.6369-1-mark.cave-ayland@ilande.co.uk> References: <20210304221103.6369-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.148.34.47 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 32/42] esp: latch individual bits in ESP_RINTR register X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.uk0.bigv.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Currently the ESP_RINTR register is set to a specific value as required wit= hin the ESP state machine. In order to implement the upcoming deferred interrupt functionality it is necessary to set individual bits within ESP_RINTR so th= at a deferred interrupt will not overwrite the value of any other interrupt bi= ts. This also requires fixing up a few locations where the ESP_RINTR and ESP_RS= EQ registers are set/reset unexpectedly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier --- hw/scsi/esp.c | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 6aae6f91c2..54d008c609 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -178,7 +178,7 @@ static int esp_select(ESPState *s) if (!s->current_dev) { /* No such drive */ s->rregs[ESP_RSTAT] =3D 0; - s->rregs[ESP_RINTR] =3D INTR_DC; + s->rregs[ESP_RINTR] |=3D INTR_DC; s->rregs[ESP_RSEQ] =3D SEQ_0; esp_raise_irq(s); return -1; @@ -245,7 +245,7 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uin= t8_t busid) } scsi_req_continue(s->current_req); } - s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RINTR] |=3D INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] =3D SEQ_CD; esp_raise_irq(s); esp_lower_drq(s); @@ -326,7 +326,7 @@ static void satn_stop_pdma_cb(ESPState *s) trace_esp_handle_satn_stop(s->cmdlen); s->do_cmd =3D 1; s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_CD; - s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RINTR] |=3D INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] =3D SEQ_CD; esp_raise_irq(s); } @@ -346,8 +346,8 @@ static void handle_satn_stop(ESPState *s) trace_esp_handle_satn_stop(s->cmdlen); s->cmdlen =3D cmdlen; s->do_cmd =3D 1; - s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_CD; - s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RSTAT] =3D STAT_CD; + s->rregs[ESP_RINTR] |=3D INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] =3D SEQ_CD; esp_raise_irq(s); } else if (cmdlen =3D=3D 0) { @@ -362,7 +362,7 @@ static void handle_satn_stop(ESPState *s) static void write_response_pdma_cb(ESPState *s) { s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; - s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RINTR] |=3D INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] =3D SEQ_CD; esp_raise_irq(s); } @@ -376,7 +376,7 @@ static void write_response(ESPState *s) if (s->dma_memory_write) { s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); s->rregs[ESP_RSTAT] =3D STAT_TC | STAT_ST; - s->rregs[ESP_RINTR] =3D INTR_BS | INTR_FC; + s->rregs[ESP_RINTR] |=3D INTR_BS | INTR_FC; s->rregs[ESP_RSEQ] =3D SEQ_CD; } else { s->pdma_cb =3D write_response_pdma_cb; @@ -395,7 +395,7 @@ static void write_response(ESPState *s) static void esp_dma_done(ESPState *s) { s->rregs[ESP_RSTAT] |=3D STAT_TC; - s->rregs[ESP_RINTR] =3D INTR_BS; + s->rregs[ESP_RINTR] |=3D INTR_BS; s->rregs[ESP_RSEQ] =3D 0; s->rregs[ESP_RFLAGS] =3D 0; esp_set_tc(s, 0); @@ -700,7 +700,7 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr) val =3D s->rregs[ESP_RINTR]; s->rregs[ESP_RINTR] =3D 0; s->rregs[ESP_RSTAT] &=3D ~STAT_TC; - s->rregs[ESP_RSEQ] =3D SEQ_CD; + s->rregs[ESP_RSEQ] =3D SEQ_0; esp_lower_irq(s); if (s->deferred_complete) { esp_report_command_complete(s, s->deferred_status); @@ -771,9 +771,6 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_= t val) /*s->ti_size =3D 0;*/ s->ti_wptr =3D 0; s->ti_rptr =3D 0; - s->rregs[ESP_RINTR] =3D INTR_FC; - s->rregs[ESP_RSEQ] =3D 0; - s->rregs[ESP_RFLAGS] =3D 0; break; case CMD_RESET: trace_esp_mem_writeb_cmd_reset(val); @@ -781,8 +778,8 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_= t val) break; case CMD_BUSRESET: trace_esp_mem_writeb_cmd_bus_reset(val); - s->rregs[ESP_RINTR] =3D INTR_RST; if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { + s->rregs[ESP_RINTR] |=3D INTR_RST; esp_raise_irq(s); } break; @@ -793,12 +790,12 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint6= 4_t val) case CMD_ICCS: trace_esp_mem_writeb_cmd_iccs(val); write_response(s); - s->rregs[ESP_RINTR] =3D INTR_FC; + s->rregs[ESP_RINTR] |=3D INTR_FC; s->rregs[ESP_RSTAT] |=3D STAT_MI; break; case CMD_MSGACC: trace_esp_mem_writeb_cmd_msgacc(val); - s->rregs[ESP_RINTR] =3D INTR_DC; + s->rregs[ESP_RINTR] |=3D INTR_DC; s->rregs[ESP_RSEQ] =3D 0; s->rregs[ESP_RFLAGS] =3D 0; esp_raise_irq(s); @@ -806,7 +803,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_= t val) case CMD_PAD: trace_esp_mem_writeb_cmd_pad(val); s->rregs[ESP_RSTAT] =3D STAT_TC; - s->rregs[ESP_RINTR] =3D INTR_FC; + s->rregs[ESP_RINTR] |=3D INTR_FC; s->rregs[ESP_RSEQ] =3D 0; break; case CMD_SATN: --=20 2.20.1