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Iglesias" , Stafford Horne , Yoshinori Sato , Guan Xuetao , Max Filippov Subject: [PATCH v4 01/28] target: Set CPUClass::vmsd instead of DeviceClass::vmsd Date: Wed, 3 Mar 2021 22:46:41 +0100 Message-Id: <20210303214708.1727801-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The cpu model is the single device available in user-mode. Since we want to restrict some fields to user-mode emulation, we prefer to set the vmsd field of CPUClass, rather than the DeviceClass one. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/alpha/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27192b62e22..faabffe0796 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -237,7 +237,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_alpha_cpu; + cc->vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed983380fca..29a865b75d2 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -293,7 +293,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_cris_cpu; + cc->vmsd =3D &vmstate_cris_cpu; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d8fad52d1fe..4f142de6e45 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -162,7 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_hppa_cpu; + cc->vmsd =3D &vmstate_hppa_cpu; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 37d2ed9dc79..c98fb1e33be 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -533,7 +533,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_m68k_cpu; + cc->vmsd =3D &vmstate_m68k_cpu; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 433ba202037..335dfdc734e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -387,7 +387,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; - dc->vmsd =3D &vmstate_mb_cpu; + cc->vmsd =3D &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46b..79d246d1930 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -204,7 +204,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_openrisc_cpu; + cc->vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ac65c88f1f8..bd44de53729 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,7 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->gdb_num_core_regs =3D 59; =20 - dc->vmsd =3D &vmstate_sh_cpu; + cc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 0258884f845..12894ffac6a 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -146,7 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_uc32_cpu; + cc->vmsd =3D &vmstate_uc32_cpu; cc->tcg_ops =3D &uc32_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e2b2c7a71c1..6bedd5b97b8 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -218,7 +218,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - dc->vmsd =3D &vmstate_xtensa_cpu; + cc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614808042; cv=none; d=zohomail.com; s=zohoarc; b=ShZef3NCUNV9hf2O83W6hmY+hITHWrPf6gDhFiH8+1DgrFo+DeaytSeigGVZ+TT13U+z8oSEP9/rxPgmnQDCf93ESSxqgbifiY878uNYzasYmCiukX4sMzK8wNL3sQEWCxt3tBS4yU4hus2uqH+2TM0wBT+QpoLWXGAK6AWouKo= ARC-Message-Signature: i=1; a=rsa-sha256; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id i1sm6516207wmq.12.2021.03.03.13.47.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:47:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UQM81mur+9UHjxbQN0Zv4wGjBmPMsrfz+L5iL9ZySpM=; b=HuJJwRmQm/WNOwG0i0A956QWH6H100m0JkDutpdpBZXuu/7RBFufc96trr+qP0h/i7 szkhInTF9ujPv4lnxTuYB/vn4oniSp09pr6ETBqkqrWm+0EK3Fxl71k2J7trHUiWTW9p lwFMy4VhPTnjVy9GyZGlZGRPh/+OBf1LcV0XONqrpc8HyyTFgYx+cPot7b6rGACmbK/W dS8GiTIl0slZmoPXWKMsw2UHEG/YlF9EVjBbwsORGh8uDuAq74258iuj9aIVG82OZ2VS JGU8QKblTOFSquBrtbwhKIAF7piCIyibLMQoy+/ysvpRZflRnTAuQznhb8L4001AtFqB 7eiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UQM81mur+9UHjxbQN0Zv4wGjBmPMsrfz+L5iL9ZySpM=; b=WipSMBDKeXuEY34xXGM1R1oMy/c7J4sXClRFSkLEyr1TOz77gI8y21pP9tFtMwbPNU saeG+TyZh7zi5zI0bp1LSa4cpmS+gw0jMqIhI+FfUBNj5MwNDokp/LEKgcpQbAK/SQpr jP8FrGLHpy4AWDtVKDrfz7vjgcswP53f0Mdxc+d6a9gbsqp26JiHGkz5jkSYKO7Yx02j WRrjADEMd4t5WVcfZjxoug3kCHB+/f5zq+lA6cDC6DboT8cx4MlZRCJVKuSLwD/oJK4o GkZ9zUegTRGtdqVK7M+mQCJnn/HbE3UVwuu/Dd1qUg7dg2X6+PzYKe2MlWH05XO0yFO7 1P1g== X-Gm-Message-State: AOAM533kMcS/bCn6L1t9sIRf5jBhdDGnLLDgV0q3iO1lRkw86aPM3QJr Y+9YdsD/f4wPqYcuYPciNX8= X-Google-Smtp-Source: ABdhPJzxS2VzZOvh/vxiv32QSoXBqRD0SUS3vVBgJQmaWmg7PAPBa+svtupAyEDVFXt/BahNUtcokQ== X-Received: by 2002:a1c:4182:: with SMTP id o124mr848914wma.61.1614808041190; Wed, 03 Mar 2021 13:47:21 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 02/28] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Date: Wed, 3 Mar 2021 22:46:42 +0100 Message-Id: <20210303214708.1727801-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 33 ++++----------------------------- hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c005d3dc2d8..2d43f78819f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -578,18 +578,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags); * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr ad= dr, - MemTxAttrs *attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); - } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); -} +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); =20 /** * cpu_get_phys_page_debug: @@ -601,12 +591,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPU= State *cpu, vaddr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) -{ - MemTxAttrs attrs =3D {}; - - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); -} +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 /** cpu_asidx_from_attrs: * @cpu: CPU @@ -615,17 +600,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState = *cpu, vaddr addr) * Returns the address space index specifying the CPU AddressSpace * to use for a memory access with the given transaction attributes. */ -static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - int ret =3D 0; - - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); - assert(ret < cpu->num_ases && ret >=3D 0); - } - return ret; -} +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 #endif /* CONFIG_USER_ONLY */ =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..4dce35f832f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu, error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_phys_page_attrs_debug) { + return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + } + /* Fallback for CPUs which don't implement the _attrs_ hook */ + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return cc->get_phys_page_debug(cpu, addr); +} + +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +{ + MemTxAttrs attrs =3D {}; + + return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); +} + +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + int ret =3D 0; + + if (cc->asidx_from_attrs) { + ret =3D cc->asidx_from_attrs(cpu, attrs); + assert(ret < cpu->num_ases && ret >=3D 0); + } + return ret; +} + /* Resetting the IRQ comes from across the code base so we take the * BQL here if we need to. cpu_interrupt assumes it is held.*/ void cpu_reset_interrupt(CPUState *cpu, int mask) --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808049; cv=none; d=zohomail.com; s=zohoarc; b=Mun+24dD49O9M61M/t+YspFd8WP0QZOLuGtN+P2TtXOSjOPOiDEiVEjsEfHXf2pV7QK2kQDLvprtuoeqyTluxDW/+QKnFqoU/dhDNugntW8RAQsSA4dw7cv2Ku6n9MUulxZfzSkPXyjX1yuXHjVUICo/eMRF2Vh/okic4iIAFX4= ARC-Message-Signature: i=1; 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Tsirkin" Subject: [PATCH v4 03/28] cpu: Introduce cpu_virtio_is_big_endian() Date: Wed, 3 Mar 2021 22:46:43 +0100 Message-Id: <20210303214708.1727801-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the cpu_virtio_is_big_endian() generic helper to avoid calling CPUClass internal virtio_is_big_endian() one. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 9 +++++++++ hw/core/cpu.c | 8 ++++++-- hw/virtio/virtio.c | 4 +--- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2d43f78819f..b12028c3c03 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr ad= dr); */ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 +/** + * cpu_virtio_is_big_endian: + * @cpu: CPU + + * Returns %true if a CPU which supports runtime configurable endianness + * is currently big-endian. + */ +bool cpu_virtio_is_big_endian(CPUState *cpu); + #endif /* CONFIG_USER_ONLY */ =20 /** diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 4dce35f832f..daaff56a79e 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu= , uint8_t *buf, int reg) return 0; } =20 -static bool cpu_common_virtio_is_big_endian(CPUState *cpu) +bool cpu_virtio_is_big_endian(CPUState *cpu) { + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->virtio_is_big_endian) { + return cc->virtio_is_big_endian(cpu); + } return target_words_bigendian(); } =20 @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; - k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 1fd1917ca0f..fe6a4be99e4 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endia= n(void) =20 static enum virtio_device_endian virtio_current_cpu_endian(void) { - CPUClass *cc =3D CPU_GET_CLASS(current_cpu); - - if (cc->virtio_is_big_endian(current_cpu)) { + if (cpu_virtio_is_big_endian(current_cpu)) { return VIRTIO_DEVICE_ENDIAN_BIG; } else { return VIRTIO_DEVICE_ENDIAN_LITTLE; --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808053; cv=none; d=zohomail.com; s=zohoarc; b=gfU1xXem1QSFLh6jtSIYv+m8KjM/q0OiPZmC8aLWxVzf9nsFEz856cpc0qLZQuIyU/Rv1Z7EsoaGBFQWBGDJ2fPwKYNswO4cLyrq4EP6NF0uWfJFizd5kj1/Pdlzh9UO5PxIGTUeF6ub8MKBHwfBNJK6ZieHFslzVuuRIwzMfg8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808053; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VJm0iGgu/pocJ2Vudv8ibS2Ot9Xd+ih0+p5aBEZz7PY=; b=MPhsJmzH79wF9AxnfxdfeBL3+qgz/aRRt57LFvfo0lmYQpgOe2paRkYDUniFf/0X194LjvS4EDps71NONVh2tuWFeTTRJN3VMCTwqlN/KUCUPsrTeHgeuFpEesPBN0BJlZJQbfc62BN+x9CrIlQYJCuxiDKjiBtqn10M4CGOLa8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1614808053258137.542237566656; Wed, 3 Mar 2021 13:47:33 -0800 (PST) Received: by mail-wr1-f48.google.com with SMTP id h98so25338323wrh.11 for ; Wed, 03 Mar 2021 13:47:32 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id e1sm6300140wrw.85.2021.03.03.13.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:47:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VJm0iGgu/pocJ2Vudv8ibS2Ot9Xd+ih0+p5aBEZz7PY=; b=ifqZqtDqhOgY5uLlul8CZC2+PlZhTINOhh0kNI68/3gI2CUuK5DNuuPAdktT6AkgiI YQnfr0bGkGXpuUexxjKr1Ay1NlTBG9t9pvRbGRZQyAtjY3t2ypgILRMdq2GY+RmC0Kgb 2LWSL97EFxySaGYlQidHhuNiM5ugkNLYhec3P0I1jFmnMcEEnNkXe9mcuEqNfS7oHjwH pkIguz6PFbMM1I2WL3AzWLpu/hDelAW/sq79X2xCVQiSksxu19G/ym9kxXImCvTvrUqX umYOBDzT71Z1sqPMk4jVOuaQSffSssMCmLbJGaTzhlS2PeJ01fU8nqNnbKMAWGFg6e6G lHHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VJm0iGgu/pocJ2Vudv8ibS2Ot9Xd+ih0+p5aBEZz7PY=; b=eT1TMlCVQF11kmhqjPfu5QV7DJPgx7KAH/Q6FzyZP1lY79w76FMxStyfLJYnj/B9Xd eeElWU/5EzH7YL2KWBn1g9MOK3UGHeIWPx72QiTUh+NsDkFCQg53mrI4BAfL+4pTrc/l akws6RHFdiZWRdjGFp3lregsYQt/zsMyxiihnTMMAbagnc5+hFke8KiuV0bTXmI06JKX t3ziIeXdIBuIiHEDNxMq1tbLOf6l98Vw/W1/SJI8QoR4o3sY96i9PjZKwa3UjVFABJ+F 5L61nhd4bVeCyFdk8QlLA+QuDGPs+Fr7ZeYTPal3lZQ8p1Zv0FIJsc1Ux4pccTKlJbzp Y1gQ== X-Gm-Message-State: AOAM532SoNfNTXWeWxKL3aYC2+46mvTvaNzzCLd+fq7Grpk54UeBOwW1 /Xnuflmr2COFn+BcM4aW9nE= X-Google-Smtp-Source: ABdhPJx7+hJT7rzIyQPksMqjdWusZ/CddoRC+72dPVEWnznIKRRTNju+ViqG8Y+Kl8UyxTVe8tMLrA== X-Received: by 2002:adf:e411:: with SMTP id g17mr664079wrm.225.1614808051551; Wed, 03 Mar 2021 13:47:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 04/28] cpu: Directly use cpu_write_elf*() fallback handlers in place Date: Wed, 3 Mar 2021 22:46:44 +0100 Message-Id: <20210303214708.1727801-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code directly accesses CPUClass::write_elf*() handlers out of hw/core/cpu.c (the rest are assignation in target/ code): $ git grep -F -- '->write_elf' hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque); hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque); hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:440: k->write_elf32_qemunote =3D cpu_common_write_elf32_= qemunote; hw/core/cpu.c:441: k->write_elf32_note =3D cpu_common_write_elf32_note; hw/core/cpu.c:442: k->write_elf64_qemunote =3D cpu_common_write_elf64_= qemunote; hw/core/cpu.c:443: k->write_elf64_note =3D cpu_common_write_elf64_note; target/arm/cpu.c:2304: cc->write_elf64_note =3D arm_cpu_write_elf64_no= te; target/arm/cpu.c:2305: cc->write_elf32_note =3D arm_cpu_write_elf32_no= te; target/i386/cpu.c:7425: cc->write_elf64_note =3D x86_cpu_write_elf64_n= ote; target/i386/cpu.c:7426: cc->write_elf64_qemunote =3D x86_cpu_write_elf= 64_qemunote; target/i386/cpu.c:7427: cc->write_elf32_note =3D x86_cpu_write_elf32_n= ote; target/i386/cpu.c:7428: cc->write_elf32_qemunote =3D x86_cpu_write_elf= 32_qemunote; target/ppc/translate_init.c.inc:10891: cc->write_elf64_note =3D ppc64_= cpu_write_elf64_note; target/ppc/translate_init.c.inc:10892: cc->write_elf32_note =3D ppc32_= cpu_write_elf32_note; target/s390x/cpu.c:522: cc->write_elf64_note =3D s390_cpu_write_elf64_= note; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/core/cpu.c | 43 ++++++++++++------------------------------- 1 file changed, 12 insertions(+), 31 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index daaff56a79e..a9ee2c74ec5 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_qemunote) { + return 0; + } return (*cc->write_elf32_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_note) { + return -1; + } return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_qemunote) { + return 0; + } return (*cc->write_elf64_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_note) { + return -1; + } return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - - static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) { return 0; @@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *d= ata) k->has_work =3D cpu_common_has_work; k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; - k->write_elf32_qemunote =3D cpu_common_write_elf32_qemunote; - k->write_elf32_note =3D cpu_common_write_elf32_note; - k->write_elf64_qemunote =3D cpu_common_write_elf64_qemunote; - k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808058; cv=none; d=zohomail.com; s=zohoarc; b=Y1pC/kPrMNFAK89FHvmJ8x1x39EdslybgtW31+dMu8EUdXCkb+bbAc7Phm56ykRZURjEXt6/Ayn6YAbhJf12b2B+FXHWsboAPgiqfTkFqDV1sSIfcQ/n11b4ljCGtHqtMO5Hhn5twaCIKglIQk5HB5sJBkoamgo7HDHK0wdZLys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808058; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yI5v3ChjpgUoMVznW3/vQVCaXLpm+f+cFTMRG3SQklk=; b=A7h8dsolI0uhztQndZe4880fCj587aw2M9WMszqBcGxvXXWk9ryP8mv7CaGeU1ZUNijhOlw9WbhQnZtnn9tW8ZJVgead/IokSOiYCoobSDzZgWcuFVQf3k/mgg4fFwnP8Cviw0wrg9CV8m32Lv48bM5oJVSRzQ/JvdCgtveuOSU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1614808058435500.33881341586095; Wed, 3 Mar 2021 13:47:38 -0800 (PST) Received: by mail-wr1-f53.google.com with SMTP id u16so7362978wrt.1 for ; Wed, 03 Mar 2021 13:47:37 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id w18sm7480294wrr.7.2021.03.03.13.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:47:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yI5v3ChjpgUoMVznW3/vQVCaXLpm+f+cFTMRG3SQklk=; b=sXWy4MUACGSPd5NPgWXirQrkFX+fN6+K9/FZbmETAlGkcqp9FiygCi31bkTrCoJbj7 Jfo6zVqQJzWbYtuhbNcLpyAf7HX5TBRNw/yQAlGkoS8emkCU3otkO0UtRrXnjl9d7vkM wjLRDOf6yaWNxB45UKkCY1Npx6GrM25/H1aqWZekSWNYASr7QqG2rk+ED+nciimTfwd1 TdZVcTicRlHbda5DJ0VU8Df95AkI90VVEr0aJgElN0CnQaY45+x75+bko/r0XicA9f9m bxvuPgVeOFzMQ3MNuhTYQFWTNEQlW8H69wzskpLmGnioyime3W5KpO2n9IU6lRvzllCl zLCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yI5v3ChjpgUoMVznW3/vQVCaXLpm+f+cFTMRG3SQklk=; b=LjfP5jRwwWuSTCoIeA3j3ZRfozNEgsNnVdR40YHN6xjs7D3JCLNALc1+01IlCh/BO1 f09BdzBXzxCbZzt18i6FhH8mFD1Z3DfYK7OKTJcPNhtoUakOzAAJ/Hij71ZhUQ8DOz+W Xv2bj3iGBJxYfyE4CcK+9Ezngw3lu+XPSjpcSa4+5qnU0x86ycBnfqN0abWGhW6WASb+ npzrRfVRRpkSqkEEW5rWxr+R0cS+xIQACeA1YGL6Xp+jddvgbfAM2lfuCI7CvKuigupA ba6EYxv2VJFxrtNGx4gSFlgTe/Uz6JctPqYSBag6SHNB/p134bcMHw8xHD2uiR7FYl/G rziA== X-Gm-Message-State: AOAM531B7JW5Fnc2N8rcUO0oQDvuRHqmkG8Ad+heMzTnYcWPuFxYA8Ud MwchVJZc8SVlu5cxLTj5MQI= X-Google-Smtp-Source: ABdhPJxqIH0Ww3giDB0byK+vFGzlNSpnTwVJ2DfY3n21Z3+TTxvouratr/T8dvTbD0znc0f84r1NpQ== X-Received: by 2002:a5d:53c8:: with SMTP id a8mr652242wrw.323.1614808056742; Wed, 03 Mar 2021 13:47:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 05/28] cpu: Directly use get_paging_enabled() fallback handlers in place Date: Wed, 3 Mar 2021 22:46:45 +0100 Message-Id: <20210303214708.1727801-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c: $ git grep -F -- '->get_paging_enabled' hw/core/cpu.c:74: return cc->get_paging_enabled(cpu); hw/core/cpu.c:438: k->get_paging_enabled =3D cpu_common_get_paging_ena= bled; target/i386/cpu.c:7418: cc->get_paging_enabled =3D x86_cpu_get_paging_= enabled; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/core/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index a9ee2c74ec5..1de00bbb474 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - return cc->get_paging_enabled(cpu); -} + if (cc->get_paging_enabled) { + return cc->get_paging_enabled(cpu); + } =20 -static bool cpu_common_get_paging_enabled(const CPUState *cpu) -{ return false; } =20 @@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808063; cv=none; d=zohomail.com; s=zohoarc; b=VRDQIcgwA9lhf/wz2pbAlqUuJlPCm+QW1BAub9+AlVOABh914RuxV08DQ+aFkx2hYt56dz/eHLScyUJbeBBXmsyMnIGEpK+6ST8nyI5k4VkQ9iz1meGOychpTyLwxE+chu2EixXECl/eA93KqbCpF4m2BCyNaiANyCTFEE433b4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808063; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iDkHmNWDJUjsisDNEA+tDXF79jqbgWv+Yeaa+F2Cdm4=; b=bcIGaOuOIXL2pzqqcwqtkN0Or/pkLePjWHj3FJqEr/8bN5cvuEfILZZcsZxsmstW0qpvHF3Fz66wUVVESd58pA7YQ5kCYSRd8E1TR++LBpo4hCJW27HhWRLrFzI0ANBqL5UF0ygKcKEpnIIWRLUEM/NnrF6kazFg4mX1Hh1VUj8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.zohomail.com with SMTPS id 1614808063680892.1899715329585; Wed, 3 Mar 2021 13:47:43 -0800 (PST) Received: by mail-wm1-f46.google.com with SMTP id i9so6347562wml.0 for ; Wed, 03 Mar 2021 13:47:43 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id g9sm6935176wmq.25.2021.03.03.13.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:47:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iDkHmNWDJUjsisDNEA+tDXF79jqbgWv+Yeaa+F2Cdm4=; b=ZgbC2jy6AG+RLur1BjIecSk+qs2lJQd1qYBzQYFFcQVKLdTR2adqVQhR+BNuxjrOn0 RovMZS38gTe2c5ML2yGa47NrUOeUfVBG0t3wHT4Yl1LTYeflXoiOlJIyeoElw/1E8rsx WiED4I0tprqnt2AzsUZIz0lIEVwncf+7i0er2v24jxYE9M8PxZ25o+p3M5GVrcSFFd9U H9qJHKUhtx+dY6DO7M6iKmiBb4bgCqJRnqkjIKsn1mAibxOlp+NPbOPeFHQzUQn9bi+Z Vx3OaOKBcnYKDLDoKDEvdLHr15dwbiuJra+ps/y+7KCVXeatb0ZSrV2FWBbw+ulzwR6a erGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iDkHmNWDJUjsisDNEA+tDXF79jqbgWv+Yeaa+F2Cdm4=; b=XdQjbcjXsAsmSBD1RhSH1Bs6jP7r3nOzynem6PAwdGIAjfeaA8mB92JfONBpEFwlVC o4MYBRFkj4SpLWVXPNKiaLnfCQ5vTEwtxLgEkNtK7JEib9R4Kh1re8vtg4JMayH504Vq rlwTjRm5FnsqknxIP5KomCijgOz/C5SLT/Yob+auRWxMe82O6ah5XxigxYQsVPUR6oQ+ NE62aea42HJj1IXofhMmo4xJfdmabEwwGMQ7eLPEUBPGMK3AXI/neh5d0z5REfwkbDJ0 Dk8gQ844qGQdE0T4NnhHGD+aizfsSlD/daltUnHKf95NPTZeVgd9Xd5XzcGdUoT7G9rC WbNA== X-Gm-Message-State: AOAM53121c7dRDTRfK7Ys7dwjyMzfhQMmNZG35+usANx080vl0lDox05 1nNzHD/ymbaf4fKQy+q5G0w= X-Google-Smtp-Source: ABdhPJyFd5xk9OkNc9a2uHS1GRZjG6YVKtiIkDjU8POlwni8ZQ8Ge8hXSIMDlcTDzIJM24ntPHcndA== X-Received: by 2002:a7b:cd04:: with SMTP id f4mr812149wmj.81.1614808061943; Wed, 03 Mar 2021 13:47:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 06/28] cpu: Directly use get_memory_mapping() fallback handlers in place Date: Wed, 3 Mar 2021 22:46:46 +0100 Message-Id: <20210303214708.1727801-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c: $ git grep -F -- '->get_memory_mapping' hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp); hw/core/cpu.c:439: k->get_memory_mapping =3D cpu_common_get_memory_map= ping; target/i386/cpu.c:7422: cc->get_memory_mapping =3D x86_cpu_get_memory_= mapping; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/core/cpu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 1de00bbb474..5abf8bed2e4 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappin= gList *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->get_memory_mapping(cpu, list, errp); -} + if (cc->get_memory_mapping) { + cc->get_memory_mapping(cpu, list, errp); + return; + } =20 -static void cpu_common_get_memory_mapping(CPUState *cpu, - MemoryMappingList *list, - Error **errp) -{ error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 @@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808070; cv=none; d=zohomail.com; s=zohoarc; b=F2g9H19Yl7fayV/9pnoJlCro0CQ0MyaaCFUCV4dYfIPHCyXJumDul0/IP0+62/R+TYWV6sNWepjHLJRrS8EUTstpkI1t/rVQJiVsC4G7F25kFsr76f7P4apt2wxf8C83graykfMiZBwU6fZks4UpFSnttlHTsaPFixLxn7OtY+4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808070; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8nwRWzveSDXnTRlevCzDcw5mN814sllYPgfUs9XTDuI=; b=XkYLtVNNbcHKG7F/GS8BfqPNzyPHRYRLlywo1lOac59gM0qePqrLzvG3fWhzI0VrHE2yVQq4mZScTewKeUL1wqeas2AyvjUDlFafyuFX0jRsUzGScMuX4mL6dSiZ0H9fHNNm20rWiCE//pza+tVQ5Jo0UCZ90Tr6D/8Z3o9+iiw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.zohomail.com with SMTPS id 1614808070349964.0866738331275; Wed, 3 Mar 2021 13:47:50 -0800 (PST) Received: by mail-wm1-f49.google.com with SMTP id k66so7674134wmf.1 for ; Wed, 03 Mar 2021 13:47:49 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id i8sm21942818wrx.43.2021.03.03.13.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:47:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8nwRWzveSDXnTRlevCzDcw5mN814sllYPgfUs9XTDuI=; b=DRSomd09uRSnJgxAdaY8yzuzlGnIbCz+x0MkUhvvC7mO7jDFfplscnbWxRSIJyQfNj 3uZObkx0yQy+VhuEGeSbED06WN4Af7QDzLH5Wa28ceaKO/8I0Af2g5DbEqdRick/AMks kWLOcDqZnjohtCMVGKZhsZtunuU+FNJtl+gfYD883iT8q+oM1sHBGNsMBLR/HW00NVeF JA30fkTM9RQW9Ya/O5AkWk6dFYNiLlxAB7CUlIfhgtfMXs7RgKuCkmxtY0HeurTed9Mn sZTLB2vKuj1vnQgV4TXtxXt7xI3lccagUOvaH63XVLskMnGGpzI3YztU2Rz1CX3PLblX L11A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8nwRWzveSDXnTRlevCzDcw5mN814sllYPgfUs9XTDuI=; b=LzW+TXT3ri0Sy/gMyAT+xT68e1BJVjKm1QmGZhIoTbYTNOQEAvucPBnoWl83VIhXCs uzPrG612Odnuz74PFRhVE2PFoDxKfCL3cmXVLZQxQgGwHtvpkHRuVILqN7Z90Ciy/nwf 55Q1H2wb6ve41rSZAKJ26v+tjMEnnLrxuv6vQu0VoZwy5o9aCZMWDJzFzDm0bLD9mavT dPEFM83n66yUHDSv1jSP+1L/pi/TVnWBBDMNTh8EYC2mmqAFpE9w87mWtDuM2oWAX1fT o5h91c4wXrnJt+NKH9hozZQyVaUqjCf/axzr7uW7fbc+RQrhL8vgXm/CBRuEQu1DJ2OI e2uA== X-Gm-Message-State: AOAM5303Nxsl8mxfoQolTVglvaSeL8xwG7zbt3plti7EhfUACk/zR4Hw VVETffy+UsKsG4xG7e7ScAg= X-Google-Smtp-Source: ABdhPJz9LiiClOUsy02SiaOCWQDWd4uACUCAXFEbEcd1Sgw0/pAF+jVocH4c6iYKQ78WWEqrLILUlg== X-Received: by 2002:a1c:b789:: with SMTP id h131mr862398wmf.106.1614808068393; Wed, 03 Mar 2021 13:47:48 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Michael Rolnik , Sarah Harris , "Edgar E. Iglesias" , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v4 07/28] cpu: Introduce SysemuCPUOps structure Date: Wed, 3 Mar 2021 22:46:47 +0100 Message-Id: <20210303214708.1727801-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 5 +++++ include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++ target/alpha/cpu.c | 6 ++++++ target/arm/cpu.c | 6 ++++++ target/avr/cpu.c | 4 ++++ target/cris/cpu.c | 6 ++++++ target/hppa/cpu.c | 6 ++++++ target/i386/cpu.c | 6 ++++++ target/lm32/cpu.c | 6 ++++++ target/m68k/cpu.c | 6 ++++++ target/microblaze/cpu.c | 6 ++++++ target/mips/cpu.c | 6 ++++++ target/moxie/cpu.c | 4 ++++ target/nios2/cpu.c | 6 ++++++ target/openrisc/cpu.c | 6 ++++++ target/riscv/cpu.c | 6 ++++++ target/rx/cpu.c | 8 ++++++++ target/s390x/cpu.c | 6 ++++++ target/sh4/cpu.c | 6 ++++++ target/sparc/cpu.c | 6 ++++++ target/tricore/cpu.c | 4 ++++ target/unicore32/cpu.c | 4 ++++ target/xtensa/cpu.c | 6 ++++++ target/ppc/translate_init.c.inc | 6 ++++++ 24 files changed, 152 insertions(+) create mode 100644 include/hw/core/sysemu-cpu-ops.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b12028c3c03..3c26471d0fa 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,6 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 +#include "hw/core/sysemu-cpu-ops.h" + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -190,6 +192,9 @@ struct CPUClass { bool gdb_stop_before_watchpoint; struct AccelCPUClass *accel_cpu; =20 + /* when system emulation is not available, this pointer is NULL */ + const struct SysemuCPUOps *sysemu_ops; + /* when TCG is not available, this pointer is NULL */ struct TCGCPUOps *tcg_ops; }; diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h new file mode 100644 index 00000000000..e54a08ea25e --- /dev/null +++ b/include/hw/core/sysemu-cpu-ops.h @@ -0,0 +1,21 @@ +/* + * CPU operations specific to system emulation + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef SYSEMU_CPU_OPS_H +#define SYSEMU_CPU_OPS_H + +#include "hw/core/cpu.h" + +/* + * struct SysemuCPUOps: System operations specific to a CPU class + */ +typedef struct SysemuCPUOps { +} SysemuCPUOps; + +#endif /* SYSEMU_CPU_OPS_H */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index faabffe0796..663b1a4fc4e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps alpha_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps alpha_tcg_ops =3D { @@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_alpha_cpu; + cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b8bc89e71fc..1fe3c4ab273 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2260,6 +2260,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs) return g_strdup("arm"); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps arm_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG static struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, @@ -2303,6 +2308,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; + cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f4596932ba..78ef4473c50 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) qemu_fprintf(f, "\n"); } =20 +static const struct SysemuCPUOps avr_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps avr_tcg_ops =3D { @@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; cc->vmsd =3D &vms_avr_cpu; + cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 29a865b75d2..2e447bbf8bc 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps cris_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps crisv10_tcg_ops =3D { @@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_cris_cpu; + cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4f142de6e45..4bc4fdbf105 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char = *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps hppa_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps hppa_tcg_ops =3D { @@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_hppa_cpu; + cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 50008431c35..d9ed1972eeb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7386,6 +7386,11 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps i386_sysemu_ops =3D { +}; +#endif + static void x86_cpu_common_class_init(ObjectClass *oc, void *data) { X86CPUClass *xcc =3D X86_CPU_CLASS(oc); @@ -7427,6 +7432,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->vmsd =3D &vmstate_x86_cpu; + cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c23d72874c0..15935ae7ceb 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char = *cpu_model) return oc; } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps lm32_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps lm32_tcg_ops =3D { @@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_lm32_cpu; + cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c98fb1e33be..caa606303f7 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -502,6 +502,11 @@ static const VMStateDescription vmstate_m68k_cpu =3D { }; #endif =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps m68k_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps m68k_tcg_ops =3D { @@ -534,6 +539,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_m68k_cpu; + cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 335dfdc734e..99c3def0ce6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *c= pu_model) return object_class_by_name(TYPE_MICROBLAZE_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mb_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps mb_tcg_ops =3D { @@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; cc->vmsd =3D &vmstate_mb_cpu; + cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bf70c77295f..c8edc1f6ffa 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -680,6 +680,11 @@ static Property mips_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mips_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_mips_cpu; + cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; cc->gdb_num_core_regs =3D 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 83bec34d36c..2cd631a7304 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) return oc; } =20 +static const struct SysemuCPUOps moxie_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps moxie_tcg_ops =3D { @@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; + cc->sysemu_ops =3D &moxie_sysemu_ops; cc->tcg_ops =3D &moxie_tcg_ops; } =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a389..296ccc0ed3c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -207,6 +207,11 @@ static Property nios2_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps nios2_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps nios2_tcg_ops =3D { @@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 79d246d1930..7819413eeb3 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj) | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps openrisc_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps openrisc_tcg_ops =3D { @@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_openrisc_cpu; + cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16f1a342388..5e7efcf3feb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -580,6 +580,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState = *cs, const char *xmlname) return NULL; } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps riscv_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps riscv_tcg_ops =3D { @@ -624,6 +629,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->vmsd =3D &vmstate_riscv_cpu; + cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26b..bbee1cb913f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps rx_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps rx_tcg_ops =3D { @@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; =20 +#ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &rx_sysemu_ops; +#endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d35eb39a1bb..36085035d1f 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev) return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps s390_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; + cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index bd44de53729..c3cdb08e0b2 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -223,6 +223,11 @@ static const VMStateDescription vmstate_sh_cpu =3D { .unmigratable =3D 1, }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps sh4_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps superh_tcg_ops =3D { @@ -257,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &sh4_sysemu_ops; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index aece2c7dc83..a5dde9f7dd9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps sparc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_sparc_cpu; + cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcba..8865fa18fce 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +static const struct SysemuCPUOps tricore_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps tricore_tcg_ops =3D { @@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 12894ffac6a..1c89168f172 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu =3D { .unmigratable =3D 1, }; =20 +static const struct SysemuCPUOps uc32_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps uc32_tcg_ops =3D { @@ -147,6 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_uc32_cpu; + cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6bedd5b97b8..28ad2a44878 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,6 +181,11 @@ static const VMStateDescription vmstate_xtensa_cpu =3D= { .unmigratable =3D 1, }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps xtensa_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps xtensa_tcg_ops =3D { @@ -215,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &xtensa_sysemu_ops; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index e7324e85cdb..6d50af8c67b 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10843,6 +10843,11 @@ static Property ppc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps ppc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -10886,6 +10891,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_ppc_cpu; + cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808077; cv=none; d=zohomail.com; s=zohoarc; b=m87CxZtLetmhI/5JzaWGsm+gwukqMM9bT640Hham7QWc+U5IFQu+iQw7d/W1cUpBFH9LmV4H1POQNgKAKzzvwQbzDRxG6ilbCb7wVeXNOnJjSlbF73PZsBBmJdmYMJh9QEpnEE6G/53Q2b4kLO3f/qSV6U9h6pU25xGhSs2AYzA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808077; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id l15sm6990982wme.43.2021.03.03.13.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:47:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cSKVByIcRj2NwPCx616UOTTg18c0IIvEpRg0z+kyxys=; b=jA+01ZBm9eibklgJ0w4xO5HAGYPhAiq+Fqfrl0bdY7CpL3uiamWFj5nzZVIyiO3Y3R 0yPPgFrSxcPHsIv2uhXtAciPy9UGvZoqTSSEs5mACp16MXGr6wuQVEZ+mnHY5LqgiKNG plLQtOen9Oqip4zn/haiyfm7jRqcookS1vE+in4AHLi/pkw/WVnr/hgwvSu06xT1ygLK 7KdKFDhZfpARuVH44EKp5LC4OdmbGeTMAweFWe7YZhhCWH8w9p62sxBnIe8/EbNcxcsN 5J6lU4csKghU/tmkDSPon9my2qzh+Z0RxfywFxggGkYgUPY84v075cuThHOtPvqDUfuc chsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cSKVByIcRj2NwPCx616UOTTg18c0IIvEpRg0z+kyxys=; b=XBWgHbZ9kFiHzHuXuVuv5Urn5IYImLlkHNeav+iyHDgYfknOtkqI6jzSvUmPO26ttY Wh9YMuHjTK3Uu+mXrBPuMy2SEukk6cyb+63bwyVkhaEptpRg0coUMH2LQTzaBExzXcet 1ewgPV5cD2z19com4CS3vI/qc/e52ywW/waK1yPdao/E9Ekl8LnjqUreKGReJkYwGxh8 22rOFpeA8l5D+F05gv5K2jHvEDdBcvp2FG2ACRvYNQfr1YYRUL0h6unmPFeRQ0YXSwS7 HGjmWAiXqUIQ6MPrGhMXCTdQ/SE1WktSd3TFGgfUKdaSwKz362YwwJ5Ea+aeA6CZpE5H DBHg== X-Gm-Message-State: AOAM533bvmqux6UyPSm6xT4LjXCvXQ8bz86/MttLQTemJh9PuEGQEMZ5 nOL9tt8cCdzEsTWhCZtrRiQ= X-Google-Smtp-Source: ABdhPJy/l09EpkJgQtuvxh83oYKfGpB57EfcbTNEYGaxGs8U5UoZb7myu1kXqHYUtDA9aBctYMw/tg== X-Received: by 2002:a1c:e184:: with SMTP id y126mr815522wmg.163.1614808075259; Wed, 03 Mar 2021 13:47:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Michael Rolnik , Sarah Harris , "Edgar E. Iglesias" , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v4 08/28] cpu: Move CPUClass::vmsd to SysemuCPUOps Date: Wed, 3 Mar 2021 22:46:48 +0100 Message-Id: <20210303214708.1727801-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Migration is specific to system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 2 -- include/hw/core/sysemu-cpu-ops.h | 4 ++++ cpu.c | 18 ++++++++---------- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 7 +++++++ target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 4 ++-- target/rx/cpu.c | 6 ++++++ target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 7 +++++++ target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 4 ++-- target/ppc/translate_init.c.inc | 2 +- 25 files changed, 54 insertions(+), 34 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3c26471d0fa..471c99d9f04 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -124,7 +124,6 @@ struct AccelCPUClass; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @vmsd: State description for migration. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -179,7 +178,6 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); =20 - const VMStateDescription *vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index e54a08ea25e..05f19b22070 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,10 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @vmsd: State description for migration. + */ + const VMStateDescription *vmsd; } SysemuCPUOps; =20 #endif /* SYSEMU_CPU_OPS_H */ diff --git a/cpu.c b/cpu.c index bfbe5a66f95..64e17537e21 100644 --- a/cpu.c +++ b/cpu.c @@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common =3D { =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); +#endif =20 cpu_list_add(cpu); =20 @@ -137,27 +139,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) } #endif /* CONFIG_TCG */ =20 -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else +#ifndef CONFIG_USER_ONLY if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + if (cc->sysemu_ops->vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } =20 void cpu_exec_unrealizefn(CPUState *cpu) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else - if (cc->vmsd !=3D NULL) { - vmstate_unregister(NULL, cc->vmsd, cpu); + if (cc->sysemu_ops->vmsd !=3D NULL) { + vmstate_unregister(NULL, cc->sysemu_ops->vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 663b1a4fc4e..de8f9c648fa 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps alpha_sysemu_ops =3D { + .vmsd =3D &vmstate_alpha_cpu, }; #endif =20 @@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_alpha_cpu; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1fe3c4ab273..403422c6e76 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .vmsd =3D &vmstate_arm_cpu, }; #endif =20 @@ -2304,7 +2305,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->vmsd =3D &vmstate_arm_cpu; cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 78ef4473c50..20a48bdfbab 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static const struct SysemuCPUOps avr_sysemu_ops =3D { + .vmsd =3D &vms_avr_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->vmsd =3D &vms_avr_cpu; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 2e447bbf8bc..c05707bad2c 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps cris_sysemu_ops =3D { + .vmsd =3D &vmstate_cris_cpu, }; #endif =20 @@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_cris_cpu; cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4bc4fdbf105..110cc8a6d68 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps hppa_sysemu_ops =3D { + .vmsd =3D &vmstate_hppa_cpu, }; #endif =20 @@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_hppa_cpu; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d9ed1972eeb..b8f056849a7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .vmsd =3D &vmstate_x86_cpu, }; #endif =20 @@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; - cc->vmsd =3D &vmstate_x86_cpu; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 15935ae7ceb..4ff54fd9204 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps lm32_sysemu_ops =3D { + .vmsd =3D &vmstate_lm32_cpu, }; #endif =20 @@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_lm32_cpu; cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index caa606303f7..e7ddcf2ee28 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps m68k_sysemu_ops =3D { + .vmsd =3D &vmstate_m68k_cpu, }; #endif =20 @@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_m68k_cpu; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 99c3def0ce6..8b86b99c15b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mb_sysemu_ops =3D { + .vmsd =3D &vmstate_mb_cpu, }; #endif =20 @@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; - cc->vmsd =3D &vmstate_mb_cpu; cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c8edc1f6ffa..ef997bcd67f 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .vmsd =3D &vmstate_mips_cpu, }; #endif =20 @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_mips_cpu; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 2cd631a7304..1e87f07ca73 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) } =20 static const struct SysemuCPUOps moxie_sysemu_ops =3D { + .vmsd =3D &vmstate_moxie_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -125,7 +126,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->sysemu_ops =3D &moxie_sysemu_ops; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 296ccc0ed3c..a785f3ea7b6 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -25,6 +25,7 @@ #include "exec/log.h" #include "exec/gdbstub.h" #include "hw/qdev-properties.h" +#include "migration/vmstate.h" =20 static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { @@ -208,7 +209,13 @@ static Property nios2_properties[] =3D { }; =20 #ifndef CONFIG_USER_ONLY +static const VMStateDescription vmstate_nios2_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static const struct SysemuCPUOps nios2_sysemu_ops =3D { + .vmsd =3D &vmstate_nios2_cpu, }; #endif =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 7819413eeb3..2149e9564fa 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps openrisc_sysemu_ops =3D { + .vmsd =3D &vmstate_openrisc_cpu, }; #endif =20 @@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_openrisc_cpu; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5e7efcf3feb..a6b1ff93299 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -582,6 +582,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + /* For now, mark unmigratable: */ + .vmsd =3D &vmstate_riscv_cpu, }; #endif =20 @@ -627,8 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; - /* For now, mark unmigratable: */ - cc->vmsd =3D &vmstate_riscv_cpu; cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index bbee1cb913f..f293f3630d0 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -174,7 +174,13 @@ static void rx_cpu_init(Object *obj) } =20 #ifndef CONFIG_USER_ONLY +static const VMStateDescription vmstate_rx_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static const struct SysemuCPUOps rx_sysemu_ops =3D { + .vmsd =3D &vmstate_rx_cpu, }; #endif =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 36085035d1f..fe908d9bc40 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .vmsd =3D &vmstate_s390_cpu, }; #endif =20 @@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index c3cdb08e0b2..8c1d0ba53b1 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -218,13 +218,14 @@ static void superh_cpu_initfn(Object *obj) env->movcal_backup_tail =3D &(env->movcal_backup); } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_sh_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; =20 -#ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sh4_sysemu_ops =3D { + .vmsd =3D &vmstate_sh_cpu, }; #endif =20 @@ -268,7 +269,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->gdb_num_core_regs =3D 59; =20 - cc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index a5dde9f7dd9..f5862e74baf 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .vmsd =3D &vmstate_sparc_cpu, }; #endif =20 @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_sparc_cpu; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8865fa18fce..9374f8440a0 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "qemu/error-report.h" +#include "migration/vmstate.h" =20 static inline void set_feature(CPUTriCoreState *env, int feature) { @@ -142,7 +143,13 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +static const VMStateDescription vmstate_tricore_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static const struct SysemuCPUOps tricore_sysemu_ops =3D { + .vmsd =3D &vmstate_tricore_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 1c89168f172..345b6e9e417 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { }; =20 static const struct SysemuCPUOps uc32_sysemu_ops =3D { + .vmsd =3D &vmstate_uc32_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_uc32_cpu; cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 28ad2a44878..fd65246015f 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -176,13 +176,14 @@ static void xtensa_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_xtensa_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; =20 -#ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps xtensa_sysemu_ops =3D { + .vmsd =3D &vmstate_xtensa_cpu, }; #endif =20 @@ -224,7 +225,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - cc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 6d50af8c67b..819b807097d 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .vmsd =3D &vmstate_ppc_cpu, }; #endif =20 @@ -10890,7 +10891,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_ppc_cpu; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808082; cv=none; d=zohomail.com; s=zohoarc; b=Dbm5D5geKrTPP4SogmtKJn4zwNUpULNN04zyjCRheBDRhZJ54bJKm0gpqsQAnlBqeqbtmpNG6fDZXhFSpFn91DHAMGK1YpKxAeTWVZZMiua6gOEDT7nMNKFrw7YrpWlj7zKN6QwYMwzn3wgQ8ih5tF0XRuFtx7plOo3eexsn4bA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808082; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id n6sm14034871wrt.1.2021.03.03.13.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:47:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KrfmTAy/y06Liy613dmSM4G3rbSLinZL5wmkGcBjQ6Q=; b=U7nX/qH/pj9vuhk5OuE9MYtkaxBeNOesC2soCFMJdLnuVOBjF9fFA2Oxp1pSweSYco wiu2WVgM2FCSZe6jF5bu6+cluDmDfoxu6fop027s/68r5SQR4PP8IBFu0JtfEioDLhmG nBu+3OLGVESAfbUgltl7btQsSf4TjkXd8v7u9QOCsSxnQtn6/pEH0JntEMT2OsPOK6bL GXqJnjOuGDbPKlepBghW2gklBTNHdmVIa+OiETZb4n10MDPzGJKDo8ybIa44w8MNXfUs RKZzDqxxq4SvpBmxqzJgP2HgjMAk/X2A6/cyDGZf76xz92b4eUiFmveD19kme9JBjC37 yMQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=KrfmTAy/y06Liy613dmSM4G3rbSLinZL5wmkGcBjQ6Q=; b=Kb7Pq/tC40TJ6/nnFVhg+ai/2MXbgeQySGrCm1z4X7paXzVUECC5xAmLD8V+NHHHPX qHxagVq7bmUFx/+vdFLxcb7je7kROYBQI3LKd/9TfvA4S2jGPnDDTDKE1W+VIXoEqiHJ yNMcg+939M2Ew/r1h59rpuxcq7aaVDDn8x6lLeXTxbW1b5omhjognNEoRRhn9yVUDhxY 3RcfPrDJhFNd4RkUykqXiUYdkppiQiFX/r39Bi470mx+zOf/hYcOFzshayS0QF9WiPUv gbL0N9LhSlD9RfvElammS6Dn+NRZCPPxshqobSQBEIQn76zNxiqhLmGKAVuXdMPlBztz OnBw== X-Gm-Message-State: AOAM533KU3V/bZsQTvnhUr8/vZqLvklf2//TzTpE3C/nlSNq1uECXvVf uJIjdU6X3y/sjUn2t86w+js= X-Google-Smtp-Source: ABdhPJwwJYH4kp+e2fr7J19qTnWtXIwYIOd2JbiU45YGKXBBTf8H5A5pvrhOuqeIbSub+9as3hur6w== X-Received: by 2002:adf:97d5:: with SMTP id t21mr675099wrb.139.1614808080451; Wed, 03 Mar 2021 13:48:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , David Gibson , Greg Kurz Subject: [PATCH v4 09/28] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps Date: Wed, 3 Mar 2021 22:46:49 +0100 Message-Id: <20210303214708.1727801-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) VirtIO devices are only meaningful with system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 5 ----- include/hw/core/sysemu-cpu-ops.h | 8 ++++++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/ppc/translate_init.c.inc | 4 +--- 5 files changed, 12 insertions(+), 11 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 471c99d9f04..dfb50b60128 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,10 +89,6 @@ struct AccelCPUClass; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @virtio_is_big_endian: Callback to return %true if a CPU which supports - * runtime configurable endianness is currently big-endian. Non-configurab= le - * CPUs can use the default implementation of this method. This method sho= uld - * not be used by any callers other than the pre-1.0 virtio devices. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. @@ -151,7 +147,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 05f19b22070..9c3ac4f2280 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,14 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts + * runtime configurable endianness is currently big-endian. + * Non-configurable CPUs can use the default implementation of this me= thod. + * This method should not be used by any callers other than the pre-1.0 + * virtio devices. + */ + bool (*virtio_is_big_endian)(CPUState *cpu); /** * @vmsd: State description for migration. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 5abf8bed2e4..09eaa3fa49f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->virtio_is_big_endian) { - return cc->virtio_is_big_endian(cpu); + if (cc->sysemu_ops->virtio_is_big_endian) { + return cc->sysemu_ops->virtio_is_big_endian(cpu); } return target_words_bigendian(); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 403422c6e76..fa0d4bba590 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .vmsd =3D &vmstate_arm_cpu, }; #endif @@ -2305,7 +2306,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 819b807097d..789124debe7 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .vmsd =3D &vmstate_ppc_cpu, }; #endif @@ -10913,9 +10914,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_core_xml_file =3D "power64-core.xml"; #else cc->gdb_core_xml_file =3D "power-core.xml"; -#endif -#ifndef CONFIG_USER_ONLY - cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif cc->disas_set_info =3D ppc_disas_set_info; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id w6sm12282220wrl.49.2021.03.03.13.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qFTBHcwtMLt6piI19qY9hIVE30tS0o+fHbwt4Y38uFg=; b=KQtjxa8q0oGu1P01ZHc+oTFvjQlJ2RKqckDvVT6RTLR1PDEEHrvrxVoTAzCNYHWo80 xBpq6O/SZh554bRL3TgBSl+OP6Nc9ZNudPNKHx2VqRjpYeKJ+UXNMMgm2IlSclBcmfDV 9ulqH1zn0OTBIS2ph46dudYv0N+tFC8b2M8Aw7anGhvbgmBSoyhmrpp9k0err+9GBfnE dqqJq3R0x9HAL7LIOuXzP3LLD1TSRQtC5qhoukDRqxK5COfT4+1/vulhzpcoCOzoW/eQ yj5WzfLibe7gLHigWZtWvU3h7Fj/wIKlqF+jH1QhLzDib8q8RTbxc6/MIddH3Q38ivV3 PcZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qFTBHcwtMLt6piI19qY9hIVE30tS0o+fHbwt4Y38uFg=; b=ZzxtqcsKK8Ht1bUaucLPzelxzv2WiyT3xsdZzJJFFuV8zggJWWfgwd2L1nl/VrsdwU tN7GoHDVV4YwxOMkhvkx30zdkd+PIWivXpwiszqlc7RHjbg6KOstzmuivJo3x0CXDZTO 0qh2XmGL0tECv6zMwSuhfiUjXN2MnXZ8rxor9NK6mE7Mqy9OP7A68klgI8lbln4IM2K+ CToHOccGEieNG7mYZoxNSjWuixCKSSg4FZv6wVTv1ag2qHOYgId4UClnmfebvW6FEu6e lVVsfcFEk02s0YW3Mzj/eoBoCVG431UeVYVrL9MD62dHVKjhzJFKRwxU3HNtWszXWTDS 9aow== X-Gm-Message-State: AOAM532nYSuO382eAEI0BKwQOQerIHWnR8nwHYHj8MV2x3AoG9L5qGEj g+YSXEanplnSvTKHj7rH1EA= X-Google-Smtp-Source: ABdhPJxMaEhVPf2fe/w19zrKLULEho24wRE6zwqlZ6aAS3z9ICzA5F4ZQ7d+oIM/Mkgue9RwcrMVPw== X-Received: by 2002:adf:a2c7:: with SMTP id t7mr804405wra.42.1614808085777; Wed, 03 Mar 2021 13:48:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , David Hildenbrand Subject: [PATCH v4 10/28] cpu: Move CPUClass::get_crash_info to SysemuCPUOps Date: Wed, 3 Mar 2021 22:46:50 +0100 Message-Id: <20210303214708.1727801-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) cpu_get_crash_info() is called on GUEST_PANICKED events, which only occur in system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 1 - include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- target/s390x/cpu.c | 2 +- 5 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index dfb50b60128..781cd8fc42b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -150,7 +150,6 @@ struct CPUClass { int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); - GuestPanicInformation* (*get_crash_info)(CPUState *cpu); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 9c3ac4f2280..b9ffca07665 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_crash_info: Callback for reporting guest crash information in + * GUEST_PANICKED events. + */ + GuestPanicInformation* (*get_crash_info)(CPUState *cpu); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 09eaa3fa49f..0aebc18c41f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) CPUClass *cc =3D CPU_GET_CLASS(cpu); GuestPanicInformation *res =3D NULL; =20 - if (cc->get_crash_info) { - res =3D cc->get_crash_info(cpu); + if (cc->sysemu_ops->get_crash_info) { + res =3D cc->sysemu_ops->get_crash_info(cpu); } return res; } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b8f056849a7..362ad56ab68 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_crash_info =3D x86_cpu_get_crash_info, .vmsd =3D &vmstate_x86_cpu, }; #endif @@ -7427,7 +7428,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->get_crash_info =3D x86_cpu_get_crash_info; cc->write_elf64_note =3D x86_cpu_write_elf64_note; cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index fe908d9bc40..fdc169bb0ac 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .get_crash_info =3D s390_cpu_get_crash_info, .vmsd =3D &vmstate_s390_cpu, }; #endif @@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id n6sm14035298wrt.1.2021.03.03.13.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YXKlTeCnjmHxOIuW+5ok+sHuvv9dHK5aHCAXQUqIY0w=; b=SEZ4KBDcFeAeqQ/5JtNtzvNXQgdGlZcbsKkoAldLMpqwQ9bM41viT6moaATrG27Cr4 sGitvPcB72EwpGsEuLWBOOZmA8cXMbO07pI+gmawAbmszagWVVKsNmzqTTnh4zLC92jl EquBq+ZStJ59VTrs63E1q+52qQZtMXEOfG8tnW7VpZBVtKQEaWrQ3UgvZsy1UuuMhCeY E3mqMQKxTpSONYg5tWR9sz40hWl091Tmg521XJahoHdJSdv/RqVsVpi8pY0DcXd7Vz8/ 53aFHfWPNUDarS4ewUItcEcl1J6cH8fEMNCu10bGuHCEyLOlETy1gq/I10d+mgVduaM6 O3YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YXKlTeCnjmHxOIuW+5ok+sHuvv9dHK5aHCAXQUqIY0w=; b=rzFGrsncaP84KO9Qk6ATl/aiS0eW2PseBL0bzL8JYutL6AnP+8d4eWDk9cKEfEPex5 5KevJ/5sRzbs0DxZZQ0qJjP41pRAjtJKf3bGzdOqMbR7C48O5/T1ZrjU+SAL4fAZ4zUj zlAXqmXTxqyPfCXu1REFlIcxDzZyHd1v9NXoiyuG2HG5Rb+6pEXwJXzH1/XplXdsZBmt tTTsqx0MALYWvhlezM81f4ja+O9voWOnlBh/j3I45c5jYsWYM6xMjPxSbq+eq4izydmK 3WA3PetyfZoAakdkkeEDECqFUVqv/itrN9Y4mFwcdVP+5al/qqgGQZsia5rRV/bChUkp 1nrg== X-Gm-Message-State: AOAM530GZyLBprRmA3Y7ogoS7TUOTJaUETMiXCQPZTFEMujNKSvoy4fT KtqtfUeMp5o6pPC2WMhgFtY= X-Google-Smtp-Source: ABdhPJxAONuByIIGIauhsjsh8+raA1mqasyYjOXylUqzsaoKTs3hTHMP9yjNuWo4rv2nPee/4+1GRg== X-Received: by 2002:adf:e485:: with SMTP id i5mr820835wrm.26.1614808090992; Wed, 03 Mar 2021 13:48:10 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , David Gibson , Greg Kurz , David Hildenbrand Subject: [PATCH v4 11/28] cpu: Move CPUClass::write_elf* to SysemuCPUOps Date: Wed, 3 Mar 2021 22:46:51 +0100 Message-Id: <20210303214708.1727801-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The write_elf*() handlers are used to dump vmcore images. This feature is only meaningful for system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 17 ----------------- include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++ hw/core/cpu.c | 16 ++++++++-------- target/arm/cpu.c | 4 ++-- target/i386/cpu.c | 8 ++++---- target/s390x/cpu.c | 2 +- target/ppc/translate_init.c.inc | 6 ++---- 7 files changed, 41 insertions(+), 36 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 781cd8fc42b..0a2c29c3735 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -112,14 +112,6 @@ struct AccelCPUClass; * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. - * @write_elf64_note: Callback for writing a CPU-specific ELF note to a - * 64-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. - * @write_elf32_note: Callback for writing a CPU-specific ELF note to a - * 32-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -163,15 +155,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 - int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index b9ffca07665..60c667801ef 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,30 @@ typedef struct SysemuCPUOps { * GUEST_PANICKED events. */ GuestPanicInformation* (*get_crash_info)(CPUState *cpu); + /** + * @write_elf32_note: Callback for writing a CPU-specific ELF note to a + * 32-bit VM coredump. + */ + int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf64_note: Callback for writing a CPU-specific ELF note to a + * 64-bit VM coredump. + */ + int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 32-bit VM coredump. + */ + int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + /** + * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 64-bit VM coredump. + */ + int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 0aebc18c41f..c74390aafbf 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_qemunote) { + if (!cc->sysemu_ops->write_elf32_qemunote) { return 0; } - return (*cc->write_elf32_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_note) { + if (!cc->sysemu_ops->write_elf32_note) { return -1; } - return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque); } =20 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, @@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_qemunote) { + if (!cc->sysemu_ops->write_elf64_qemunote) { return 0; } - return (*cc->write_elf64_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_note) { + if (!cc->sysemu_ops->write_elf64_note) { return -1; } - return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); } =20 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fa0d4bba590..0c06b9b1758 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .write_elf32_note =3D arm_cpu_write_elf32_note, + .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .vmsd =3D &vmstate_arm_cpu, }; @@ -2306,8 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->write_elf64_note =3D arm_cpu_write_elf64_note; - cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 362ad56ab68..403ed65fc61 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7389,6 +7389,10 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { .get_crash_info =3D x86_cpu_get_crash_info, + .write_elf32_note =3D x86_cpu_write_elf32_note, + .write_elf64_note =3D x86_cpu_write_elf64_note, + .write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote, + .write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote, .vmsd =3D &vmstate_x86_cpu, }; #endif @@ -7428,10 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->write_elf64_note =3D x86_cpu_write_elf64_note; - cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; - cc->write_elf32_note =3D x86_cpu_write_elf32_note; - cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index fdc169bb0ac..2b249f47eb9 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { .get_crash_info =3D s390_cpu_get_crash_info, + .write_elf64_note =3D s390_cpu_write_elf64_note, .vmsd =3D &vmstate_s390_cpu, }; #endif @@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 789124debe7..598304bd636 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,6 +10845,8 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .write_elf32_note =3D ppc32_cpu_write_elf32_note, + .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .vmsd =3D &vmstate_ppc_cpu, }; @@ -10894,10 +10896,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif -#if defined(CONFIG_SOFTMMU) - cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; - cc->write_elf32_note =3D ppc32_cpu_write_elf32_note; -#endif =20 cc->gdb_num_core_regs =3D 71; #ifndef CONFIG_USER_ONLY --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808097; cv=none; d=zohomail.com; s=zohoarc; b=OAFGfWk7DVZhs+E3/CDXlAlKEQ8WIX9AUeDiB51BymUD35UpDTpRR3QffRx2xw8N4poOTalGhQpvsuMxccMcFVVS9mf6Lpn/8u/qvQPVf+A6YJGsPbU/HaPNWc+DK2dvyeMIhX4UTN9vQhi6h83XIvFUEbkFHErs5dEkWPNYblE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808097; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id p17sm6567070wmq.47.2021.03.03.13.48.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SGgvJvthMXD03HaoXNm8wXH0XCzERc2USBOw0EtbwiA=; b=Mc4d/acAmB+6BqJYXabbkaPu4sAg7su+vbKRsuJpl28QVvFI2w48rM+a6juPZXFknq cLCJ+zVdFbjIFyr9FKEjIGqw4Gcjo0LpyJNKu55vG8glS1GrM1RGJYqZH8SlSaQUtPZV /ell4udmI49GNj3Zv9jgDa8tOH2YE6pSGRcTdiYMUABCI48c9OczNnox7cQ445VnEXxD sHkue5Xo4hVndVoUg5cPRcUmyrvm4h8ORizDW1xq4769FaAZev8Cm9XadvWNw0L8LF5o jQuJpggthS7vkv2oe82rW9E1xVajhoGoikVmbO7PcbVay14cng3zrJaS3aNqpqy+IpIH wHxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=SGgvJvthMXD03HaoXNm8wXH0XCzERc2USBOw0EtbwiA=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 0a2c29c3735..6713a615916 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -108,8 +108,6 @@ struct AccelCPUClass; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -151,7 +149,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 60c667801ef..3c3f211136d 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or + * a memory access with the specified memory transaction attribu= tes. + */ + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); /** * @get_crash_info: Callback for reporting guest crash information in * GUEST_PANICKED events. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c74390aafbf..c44229205ff 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attr= s) CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); + if (cc->sysemu_ops->asidx_from_attrs) { + ret =3D cc->sysemu_ops->asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0c06b9b1758..7edb9f581bc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, @@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; - cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 403ed65fc61..4f64f9c2d68 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, .write_elf64_note =3D x86_cpu_write_elf64_note, @@ -7429,7 +7430,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id s124sm6857300wms.40.2021.03.03.13.48.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YXKcRBx6DyaBPlolssOm9PcYgrKAw92o6BreAJ9X3O0=; b=ZD+XzyE1FKGjHE1RZf9uN0VcRExALzY3sDQI9lSnQhG5zIaIhnNV4QmNY+NIlWFNBt pEme1zXvEJ+lvLOPJezWbw/G1ycuiT4pTafWOdmFRKUFxGbS9hRGJOTck0iFAh0DqoIS ou7V1kFN9VKHDbe62MMAKF5PXq2gOc+3j8LDKYs8iGbL3PWS3K4+c4LhfQpO25TIXRJi KzXTo6LuDh9iO+JJXFWW3/l0J4S/oPVTcxvBotiN95l0eNgCBdqi0ZsCoGRyG4/dVYD1 WD7fPSldQgynqHTWmAl3/PUnjdFKG5jrrQ+GW6FeDX7xccSiaA3MAiZmlQqFYcR+4826 3FQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YXKcRBx6DyaBPlolssOm9PcYgrKAw92o6BreAJ9X3O0=; b=IxEV0TBzDmJ6wSy2FWga+ORcvZjLlr8Xxw4dPHeHUqOZOaQTVqxGTLb9ATpCYZxGLa DboSwODLYSwHKojgUqDmQUjjjiXRIAI8puoOuEdKp5zYaXxdhM5rVOzcxiI5qt4+VWg+ EnSJiOWj9nc5FVpagoHTM+JN7akQJNBauxPLjWiGx5piRGfb+p+zvIU5GzfZKmGbEMcC sohpu1wfK9O8iYUm2qxvFMiRz/ClyYR6k82IpPzKwyoSbx4JB3e6XhkbmLEdrYrg+yhH 7Ag14Ug//1WqktCMU8h5n/l9VKtoSbZwhZGP1Ui/a79ykhVbqYDIH03+Poh0QITBFJzi lvUQ== X-Gm-Message-State: AOAM5308oIdzn40YkZX8RM6XB6mzUm6nWLzND+k+jtbE9s/iFCWtpZbi n/rw5EMu1BIjcEl1Zc2GtGw= X-Google-Smtp-Source: ABdhPJz1L1VkH6/bGWBaT8vHt2Tbc2noq5Z/IbG+0eY/5NhsFBfw38eKb+cQHDD0gHtGBNFVm/5fxg== X-Received: by 2002:a1c:9a92:: with SMTP id c140mr781213wme.167.1614808102320; Wed, 03 Mar 2021 13:48:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Michael Rolnik , Sarah Harris , "Edgar E. Iglesias" , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v4 13/28] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps Date: Wed, 3 Mar 2021 22:46:53 +0100 Message-Id: <20210303214708.1727801-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 8 -------- include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++ hw/core/cpu.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 4 +--- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 25 files changed, 38 insertions(+), 35 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6713a615916..9a86c707cf7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,11 +103,6 @@ struct AccelCPUClass; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -146,9 +141,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 3c3f211136d..0c8f616a565 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,19 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * and the associated memory transaction attributes to use for t= he + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c44229205ff..6932781425a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cc->sysemu_ops->get_phys_page_attrs_debug) { + return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); + return cc->sysemu_ops->get_phys_page_debug(cpu, addr); } =20 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index de8f9c648fa..fbef4c0923f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps alpha_sysemu_ops =3D { + .get_phys_page_debug =3D alpha_cpu_get_phys_page_debug, .vmsd =3D &vmstate_alpha_cpu, }; #endif @@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7edb9f581bc..09566a535e5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, @@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 20a48bdfbab..436d001a679 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static const struct SysemuCPUOps avr_sysemu_ops =3D { + .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, .vmsd =3D &vms_avr_cpu, }; =20 @@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; - cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c05707bad2c..6c1eb8d6172 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps cris_sysemu_ops =3D { + .get_phys_page_debug =3D cris_cpu_get_phys_page_debug, .vmsd =3D &vmstate_cris_cpu, }; #endif @@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 110cc8a6d68..f0eeaea22bb 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps hppa_sysemu_ops =3D { + .get_phys_page_debug =3D hppa_cpu_get_phys_page_debug, .vmsd =3D &vmstate_hppa_cpu, }; #endif @@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4f64f9c2d68..0de4ee18bee 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, @@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 #ifndef CONFIG_USER_ONLY cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 4ff54fd9204..d31c33575f6 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps lm32_sysemu_ops =3D { + .get_phys_page_debug =3D lm32_cpu_get_phys_page_debug, .vmsd =3D &vmstate_lm32_cpu, }; #endif @@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index e7ddcf2ee28..67ea33c8200 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps m68k_sysemu_ops =3D { + .get_phys_page_debug =3D m68k_cpu_get_phys_page_debug, .vmsd =3D &vmstate_m68k_cpu, }; #endif @@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) - cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 8b86b99c15b..49d6f16ca70 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mb_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug, .vmsd =3D &vmstate_mb_cpu, }; #endif @@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ef997bcd67f..d8f2086c69e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .get_phys_page_debug =3D mips_cpu_get_phys_page_debug, .vmsd =3D &vmstate_mips_cpu, }; #endif @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 1e87f07ca73..c488bbc894a 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) } =20 static const struct SysemuCPUOps moxie_sysemu_ops =3D { + .get_phys_page_debug =3D moxie_cpu_get_phys_page_debug, .vmsd =3D &vmstate_moxie_cpu, }; =20 @@ -124,9 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D moxie_cpu_has_work; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; -#ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; -#endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->sysemu_ops =3D &moxie_sysemu_ops; cc->tcg_ops =3D &moxie_tcg_ops; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a785f3ea7b6..6fc73ed8693 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -215,6 +215,7 @@ static const VMStateDescription vmstate_nios2_cpu =3D { }; =20 static const struct SysemuCPUOps nios2_sysemu_ops =3D { + .get_phys_page_debug =3D nios2_cpu_get_phys_page_debug, .vmsd =3D &vmstate_nios2_cpu, }; #endif @@ -249,7 +250,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2149e9564fa..1b05f4e3567 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps openrisc_sysemu_ops =3D { + .get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug, .vmsd =3D &vmstate_openrisc_cpu, }; #endif @@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a6b1ff93299..14dc8583615 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -582,6 +582,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, /* For now, mark unmigratable: */ .vmsd =3D &vmstate_riscv_cpu, }; @@ -628,7 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index f293f3630d0..5f8226ed31c 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -180,6 +180,7 @@ static const VMStateDescription vmstate_rx_cpu =3D { }; =20 static const struct SysemuCPUOps rx_sysemu_ops =3D { + .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, .vmsd =3D &vmstate_rx_cpu, }; #endif @@ -218,7 +219,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) #endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; - cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 2b249f47eb9..96e8342fb96 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .get_phys_page_debug =3D s390_cpu_get_phys_page_debug, .get_crash_info =3D s390_cpu_get_crash_info, .write_elf64_note =3D s390_cpu_write_elf64_note, .vmsd =3D &vmstate_s390_cpu, @@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8c1d0ba53b1..2f7b43a0353 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { }; =20 static const struct SysemuCPUOps sh4_sysemu_ops =3D { + .get_phys_page_debug =3D superh_cpu_get_phys_page_debug, .vmsd =3D &vmstate_sh_cpu, }; #endif @@ -262,7 +263,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sh4_sysemu_ops; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index f5862e74baf..b13d586f79d 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .get_phys_page_debug =3D sparc_cpu_get_phys_page_debug, .vmsd =3D &vmstate_sparc_cpu, }; #endif @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 9374f8440a0..b1776c10205 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -149,6 +149,7 @@ static const VMStateDescription vmstate_tricore_cpu =3D= { }; =20 static const struct SysemuCPUOps tricore_sysemu_ops =3D { + .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, .vmsd =3D &vmstate_tricore_cpu, }; =20 @@ -180,7 +181,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 345b6e9e417..1b2bb25f508 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { }; =20 static const struct SysemuCPUOps uc32_sysemu_ops =3D { + .get_phys_page_debug =3D uc32_cpu_get_phys_page_debug, .vmsd =3D &vmstate_uc32_cpu, }; =20 @@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D uc32_cpu_has_work; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index fd65246015f..8b1d827e747 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { }; =20 static const struct SysemuCPUOps xtensa_sysemu_ops =3D { + .get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug, .vmsd =3D &vmstate_xtensa_cpu, }; #endif @@ -222,7 +223,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &xtensa_sysemu_ops; - cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; cc->tcg_ops =3D &xtensa_tcg_ops; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 598304bd636..cd22a1ce3f0 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .get_phys_page_debug =3D ppc_cpu_get_phys_page_debug, .write_elf32_note =3D ppc32_cpu_write_elf32_note, .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, @@ -10893,7 +10894,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif =20 --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) client-ip=209.85.128.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808110; cv=none; d=zohomail.com; s=zohoarc; b=mZeRA4F0i60b1k4Rd2Z1trm0X+BjyxbBYR9NRe7Jl37NFLKyVb21rZafpWFJufDJjlVxFh5jsIfbHTfdUJUZZnJ0lVSAoNTMlizvuLl68PEC+K08Su/GDj49R+5JLWjK/e/VuawvGAVorRitii6W2BsRsVe3r2V4Kp6V3WjwBjM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id f16sm32652298wrt.21.2021.03.03.13.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+jPLhsEGuSQelHyPz9BxX5tZZqthgY1a40XW4S6Sd60=; b=WNdrj8dPWwqyXW7+gX3jJsKJVD1MqaTQpRYiqerhSlaYz6eqqr1PX9tsS1AVmWNsqZ YWgHUGaFCcna3vaAqyBBak7ItwX4ilmU1ns3TUvkOP+QJAE16y7b6q7F//LRZM9caE6n 3RoDZ1xhbj07vTJrlsc7gUz9REp83X1jyqxUjIWE+ONwUpOpLch9AyGe14ifqtvnPS4k VwTcTXogrH3i/bwg6xDVlOscZZGrE3ItATot/kNB0bUbHlkVhjv2avWBh5dUquBx2uPB z5Z+llvdByrPZnVSA5ZhXWG5bFEDh1d4DWws7lTsKzNhne/VQIQhlpYhhsuZw1bgn30x Jr+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+jPLhsEGuSQelHyPz9BxX5tZZqthgY1a40XW4S6Sd60=; b=FJMg+1i3u+FNC57DQZ8W9igoufkrajw1ltz5y7Gzr1G4znA4X5I0qoP1EuPB+95XJW L48pN7df68vmm+pXvvzN7ojU2SmhqRKeQwYT4GTid5P/EsKcnfn5gHHN4BGUvVV7V+wK qQLpnToImao6WO0bmtmRt0ZFrl8UD8DOcEBziY3fZikNxR7S7IqhwGIPJBjqQBYotWcg nvERuXnmklCzXkGBlBnf36gPwqe98FoBNaEvBZEXKUdMeHkiuUJkzlQMQXt7zKlEIEmb BsVaJNxUj19Wsh6hccArZtJ4pqOY4BAQJnskA4ybrgVPgbbwWPJ5hKpJhtEge51S/HrD Sicg== X-Gm-Message-State: AOAM532LE+YD+IR93IiVoN3oYQMafmtifGPnQEvh13x23FVtDqfeSrdJ JVP4cXEvo3TVjLSCyHQsCZwDYFgj83Q= X-Google-Smtp-Source: ABdhPJzeqoIqC66Phs7TVVWlM+zEFWq9N5xg0qAHePbZ55pTvYFsMxVVPuL5zj5CVmEZa8IHflmKnQ== X-Received: by 2002:a1c:f60b:: with SMTP id w11mr882481wmc.134.1614808107729; Wed, 03 Mar 2021 13:48:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 14/28] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps Date: Wed, 3 Mar 2021 22:46:54 +0100 Message-Id: <20210303214708.1727801-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 9a86c707cf7..8af78cdde23 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -94,7 +94,6 @@ struct AccelCPUClass; * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled. - * @get_memory_mapping: Callback for obtaining the memory mappings. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -138,8 +137,6 @@ struct CPUClass { void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); - void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, - Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 0c8f616a565..460e7d63b0c 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_memory_mapping: Callback for obtaining the memory mappings. + */ + void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, + Error **errp); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 6932781425a..339bdfadd7a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingL= ist *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_memory_mapping) { - cc->get_memory_mapping(cpu, list, errp); + if (cc->sysemu_ops->get_memory_mapping) { + cc->sysemu_ops->get_memory_mapping(cpu, list, errp); return; } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0de4ee18bee..b2d3debd1f2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_memory_mapping =3D x86_cpu_get_memory_mapping, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808114; cv=none; d=zohomail.com; s=zohoarc; b=ACmDw2vYdCElJoq0b4DMdk+xwvkYMDEKdCEOS77V/QfOzsVUAzLbU4AuDEf9n51Pdc3xgxN9tgu7XbgsOImJBRM+ke6Uj/9yYU6WsQBVqST2Togsy+sHeu5fj6Cbzi5T7OSGaTuO2ihMewinGg/p+KJaSfa8ZwvXu6o2Qv6S5jI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808114; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EgbaLT145JE9K24YqnNM6CBW+74A5NiqHCMjzrliWjU=; b=SQQbzJ8jwxpc8YxPVuqaZnWxuDHQy3tv1bIPxVYLBme4kq0xpCAL5WIa/wdedFrtdHr62+i1qKAoc/r84/oUn75gjbyAeuN5ptsenaLSEwlQQD25sV4s29DxZtVeehvdXNZa+XyuUGzbevBNj3WGAcJ/ZV8Y7KJmY0tgejKL3A4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1614808114806876.730416999004; Wed, 3 Mar 2021 13:48:34 -0800 (PST) Received: by mail-wr1-f51.google.com with SMTP id a18so17162250wrc.13 for ; Wed, 03 Mar 2021 13:48:34 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id g1sm6924468wmh.9.2021.03.03.13.48.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EgbaLT145JE9K24YqnNM6CBW+74A5NiqHCMjzrliWjU=; b=khFf7D1kn1I8+VV7UwMj4AoxYALmg6FuAUX0DZ7Zk0Phjg623DyddsNHR60s5WzLo9 k4juJhLrUafayhaebqLgOJlZ23QMmAZTIxksL9vlHpK+2ewfsEFVNU4DJ8+edDfQIOd/ DigRaq5gqUjzRQ+ZDGUdk3yBn7L06hCul1H9NDWSFcH264CsAZeSAQEmTda1jOsi3aLT De7Rj8+80KgtFeYK/v/o6AaB3VjDS02KY03vMUz1OIII6ViwbTqBTQKUlUO0gWbMFKz+ Fp8BZRyPzYlYvKHupe7pvAVDDICSY5P7wOzaPn80+L5h1sSfyoYQfIpt9E4hK+3c08X6 PDHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EgbaLT145JE9K24YqnNM6CBW+74A5NiqHCMjzrliWjU=; b=oL3avybtwViDhbtEb5fVGTaacPbBfIL4sKoAolDRGn31LcfMFQp8f2euo5adEYquAj jVuBg2ZLyOQeRRbwjMvXhm0bb9XPfufFmd25/GSgwYKCPi+9Hu5aFha+jqoshramqfSY XF9RSye5ErI2Y8gv7cEXuTfTa3FT8iSCGQLA5FhBNozz/7+PSe0nNV54DLmMXOJS7b97 hpz6DXkfacNiM+XzSSRp1hgM01ot3tM23PgFQk29COHwXetB7z7S18zqXXTVbOijj5if ec6TddBsHwGMxiny/ivULzkzytbt3guF4R0qzS/gf/dYKoT7G8kctCgVcklWi0oCmcCp BUlg== X-Gm-Message-State: AOAM533cJjKmQnZBDA1FKL+4XS6vSWa+7rtHl1fQCnHvtW4OGY98Z0NH FAvVHzimlj0MJLLdsvgGgGI= X-Google-Smtp-Source: ABdhPJzg229G09tZapjldlWd9H3NvLGpGzpJKR7kk7D9KbG56lVNaudV26dJHAEeGCzH3AIMxkWkUw== X-Received: by 2002:adf:b355:: with SMTP id k21mr794588wrd.156.1614808113118; Wed, 03 Mar 2021 13:48:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 15/28] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps Date: Wed, 3 Mar 2021 22:46:55 +0100 Message-Id: <20210303214708.1727801-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 2 -- include/hw/core/sysemu-cpu-ops.h | 4 ++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 4 +++- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8af78cdde23..960846d2b64 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -93,7 +93,6 @@ struct AccelCPUClass; * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. - * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -136,7 +135,6 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); - bool (*get_paging_enabled)(const CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 460e7d63b0c..3f9a5199dd1 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,10 @@ typedef struct SysemuCPUOps { */ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); + /** + * @get_paging_enabled: Callback for inquiring whether paging is enabl= ed. + */ + bool (*get_paging_enabled)(const CPUState *cpu); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 339bdfadd7a..7a8487d468f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_paging_enabled) { - return cc->get_paging_enabled(cpu); + if (cc->sysemu_ops->get_paging_enabled) { + return cc->sysemu_ops->get_paging_enabled(cpu); } =20 return false; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b2d3debd1f2..994d58aa754 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7157,12 +7157,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs) return cpu->apic_id; } =20 +#if !defined(CONFIG_USER_ONLY) static bool x86_cpu_get_paging_enabled(const CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 return cpu->env.cr[0] & CR0_PG_MASK; } +#endif /* !CONFIG_USER_ONLY */ =20 static void x86_cpu_set_pc(CPUState *cs, vaddr value) { @@ -7389,6 +7391,7 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { .get_memory_mapping =3D x86_cpu_get_memory_mapping, + .get_paging_enabled =3D x86_cpu_get_paging_enabled, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -7429,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; - cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808121; cv=none; d=zohomail.com; s=zohoarc; b=hCRN1FzpT8H0VSP7jljT7hVfRLbllRelNRTSF0c2fqJTW/grejHv3t1URLDyRt9kQHsT+8YK/cblV9wvFTJFnBEMy+Nm5qBmgb3t81cXw78GslaHkZZShJ1lXjZbzTvdjfAINuCehYzbzFN3/YB8ll8EHh3lABcypmGcQHdCEQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808121; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aEJL6g+NIWgG6nrnpPTxwq6YXIgTFSiy1D/Ixw2Gpp0=; b=IBjvzgJ/x2Q0R2gGbkdmwZ0pIyMY7/C0jx1BdlmP18pGKYykaKay1GK0UZCS4/mCkSnHBZHdMzllPZnx/PD4Yz9zqk9S3gPxSqGZ0eJVenjgwQb6oCjSvYUCkOtQ372VVDxLeYFnbzqsVzgVRG2iDnT0Vxt0SGgiWK0P3+SpHiU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.zohomail.com with SMTPS id 1614808121479131.4281686405659; Wed, 3 Mar 2021 13:48:41 -0800 (PST) Received: by mail-wr1-f47.google.com with SMTP id j2so12516470wrx.9 for ; Wed, 03 Mar 2021 13:48:40 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 18sm6721360wmj.21.2021.03.03.13.48.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aEJL6g+NIWgG6nrnpPTxwq6YXIgTFSiy1D/Ixw2Gpp0=; b=VtVa1soKCzbURK8nE5oQZKPFDK+8E3SfmmPY58ibezRQVl1D55GwJckHQZTet2K+OK XiFcdPJud9Or1oCbJz+q7QiliU7g0LozA4VDrfVaycagTbY5uVgLkT3PyPF0262JMnh1 /o0N0JJlj8Ay/j8pRrL933RfiX0k91jY1wDKUzQNUBIObe5yJfB3sRboQx/USByrRNFB 982/qxIucm0hHqvaLwQPcRis+AgtDeq3N7v227IPJjXR/kJ6hdzZkOCRydu31PUidBSE ewPHdbxGKb/pUt3uSKrJnV4s9KoBNSmVC+FEp6IctFWy4dQj5XUmAxan8RCVR2CEnBAe g+bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=aEJL6g+NIWgG6nrnpPTxwq6YXIgTFSiy1D/Ixw2Gpp0=; b=YijXsKEwYUp3vwCRNMg2cUTsrPJhkhPCflx5J/8a+0OA4m+yDpWdhXJfjy+kk/dddY Tl9SYk+97nVnmxiQIvkkFwYsNI6GEISo6xOzjZYcfN1cvXbr3BuINOjv+H+Z1F0CeepJ gaN9Rn9FsRiGWuXOFZsDD0iig7UeQkZVGu1t3DS17eqheXl/G9hQlaHlXNBnw+ZjP+kX v0ltsyEi1iMCls9nmeVBxSaJj045bqiNZyW8QP245Y/Y9fxflXXWkhZkhuSAv75wyLNP apLyTw/CkLbGYSnHeapwq91T/tx8oSkabhJCzFDg53CZLwuolf3rjXjM2emQl6aptJct sJ0Q== X-Gm-Message-State: AOAM533a/LGhKW7axhwEe1d9DguNYCz209bJpQeyWGSwq595qjlyQXE2 djJXQr/2r0gcFgm81FQxT/Q= X-Google-Smtp-Source: ABdhPJwsgWrcAs3BNinoRi/a2rFUVJ5363ya/G70w8elT2tkZJJkg/cnXwS/3HmJ/X7i1Da+5A7/cQ== X-Received: by 2002:adf:b1c9:: with SMTP id r9mr703839wra.51.1614808119701; Wed, 03 Mar 2021 13:48:39 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Michael Rolnik , Sarah Harris , "Edgar E. Iglesias" , Taylor Simpson , Michael Walle , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Yoshinori Sato , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Guan Xuetao , Max Filippov , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v4 16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c Date: Wed, 3 Mar 2021 22:46:56 +0100 Message-Id: <20210303214708.1727801-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"): We cannot in principle make the SysEmu Operations field definitions conditional on CONFIG_SOFTMMU in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the SysEmu fields to system emulation builds, is to move all sysemu operations into a separate header file, which is only included by system-specific code. This leaves just a NULL pointer in the cpu.h for the user-mode builds. Inspired-by: Claudio Fontana Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Taylor Simpson --- include/hw/core/cpu.h | 3 ++- target/alpha/cpu.h | 3 +++ target/arm/cpu.h | 3 +++ target/avr/cpu.h | 1 + target/cris/cpu.h | 3 +++ target/hexagon/cpu.h | 3 +++ target/hppa/cpu.h | 3 +++ target/i386/cpu.h | 3 +++ target/lm32/cpu.h | 3 +++ target/m68k/cpu.h | 3 +++ target/microblaze/cpu.h | 1 + target/mips/cpu.h | 3 +++ target/moxie/cpu.h | 3 +++ target/nios2/cpu.h | 1 + target/openrisc/cpu.h | 3 +++ target/ppc/cpu.h | 3 +++ target/riscv/cpu.h | 3 +++ target/rx/cpu.h | 1 + target/s390x/cpu.h | 3 +++ target/sh4/cpu.h | 3 +++ target/sparc/cpu.h | 3 +++ target/tilegx/cpu.h | 3 +++ target/tricore/cpu.h | 3 +++ target/unicore32/cpu.h | 3 +++ target/xtensa/cpu.h | 3 +++ cpu.c | 1 + hw/core/cpu.c | 1 + 27 files changed, 68 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 960846d2b64..fe4206b540f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,7 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 -#include "hw/core/sysemu-cpu-ops.h" +/* see sysemu-cpu-ops.h */ +struct SysemuCPUOps; =20 /** * CPUClass: diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 82df108967b..f1218a27706 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index efa1618c4d5..265d00d55dd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -25,6 +25,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d148e8c75a4..e0419649fa7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "hw/core/sysemu-cpu-ops.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d3b64929096..4450f2268ea 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -23,6 +23,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define EXCP_NMI 1 #define EXCP_GURU 2 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index e04eac591c8..2a878e77f08 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState; #include "qemu-common.h" #include "exec/cpu-defs.h" #include "hex_regs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 61178fa6a2a..94d2d4701c4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -23,6 +23,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "exec/memory.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b4b136cd0d1..06965f11100 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -25,6 +25,9 @@ #include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* The x86 has a strong memory model with some store-after-load re-orderin= g */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h index ea7c01ca8b0..034183dad30 100644 --- a/target/lm32/cpu.h +++ b/target/lm32/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 typedef struct CPULM32State CPULM32State; =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7c3feeaf8a6..4b0a19bdf44 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -23,6 +23,9 @@ =20 #include "exec/cpu-defs.h" #include "cpu-qom.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define OS_BYTE 0 #define OS_WORD 1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a7551..3f5c2e048e5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -26,6 +26,7 @@ =20 typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) +#include "hw/core/sysemu-cpu-ops.h" #include "mmu.h" #endif =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 075c24abdad..923ab71f8d7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -6,6 +6,9 @@ #include "fpu/softfloat-types.h" #include "hw/clock.h" #include "mips-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h index bd6ab66084d..7a0a5e95d01 100644 --- a/target/moxie/cpu.h +++ b/target/moxie/cpu.h @@ -22,6 +22,9 @@ =20 #include "exec/cpu-defs.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define MOXIE_EX_DIV0 0 #define MOXIE_EX_BAD 1 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc713..1b88b027063 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -27,6 +27,7 @@ =20 typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) +#include "hw/core/sysemu-cpu-ops.h" #include "mmu.h" #endif =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82cbaeb4f84..2a6f9f48547 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -23,6 +23,9 @@ #include "exec/cpu-defs.h" #include "hw/core/cpu.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e73416da68d..f889c28e548 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -24,6 +24,9 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO 0 =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 02758ae0eb4..254eefaf824 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -25,6 +25,9 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO 0 =20 diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0b4b998c7be..d9b7b63716a 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -25,6 +25,7 @@ #include "cpu-qom.h" =20 #include "exec/cpu-defs.h" +#include "hw/core/sysemu-cpu-ops.h" =20 /* PSW define */ REG32(PSW, 0) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 60d434d5edd..2ca6a4f559f 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,6 +28,9 @@ #include "cpu-qom.h" #include "cpu_models.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define ELF_MACHINE_UNAME "S390X" =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 714e3b56413..07ed2f3e206 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* CPU Subtypes */ #define SH_CPU_SH7750 (1 << 0) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 4b2290650be..237ffc4fe66 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,6 +4,9 @@ #include "qemu/bswap.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 7d8e44d12e4..54bdbf0ca1e 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -22,6 +22,9 @@ =20 #include "exec/cpu-defs.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* TILE-Gx common register alias */ #define TILEGX_R_RE 0 /* 0 register, for function/syscall return val= ue */ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index b82349d1b10..cb0b989953e 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -23,6 +23,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "tricore-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 struct tricore_boot_info; =20 diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h index 7a32e086ed3..de475d0fc2e 100644 --- a/target/unicore32/cpu.h +++ b/target/unicore32/cpu.h @@ -14,6 +14,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 typedef struct CPUUniCore32State { /* Regs for current mode. */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 3bd4f691c1a..ea4ee5338f3 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -31,6 +31,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "xtensa-isa.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/cpu.c b/cpu.c index 64e17537e21..29dafee581f 100644 --- a/cpu.c +++ b/cpu.c @@ -29,6 +29,7 @@ #ifdef CONFIG_USER_ONLY #include "qemu.h" #else +#include "hw/core/sysemu-cpu-ops.h" #include "exec/address-spaces.h" #endif #include "sysemu/tcg.h" diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 7a8487d468f..da7543be514 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -35,6 +35,7 @@ #include "trace/trace-root.h" #include "qemu/plugin.h" #include "sysemu/hw_accel.h" +#include "hw/core/sysemu-cpu-ops.h" =20 CPUState *cpu_by_arch_id(int64_t id) { --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id s3sm14468228wrt.93.2021.03.03.13.48.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UwRUo7hC4h9vgJMC9crYDnluKvk2tzZcvKCkSEg/uSc=; b=VGl8wx3paFjSVhst0xwZVNTJfVvVPedOVkbRO5IhEaTM4nkJ/u9cZtz2AN+I70neKU lVME3Kx+VPZ9mGv50Y+tBC4C5r4qNzzhoaQFGcodwEeAldpOMcMbfrP5gUyJu4h9u6aN xicgkHdiuYUG6j3WSFVJtK+N+xCh20qXDBLgTlznxNLwp60/InFosxGANfxgjR6pzOdF Gl4lwdzUO9LhZ2w9HjlXhA4vSGyxRmaA8QGgL9Ir/qNWTlLSFo9NJWLWol/XdORkK22a 3oy8CU9AXspmg3aHVsQuriCMzeWA4ha9tKBEqTdB+ZxlH2qPdm9Kk3IlaMjbvjrdLg73 ZKZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UwRUo7hC4h9vgJMC9crYDnluKvk2tzZcvKCkSEg/uSc=; b=qsAjr0hoRSV8jo4vzQaPlRNflO+d9NDDvJ9lqrck4HJSy4Y9eDrJ7FAx55r6P/+oiG PWsb2G9wSlNJQ0PMsB40xLSp4O+2xkR5xGyTWDQbzaZP2vWl9e1DxdTkZEZJuW+lRKOh om8XX/9QHdDJE5y6K/HML1MU5SHq8kbasy8lL6JIDQGhFm2Da0FGdxzhl4bqgeM0XDYO GUFOkRPY0k9YpxV5Mwr/k1ESxCcOeX5DcEhQD/0IavXrc2gcoolTwyNd1gG657hcWNz4 xwGFzDd+YrWS4N6qIIxLbmIjz6UgbeJAtABUbRP82fP1WdAh+MFOKXBQSCzqgTEJQHic ZSLA== X-Gm-Message-State: AOAM530qc1pvDWxM1VDc01G6NtSQlgXdaCuXEURql2ckMZpAIMCVuoRf F8TIO5hoqi7/5GFtvUFV+PU= X-Google-Smtp-Source: ABdhPJxlz6DIchAGvKj7W4FAU5GQPu71/RTvZT2TVu4N9FvUNDg2Ns2Csov7QXRiPjgQP7q5Xx0Sjg== X-Received: by 2002:adf:ce0a:: with SMTP id p10mr671741wrn.255.1614808124862; Wed, 03 Mar 2021 13:48:44 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 17/28] linux-user: Remove dead code Date: Wed, 3 Mar 2021 22:46:57 +0100 Message-Id: <20210303214708.1727801-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We can not use watchpoints in user-mode emulation because we need the softmmu slow path to detect accesses to watchpointed memory. This code is expanded as empty stub in "hw/core/cpu.h" anyway, so we can drop it. Reviewed-by: Laurent Vivier Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/main.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 81f48ff54ed..d7af3ffbc22 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -200,7 +200,6 @@ CPUArchState *cpu_copy(CPUArchState *env) CPUState *new_cpu =3D cpu_create(cpu_type); CPUArchState *new_env =3D new_cpu->env_ptr; CPUBreakpoint *bp; - CPUWatchpoint *wp; =20 /* Reset non arch specific state */ cpu_reset(new_cpu); @@ -211,13 +210,9 @@ CPUArchState *cpu_copy(CPUArchState *env) Note: Once we support ptrace with hw-debug register access, make su= re BP_CPU break/watchpoints are handled correctly on clone. */ QTAILQ_INIT(&new_cpu->breakpoints); - QTAILQ_INIT(&new_cpu->watchpoints); QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); } - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL= ); - } =20 return new_env; } --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614808131; cv=none; d=zohomail.com; s=zohoarc; b=S5/jc1Kl863hY9orvwy+6IKLA/bpcmAoWvZCU+RSkvclh7x4t+UMtXfj6XuDctPmGQ8CoeHOAKuxyHf5GgZ6pesv2RgTdwFX4+1vc8CJouYBnf2/6VL8S6+VQhPwLFIeXpZdUXL0lUCgwxKSRS7UCYgYu1Y55VS8g0pR7o0iRrU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808131; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kUl/TkScTas4U6LyrmMWcrV1B+r956Btg0Xp2UUszDg=; b=dy+bJepB4YbNCPdAJ2CjcBkaBKG5kNkIfaAuy2NosrMCuDCpb2yznSpcQCkRvP6Cfm6VkyGtpYEEo3vq42vBPqb7jXc3aZCtSg2D3Cupr2+JFbVqCECsPc5mRVpxm7DMFkNXqbYtYstAAvYcJVeXPyExFaTtOdFTw72a/jMD2BM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1614808131796377.2936378072492; Wed, 3 Mar 2021 13:48:51 -0800 (PST) Received: by mail-wr1-f51.google.com with SMTP id f12so21566661wrx.8 for ; Wed, 03 Mar 2021 13:48:51 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id g63sm7463370wma.40.2021.03.03.13.48.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kUl/TkScTas4U6LyrmMWcrV1B+r956Btg0Xp2UUszDg=; b=qInQaYFsgsE69kLZN8Q0oTBi4JLGigTuAdCDOGlOkRUemirQGKUfhX9Pj8PC4uUvOY t88ghIacqaz2h0fwh9VbeOOOA44AWZ8O1H6BxbhYX/Qocj/GqBvR0tugFD/qlPvaCtYs s3bJFoCvS4S+9FvE9WV+PBiKVXDaEfbOFTbiDKnr8d2KZEJ8ZFoN7rKEXDRWVlm1COeO I4K7tzXcd9paZ0L5tbFEnJ1QUlimRuBh2lQgGI//cMLR469o/3detg+i+YJPevuQA7rp 4tj5UIKf38In16T2tGimCGGv5kdFEbIYLnGRnSaedNXc9dEifVo3xXRJ5ilbMN4+XSU7 whOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kUl/TkScTas4U6LyrmMWcrV1B+r956Btg0Xp2UUszDg=; b=mJWn0RRcmnUeZ2M8wEIsDCMZpGLE0tC0H9KVeVImDWiX4Wokv1Jk6LShiHpGl70wCI BXlN1xQEwEsrIh3+zPoWbb3bnZ8RkrxPOWElmYHI/tIsGUhLM2gNtXtAYqR/2CJvKQRA 5nqPapmJZEHGhNqQLpoDDG7kM8Byz8aM5bP2Lkv/bjGkR+DXfZcXs8tCzVSUHiVzmKpu DUqGIDhXCrRPBGam4X+2QOH5Z/HwqO+VSdzQ6Lbjsp2KdUhG208+SEiJkkIiZ1D2cKEA v2sfcuJMD29NF88LoQQ/gvgf+WHOfTwFUWOWRqRsxFIvkyc0XKqYr+BSeoG2FmxTfong gmpA== X-Gm-Message-State: AOAM530UmmeqvwRE/i4iGIbCFX4pMOFRdZAJhyagJ81HLVnE+XCqM5je JR46obyQlaY9RhAN8RkVTcM= X-Google-Smtp-Source: ABdhPJyY4HgQ86PsHHmKaXEniS0UUWIyAYBaegUuvR3TasK7FrH16cvXpoFJEK/WJ9eL6FDQt/11LQ== X-Received: by 2002:a5d:698e:: with SMTP id g14mr666134wru.127.1614808130141; Wed, 03 Mar 2021 13:48:50 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 18/28] gdbstub: Remove watchpoint dead code in gdbserver_fork() Date: Wed, 3 Mar 2021 22:46:58 +0100 Message-Id: <20210303214708.1727801-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) gdbserver_fork() is only used in user emulation where we can not use watchpoints because we need the softmmu slow path to detect accesses to watchpointed memory. This code doesn't do anything as declared as stubs in "hw/core/cpu.h". Drop it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- gdbstub.c | 1 - 1 file changed, 1 deletion(-) diff --git a/gdbstub.c b/gdbstub.c index 3ee40479b69..f3614ebcc7a 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -3349,7 +3349,6 @@ void gdbserver_fork(CPUState *cpu) close(gdbserver_state.fd); gdbserver_state.fd =3D -1; cpu_breakpoint_remove_all(cpu, BP_GDB); - cpu_watchpoint_remove_all(cpu, BP_GDB); } #else static int gdb_chr_can_receive(void *opaque) --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808136; cv=none; d=zohomail.com; s=zohoarc; b=mTnZXdabwclTgGjXbYZa1RORzYeCR+JVNArB7KatMMaiE/WQbkwKLD3H7G1qDhaFDDO6B6ieVoUNAiaLOiYieiwS76R1mUPF+scXeKXaeB1omvi3cMgin55dmcagqmd/QxCeNRRM34BZqTJ6b9DqOsxD4glxUV1qkqfeP//PHEg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808136; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YsyyPNDoTwAkeJjoy+M+xRx5h1vPHUVYHrANL4+RWD0=; b=LwpvS/hRZppaNLRiW5I5OmpgGFU3rzawUmoZ41RA+N8AyvC+qv+k4J/z3tDafDt0Ak7OnNuoWj0o+JNuUL+eDdIWa8Fy/3ldkToatEelz88TcqyOl6T2KPXjGCq5nV4hAEQGKbCQBTtJw1oNiDCTNu0jOT0TEcv7m0cJHqUD9Cg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1614808136927230.68031450595618; Wed, 3 Mar 2021 13:48:56 -0800 (PST) Received: by mail-wm1-f54.google.com with SMTP id o16so7678321wmh.0 for ; Wed, 03 Mar 2021 13:48:56 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id z13sm33854690wrh.65.2021.03.03.13.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YsyyPNDoTwAkeJjoy+M+xRx5h1vPHUVYHrANL4+RWD0=; b=V/SuZJ8SpGBxAstY6hDc0Qslhzv+bxiUGIKZv11yfSVv7Oxd7fKaGon1PaSAP2m3cl 5IIZaFPA/PVQXdFegc9eeUxYDN3lmW/xaGkEK0XXE7dKas2ciX2wixCe4HtcyPuD+mp8 nCiX14pCTeT/e8JakRCTYzembpCE31pZZwbB4kluwZfCdbYhw51dKrY48iV3pp9v1ZFC /fe8ThcxwPjexlTiPuuRltaw9TAQ4v7ft7Df1777KNAaM8BOXgLWCrRer+SPoqexmpJu L8MBJnoT9Q+6C1o7pXYwGGWjtzl+miEnSnLz5ois7+0QKF75aMlomznLo5pC3b61AnvJ NJfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YsyyPNDoTwAkeJjoy+M+xRx5h1vPHUVYHrANL4+RWD0=; b=jcki2Y0bEnpUv8WCglcTAQsrMNvxt2NGDm8yhM8yNo5fC0bgoDu6JsZ9MNZezP3Lsy FGGhOp6ZKhWjyaL8ZW9pwkEV/nrCanttCwDTIHLzOWqHiox9MOcCHvj49kPWA7Ow7YNg hzzshWmBXOK8ydraMX16XbAOjSXsHSUek9zXu4jigGrQFlb3CgruMmKchcShxzTMXmL4 9zyPP0f30vTAOO+syx/gnLyYQuq85jNW+DxCFvnT5+8AM6Y6e2oR3PbFyLw4/Oks6rSE A3bGl6dUSvsZAXR9J9X8Uo87p2eaLBUxpYnJRRp72AgXAHHZpZAUqi/hjsudh26cBgB6 8Cig== X-Gm-Message-State: AOAM531tVYu5HO1u8WNDpzwWVwnDJ1uDEtLPA7T0a1xw1uljGQcV200+ b7h5eijZHveChcPTY6307tU= X-Google-Smtp-Source: ABdhPJxZiYOlxTknALOe29KozWDyUp8ZjfKR71R0FW3hcWVdTXcU0Psr2cH26dTTPkD9n+nyIs/Kig== X-Received: by 2002:a05:600c:203:: with SMTP id 3mr852297wmi.88.1614808135219; Wed, 03 Mar 2021 13:48:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 19/28] target/arm/internals: Fix code style for checkpatch.pl Date: Wed, 3 Mar 2021 22:46:59 +0100 Message-Id: <20210303214708.1727801-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/internals.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 05cebc8597c..d6ace004855 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -251,7 +251,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) return pamax_map[parange]; } =20 -/* Return true if extended addresses are enabled. +/* + * Return true if extended addresses are enabled. * This is always the case if our translation regime is 64 bit, * but depends on TTBCR.EAE for 32 bit. */ @@ -262,20 +263,24 @@ static inline bool extended_addresses_enabled(CPUARMS= tate *env) (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EA= E)); } =20 -/* Update a QEMU watchpoint based on the information the guest has set in = the +/* + * Update a QEMU watchpoint based on the information the guest has set in = the * DBGWCR_EL1 and DBGWVR_EL1 registers. */ void hw_watchpoint_update(ARMCPU *cpu, int n); -/* Update the QEMU watchpoints for every guest watchpoint. This does a +/* + * Update the QEMU watchpoints for every guest watchpoint. This does a * complete delete-and-reinstate of the QEMU watchpoint list and so is * suitable for use after migration or on reset. */ void hw_watchpoint_update_all(ARMCPU *cpu); -/* Update a QEMU breakpoint based on the information the guest has set in = the +/* + * Update a QEMU breakpoint based on the information the guest has set in = the * DBGBCR_EL1 and DBGBVR_EL1 registers. */ void hw_breakpoint_update(ARMCPU *cpu, int n); -/* Update the QEMU breakpoints for every guest breakpoint. This does a +/* + * Update the QEMU breakpoints for every guest breakpoint. This does a * complete delete-and-reinstate of the QEMU breakpoint list and so is * suitable for use after migration or on reset. */ @@ -284,7 +289,8 @@ void hw_breakpoint_update_all(ARMCPU *cpu); /* Callback function for checking if a watchpoint should trigger. */ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 -/* Adjust addresses (in BE32 mode) before testing against watchpoint +/* + * Adjust addresses (in BE32 mode) before testing against watchpoint * addresses. */ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614808142; cv=none; d=zohomail.com; s=zohoarc; b=RQLRzjRy42Cg/SGG/c6A9TylCwp9Ve2JuWxdVtgIprOdkhm1lqWUn+6dquCEg5QvJqm9AiLGfQgCHu7EDavboLT9DgqNwdK21yLLA/644JMZK7gJyjyzyPD4biIOpdJpr3l5mh62h3oye7ZKMH2RP9cqvNpajhkhZaA4e0rAhik= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808142; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3OqS7UcP206wRkOojyBF7HLEMqlrEg0K8qjlNSdHuN0=; b=OaPLzoPBY2KPyBfqWrJAYRsoo6m9dmBtJ4EBhEkFqiwP9vEIKAv9gaCFlB24ZMbKDm6f85hKvV2Xjs3wWDnLQR4Gz4Tal3gnCZOgpsbQT2+KigsbXsJ9KYag4PlySTbgky8nOk8YFQ4nopTZuOkU1tgNFAyLCKyfIY3Co999RF8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.zohomail.com with SMTPS id 1614808142194743.385122374499; Wed, 3 Mar 2021 13:49:02 -0800 (PST) Received: by mail-wr1-f43.google.com with SMTP id j2so12517370wrx.9 for ; Wed, 03 Mar 2021 13:49:01 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id l8sm18988768wrx.83.2021.03.03.13.48.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:48:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3OqS7UcP206wRkOojyBF7HLEMqlrEg0K8qjlNSdHuN0=; b=hU7xL3jg+s6l7qGQ1ugo7clEuznfIYKCNPA6so5H4ANvAZEdef67E+IBrjWvumF8mr dRaunXw3yBmkFeXwznR6lnXEqeWW10oOtoH2DPV195giWlfdKoyRDNfM6yqFRly64ifM fvCYb8C6uHL0CBnsCOwK/+tfU4AJjzk3WEauKBuyGtHsNy4P1aaKon77h8q2qbBl2skk hixzKIqFxRydwPqWGXpdLc+/74/J0ToRIPbXRP7V3aiG7gOHgluV4PWATbJNzuIh9931 /v6xe4YWJopUeMrC6S63Dqz9EjeQoz5nbfVE61Ytobk18UpAmG6Ce9X4PaZBonK2zCNP q7Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3OqS7UcP206wRkOojyBF7HLEMqlrEg0K8qjlNSdHuN0=; b=pQQ66T47my5NjMueeC1NwBG0VBqNnqY2hKAVM0H5qZGmwZL4+sHDHIrRGrrbPn7XyV HVLLUUrsie7xaxefyGT9ARVLM/0zNsk1FhSIvQQD8S2MIwLIFYO9fxPuNkYmy3Rs8aWz l1CqcQ51GUbv1Vf72FIT62THVDlf19hKK56/p2wHr20YpoopZXkhdDwoIwvLU7MxObaP XxONQahcsSDU1RbOCMhLZG9QNZ8CSayh7TEUzQKRbWXlFaKXUsjeNckXzCsK6KAKkq1+ a7GCceXsVK445WtW1vljsKVytRtT70L0SGQgYfZid60052LHSXN3UOVmVklTz9kVyElK v/cQ== X-Gm-Message-State: AOAM530N+ZCY7jAqgTvbpFahy0HwY3lDp52YtIDk7ggahKAFQEUR3UWN B0I4TAJGareycZ2QFGvJYEQ= X-Google-Smtp-Source: ABdhPJz4gRG2A32sGzAfcHZ66PB3N78cOzrpsqLmQPbStAAohyvMC5U0xEoflplH77GEmL2Zf9PVIw== X-Received: by 2002:adf:d4ca:: with SMTP id w10mr816978wrk.146.1614808140459; Wed, 03 Mar 2021 13:49:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 20/28] target/arm: Move code blocks around Date: Wed, 3 Mar 2021 22:47:00 +0100 Message-Id: <20210303214708.1727801-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To simplify later #ifdef'ry, move some code around. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/internals.h | 16 ++++++++-------- target/arm/debug_helper.c | 22 +++++++++++----------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index d6ace004855..3fb295431ae 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -278,14 +278,6 @@ void hw_watchpoint_update_all(ARMCPU *cpu); * Update a QEMU breakpoint based on the information the guest has set in = the * DBGBCR_EL1 and DBGBVR_EL1 registers. */ -void hw_breakpoint_update(ARMCPU *cpu, int n); -/* - * Update the QEMU breakpoints for every guest breakpoint. This does a - * complete delete-and-reinstate of the QEMU breakpoint list and so is - * suitable for use after migration or on reset. - */ -void hw_breakpoint_update_all(ARMCPU *cpu); - /* Callback function for checking if a watchpoint should trigger. */ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 @@ -295,6 +287,14 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatch= point *wp); */ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); =20 +void hw_breakpoint_update(ARMCPU *cpu, int n); +/* + * Update the QEMU breakpoints for every guest breakpoint. This does a + * complete delete-and-reinstate of the QEMU breakpoint list and so is + * suitable for use after migration or on reset. + */ +void hw_breakpoint_update_all(ARMCPU *cpu); + /* Callback function for when a watchpoint or breakpoint triggers. */ void arm_debug_excp_handler(CPUState *cs); =20 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2ff72d47d19..c01d8524443 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -216,6 +216,17 @@ static bool check_watchpoints(ARMCPU *cpu) return false; } =20 +bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ + /* + * Called by core code when a CPU watchpoint fires; need to check if t= his + * is also an architectural watchpoint match. + */ + ARMCPU *cpu =3D ARM_CPU(cs); + + return check_watchpoints(cpu); +} + static bool check_breakpoints(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; @@ -247,17 +258,6 @@ void HELPER(check_breakpoints)(CPUARMState *env) } } =20 -bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) -{ - /* - * Called by core code when a CPU watchpoint fires; need to check if t= his - * is also an architectural watchpoint match. - */ - ARMCPU *cpu =3D ARM_CPU(cs); - - return check_watchpoints(cpu); -} - void arm_debug_excp_handler(CPUState *cs) { /* --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808147; cv=none; d=zohomail.com; s=zohoarc; b=TR+5CrDCu9k2T+TZt5Nb5sE1ZtT6UUyalXzcRF+Z1Pyy00K210lJafTcIS1EPtUL7DlFOWGkaqy2TjJkwpiD8fVkBmIyF/nfH2XgjhCHd/ABOHX5QtMCu620NABc2v9ni5N3b/H4Tn+vy4Wx3iZzJkqjrXPrkuSksYDaEyyLUww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808147; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YomvsDs5ZuIQvjHtj4a66pfmvsA4AEqB6lKkhbtyTa0=; b=n4qqYIuwDNwGn7wr0zIDdbnqLdpThWGa74hjTg2tvYydB0r9frYiJwEnTXk20HCFOm9VK0nqB1IkLoV66cmWmkLY273dsMY9zeyDgJmXcmi4wIViXx3iJIP4A6XdJRmk42XCA52oFtrb/nTNGc5jGja4JPXgING6hsGMfneOQDU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.zohomail.com with SMTPS id 1614808147355642.7192205334571; Wed, 3 Mar 2021 13:49:07 -0800 (PST) Received: by mail-wr1-f45.google.com with SMTP id b18so18891242wrn.6 for ; Wed, 03 Mar 2021 13:49:06 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id h22sm9089008wmb.36.2021.03.03.13.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:49:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YomvsDs5ZuIQvjHtj4a66pfmvsA4AEqB6lKkhbtyTa0=; b=Q9kzaXXLsrtgfnSy3Tmba9fCoXSao4m4lBzQq5YHleVSSrhl5zcnSqGhWkEO4OAobR WvW/ywB6OTsHYI6wQ8cPu6VaeIvn/CYQiUjUcCYUDVEQG7R8Ms7BiFJx0ZyN88JYnF0u G/52mSy5QIerKxgusOdPeJgyGXbt6ahhnW5NmJrE85vpSEc617OVjW9CJcp0t++14T5b BjkEBuNXGKWR7Z4Teu6KbLpTp9kiXtNX24tHACRzjnjBqG+1lbJ+uDPGBBYeCivsdwSI OO0FsP49qsvuTTNGyX8rMMWTUxEB17cYGPC6IBxoLdEdsv2hn3uVOx39iIMg6psvp6hA q6HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YomvsDs5ZuIQvjHtj4a66pfmvsA4AEqB6lKkhbtyTa0=; b=a/xLLAUlNrOSzXAvNeW3Y2G0zC+G/0AGA+9NNtIjhdyJqbHKRu3c1OXcH6ynskBq60 sPWfR3VXRFkCGSWZEhccmzPwtqg8ioNEg/rCcwVdk6jIApnczg0h/Lkw00ArMYX91tny uykTOrhrmDWOVNoAqf4GDRUzonYTWlMgZ6NELjWwOpAViNc/v6rL2zgv7jml4pTSi6sh cMkpxK46yNt7XZdffqYElH77sVM6GFksj6N9iCnLubFLKqEgqsJz73k/x7EYV2t0N5JG uBstXbd1A+kPtTnsQK+IvzsDlKb1nprI0Y20Ew811ihmC0/KUteMm1Nnxg07ihrs+FQV cl/A== X-Gm-Message-State: AOAM5326e3istVqYqDk6rjPeoXQ8L4xZC+8eCYTA2kvudLd3hxPHTBR7 oeVWNnkEgNBQ480KEvDO3R8= X-Google-Smtp-Source: ABdhPJzaxOXYuwf2B9PFQezRCx5O1WE2DWF5RcZ8r+jGknmMEb+TBFXF69v358dK6ZjgUEnlnFQ20w== X-Received: by 2002:adf:9261:: with SMTP id 88mr754722wrj.270.1614808145655; Wed, 03 Mar 2021 13:49:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 21/28] target/arm: Refactor some function bodies Date: Wed, 3 Mar 2021 22:47:01 +0100 Message-Id: <20210303214708.1727801-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Refactor few fonctions body to ease #ifdef'ry review in the next commit. No logical change intented. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- Patch easier to review using: 'git-diff --color-moved-ws=3Dallow-indentation-change' --- target/arm/debug_helper.c | 72 +++++++++++++++++++-------------------- target/arm/helper.c | 5 ++- 2 files changed, 38 insertions(+), 39 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index c01d8524443..980110e1328 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -230,7 +230,6 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchp= oint *wp) static bool check_breakpoints(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; - int n; =20 /* * If breakpoints are disabled globally or we can't take debug @@ -241,7 +240,7 @@ static bool check_breakpoints(ARMCPU *cpu) return false; } =20 - for (n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { + for (int n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; } @@ -266,47 +265,48 @@ void arm_debug_excp_handler(CPUState *cs) */ ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + uint64_t pc; + bool same_el; CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; =20 - if (wp_hit) { - if (wp_hit->flags & BP_CPU) { - bool wnr =3D (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) !=3D 0; - bool same_el =3D arm_debug_target_el(env) =3D=3D arm_current_e= l(env); + if (wp_hit && (wp_hit->flags & BP_CPU)) { + bool wnr =3D (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) !=3D 0; + bool same_el =3D arm_debug_target_el(env) =3D=3D arm_current_el(en= v); =20 - cs->watchpoint_hit =3D NULL; - - env->exception.fsr =3D arm_debug_exception_fsr(env); - env->exception.vaddress =3D wp_hit->hitaddr; - raise_exception(env, EXCP_DATA_ABORT, - syn_watchpoint(same_el, 0, wnr), - arm_debug_target_el(env)); - } - } else { - uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; - bool same_el =3D (arm_debug_target_el(env) =3D=3D arm_current_el(e= nv)); - - /* - * (1) GDB breakpoints should be handled first. - * (2) Do not raise a CPU exception if no CPU breakpoint has fired, - * since singlestep is also done by generating a debug internal - * exception. - */ - if (cpu_breakpoint_test(cs, pc, BP_GDB) - || !cpu_breakpoint_test(cs, pc, BP_CPU)) { - return; - } + cs->watchpoint_hit =3D NULL; =20 env->exception.fsr =3D arm_debug_exception_fsr(env); - /* - * FAR is UNKNOWN: clear vaddress to avoid potentially exposing - * values to the guest that it shouldn't be able to see at its - * exception/security level. - */ - env->exception.vaddress =3D 0; - raise_exception(env, EXCP_PREFETCH_ABORT, - syn_breakpoint(same_el), + env->exception.vaddress =3D wp_hit->hitaddr; + raise_exception(env, EXCP_DATA_ABORT, + syn_watchpoint(same_el, 0, wnr), arm_debug_target_el(env)); + return; } + + pc =3D is_a64(env) ? env->pc : env->regs[15]; + same_el =3D (arm_debug_target_el(env) =3D=3D arm_current_el(env)); + + /* + * (1) GDB breakpoints should be handled first. + * (2) Do not raise a CPU exception if no CPU breakpoint has fired, + * since singlestep is also done by generating a debug internal + * exception. + */ + if (cpu_breakpoint_test(cs, pc, BP_GDB) + || !cpu_breakpoint_test(cs, pc, BP_CPU)) { + return; + } + + env->exception.fsr =3D arm_debug_exception_fsr(env); + /* + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing + * values to the guest that it shouldn't be able to see at its + * exception/security level. + */ + env->exception.vaddress =3D 0; + raise_exception(env, EXCP_PREFETCH_ABORT, + syn_breakpoint(same_el), + arm_debug_target_el(env)); } =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0e1a3b94211..54648c7fbb6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6595,7 +6595,7 @@ static void define_debug_regs(ARMCPU *cpu) * These are just dummy implementations for now. */ int i; - int wrps, brps, ctx_cmps; + int brps, ctx_cmps; =20 /* * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot @@ -6614,7 +6614,6 @@ static void define_debug_regs(ARMCPU *cpu) =20 /* Note that all these register fields hold "number of Xs minus 1". */ brps =3D arm_num_brps(cpu); - wrps =3D arm_num_wrps(cpu); ctx_cmps =3D arm_num_ctx_cmps(cpu); =20 assert(ctx_cmps <=3D brps); @@ -6644,7 +6643,7 @@ static void define_debug_regs(ARMCPU *cpu) define_arm_cp_regs(cpu, dbgregs); } =20 - for (i =3D 0; i < wrps; i++) { + for (i =3D 0; i < arm_num_wrps(cpu); i++) { ARMCPRegInfo dbgregs[] =3D { { .name =3D "DBGWVR", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808152; cv=none; d=zohomail.com; s=zohoarc; b=ZW5OZZhmTrmdDqTa/WLUuYF2xYkt9YTsjwmtYto3hhqacvNu16mgMLFtvWgujt09iKVE1u4YeNSnPFViJoQmJF/gIeOH2uDZjidhkogi2OiavBK9cxxj4eKZkL9mK7uzH3xqxadq41H1IAVHuZZZLyV8cEUjiqQ8BMI5DG266II= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808152; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S715M+675Z0PbXHD9I+O0NRlMeoHb9x2yw8235n4aD4=; b=QOHYkfHmnSE/pIegsOVHBYiEw/M6iInqnWHFEVhDE0/06+YEJNn/z6snqB9l/fQ7szQmenKS7TFrExrfJMmjcSZLHfmmuRLdg/EibUWaf9HKMqeDKCvJ8H/snnkmpKK7Zi4KsnKtP7pHzvYYTZsQiN7E94LMIwW9DNxPsoAk1u0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.zohomail.com with SMTPS id 16148081527571014.8352622282986; Wed, 3 Mar 2021 13:49:12 -0800 (PST) Received: by mail-wm1-f52.google.com with SMTP id w203-20020a1c49d40000b029010c706d0642so3599410wma.0 for ; Wed, 03 Mar 2021 13:49:12 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id i8sm39345178wry.90.2021.03.03.13.49.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:49:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S715M+675Z0PbXHD9I+O0NRlMeoHb9x2yw8235n4aD4=; b=DNtWkruqQxMBHcQBamIrB4xsS7MiGaAHrAuEuSs5YOzzpdCnZZm7sKSNOXBWI5liGW H2lDY0QTTk+AyiIejw1ZHVZJlLHGPtQ9o/o3k8LwkPNwIO4cVZZSDE519gmSckUlxsDf tr53Ze5OuSq4JewiMuHpFs6rIGKIXGCNLIgcsQLwQkXIxRRkjsxmnXR7wKfByBpXIlfw z5Y01cxTBhYxiYtpta2UG4LMabBcIGwunB56wdmrFy3qOypaepMshPs4m8+mE/Gws6XD 1lVReeu3obRyPgms1cnCdr7zV+MSK37qVJ2U1H/Dp66kQYwD6/8D3VTXjZnqD2vCALbS nSYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=S715M+675Z0PbXHD9I+O0NRlMeoHb9x2yw8235n4aD4=; b=MSB2AXOBbxY0eMyIuhr160MOUffZ8xr4XNn28BuRm9NrzYY7X4terluL38EnuCffzB 3XC2VKe1rYRDNv8L9J9dSkwhnOvJIzFc2Rw+asOrCLNcu6UtNv/nhX5vDEeBRuSw24L9 9uOeCcxzqrQYmdDrQxSTrWgAisvBNHKRMljMROd886Zx3P7rZqCBerrqVISWVg15zoA7 Msfgy+zcqr0UUCwuvrUzazSubYMS24vhnBbOd/f4uzPZhhtvyXiVsC6PEHYpLQGQn0pg g72PezJ2+3oc6gTOfeBhhZSKc7o5E5SdRYffRIhUvmvutBcdMiR92B22OifPeX5ZLweR zc8g== X-Gm-Message-State: AOAM5339tqcxDqDeMSQYeQ8V3jM2aaZYcqUwuZBGvxuvwfG37YlxzHLb 1Ll9JNfLYCvvsAJaf5ee/M7dsXzDZiU= X-Google-Smtp-Source: ABdhPJyzq/395EXQ7e4rc/g9RXP3aHnx4RSP9K994E5vIztFHzllmbAJ3xzDwYr2hRTxnQ8Y/iALCg== X-Received: by 2002:a05:600c:2254:: with SMTP id a20mr852186wmm.115.1614808150922; Wed, 03 Mar 2021 13:49:10 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 22/28] target/arm: Restrict watchpoint code to system emulation Date: Wed, 3 Mar 2021 22:47:02 +0100 Message-Id: <20210303214708.1727801-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We can not use watchpoints in user-mode emulation because we need the softmmu slow path to detect accesses to watchpointed memory. Add #ifdef'ry around it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/cpu.c | 4 ++-- target/arm/debug_helper.c | 8 ++++++++ target/arm/helper.c | 4 ++++ target/arm/sve_helper.c | 12 ++++++++++++ 5 files changed, 28 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3fb295431ae..8fa0a244d59 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -263,6 +263,7 @@ static inline bool extended_addresses_enabled(CPUARMSta= te *env) (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EA= E)); } =20 +#ifndef CONFIG_USER_ONLY /* * Update a QEMU watchpoint based on the information the guest has set in = the * DBGWCR_EL1 and DBGWVR_EL1 registers. @@ -286,6 +287,7 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchp= oint *wp); * addresses. */ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); +#endif /* !CONFIG_USER_ONLY */ =20 void hw_breakpoint_update(ARMCPU *cpu, int n); /* diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 09566a535e5..efc338b24eb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -432,10 +432,10 @@ static void arm_cpu_reset(DeviceState *dev) if (kvm_enabled()) { kvm_arm_reset_vcpu(cpu); } -#endif =20 - hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); +#endif + hw_breakpoint_update_all(cpu); arm_rebuild_hflags(env); } =20 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 980110e1328..b8b7d81762d 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,6 +11,8 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" =20 +#ifndef CONFIG_USER_ONLY + /* Return true if the linked breakpoint entry lbn passes its checks */ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { @@ -227,6 +229,8 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchp= oint *wp) return check_watchpoints(cpu); } =20 +#endif /* !CONFIG_USER_ONLY */ + static bool check_breakpoints(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; @@ -240,11 +244,13 @@ static bool check_breakpoints(ARMCPU *cpu) return false; } =20 +#ifndef CONFIG_USER_ONLY for (int n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; } } +#endif /* !CONFIG_USER_ONLY */ return false; } =20 @@ -267,6 +273,7 @@ void arm_debug_excp_handler(CPUState *cs) CPUARMState *env =3D &cpu->env; uint64_t pc; bool same_el; +#ifndef CONFIG_USER_ONLY CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; =20 if (wp_hit && (wp_hit->flags & BP_CPU)) { @@ -282,6 +289,7 @@ void arm_debug_excp_handler(CPUState *cs) arm_debug_target_el(env)); return; } +#endif /* !CONFIG_USER_ONLY */ =20 pc =3D is_a64(env) ? env->pc : env->regs[15]; same_el =3D (arm_debug_target_el(env) =3D=3D arm_current_el(env)); diff --git a/target/arm/helper.c b/target/arm/helper.c index 54648c7fbb6..2e7a6356ae3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6345,6 +6345,7 @@ static const ARMCPRegInfo zcr_el3_reginfo =3D { .writefn =3D zcr_write, .raw_writefn =3D raw_write }; =20 +#ifndef CONFIG_USER_ONLY void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env =3D &cpu->env; @@ -6470,6 +6471,7 @@ static void dbgwcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, raw_write(env, ri, value); hw_watchpoint_update(cpu, i); } +#endif /* !CONFIG_USER_ONLY */ =20 void hw_breakpoint_update(ARMCPU *cpu, int n) { @@ -6643,6 +6645,7 @@ static void define_debug_regs(ARMCPU *cpu) define_arm_cp_regs(cpu, dbgregs); } =20 +#ifndef CONFIG_USER_ONLY for (i =3D 0; i < arm_num_wrps(cpu); i++) { ARMCPRegInfo dbgregs[] =3D { { .name =3D "DBGWVR", .state =3D ARM_CP_STATE_BOTH, @@ -6661,6 +6664,7 @@ static void define_debug_regs(ARMCPU *cpu) }; define_arm_cp_regs(cpu, dbgregs); } +#endif /* !CONFIG_USER_ONLY */ } =20 static void define_pmu_regs(ARMCPU *cpu) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 844db08bd57..ed3f22d78a5 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4849,6 +4849,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, /* Some page is MMIO, see below. */ goto do_fault; } +#ifndef CONFIG_USER_ONLY if (unlikely(flags & TLB_WATCHPOINT) && (cpu_watchpoint_address_matches (env_cpu(env), addr + mem_off, 1 << msz) @@ -4856,6 +4857,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, /* Watchpoint hit, see below. */ goto do_fault; } +#endif if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { goto do_fault; } @@ -4900,12 +4902,14 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, cons= t target_ulong addr, uint64_t pg =3D *(uint64_t *)(vg + (reg_off >> 3)); do { if ((pg >> (reg_off & 63)) & 1) { +#ifndef CONFIG_USER_ONLY if (unlikely(flags & TLB_WATCHPOINT) && (cpu_watchpoint_address_matches (env_cpu(env), addr + mem_off, 1 << msz) & BP_MEM_READ)) { goto do_fault; } +#endif if (mtedesc && !mte_probe1(env, mtedesc, addr + mem_off)) { goto do_fault; } @@ -5355,10 +5359,12 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, mmu_idx, retaddr); =20 if (likely(in_page >=3D msize)) { +#ifndef CONFIG_USER_ONLY if (unlikely(info.flags & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), addr, msize, info.attrs, BP_MEM_READ, reta= ddr); } +#endif if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { mte_check1(env, mtedesc, addr, retaddr); } @@ -5367,11 +5373,13 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, /* Element crosses the page boundary. */ sve_probe_page(&info2, false, env, addr + in_page, 0, MMU_DATA_LOAD, mmu_idx, retaddr); +#ifndef CONFIG_USER_ONLY if (unlikely((info.flags | info2.flags) & TLB_WATCHPOI= NT)) { cpu_check_watchpoint(env_cpu(env), addr, msize, info.attrs, BP_MEM_READ, retaddr); } +#endif if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { mte_check1(env, mtedesc, addr, retaddr); } @@ -5568,11 +5576,13 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64= _t *vg, void *vm, if (unlikely(info.flags & (TLB_INVALID_MASK | TLB_MMIO))) { goto fault; } +#ifndef CONFIG_USER_ONLY if (unlikely(info.flags & TLB_WATCHPOINT) && (cpu_watchpoint_address_matches (env_cpu(env), addr, msize) & BP_MEM_READ)) { goto fault; } +#endif if (mtedesc && arm_tlb_mte_tagged(&info.attrs) && !mte_probe1(env, mtedesc, addr)) { @@ -5754,10 +5764,12 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t= *vg, void *vm, info.flags |=3D info2.flags; } =20 +#ifndef CONFIG_USER_ONLY if (unlikely(info.flags & TLB_WATCHPOINT)) { cpu_check_watchpoint(env_cpu(env), addr, msize, info.attrs, BP_MEM_WRITE, retaddr= ); } +#endif =20 if (mtedesc && arm_tlb_mte_tagged(&info.attrs)) { mte_check1(env, mtedesc, addr, retaddr); --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808157; cv=none; d=zohomail.com; s=zohoarc; b=ZrwgFVWgKagMowJCLRrsGuaMwfS9e4DVMyqnjVRBwkgNOdrOVdQPY9Bq528THCO/12vrO7JhTstUDw+H0W1UV4grl81uS4hO3t/piEF3Nr1DFqkC8hzq5LfU3zmIlDNvd44pQPZQolV4N8nq4lJ5xgjxCvbu48PHm7DT1+2IprQ= ARC-Message-Signature: i=1; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id d85sm7280009wmd.15.2021.03.03.13.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:49:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9CGCXi9+Tg5mub0B9murOfm8Ay83y93iGvVDRpdfsps=; b=BncbyaUijP8mQby/RC1m6CuBqJhX4f8uzsk1xf64D9tsy+AD9d9Brmpw5VZRQO5Syj o7dArspPMkOOna0J7WUiL/VZKqa53GatDrqwn81COGz1Kmg6n6n+PgYM7Ojvi0zo/SsJ OH4A6PPki8hgQwWddehU5FTIuhNRyDe0sGkriywquNcSNxM+lnOO2qlBfcA1BLLjq+o0 N5Qzx5ODP0kfUJ39RwRX1uDACMjEbHauAqY0TD3Fh7164xGvF+VquUY3zrvXwZWm8bG0 xIEOPPoEtQZaGTdgO50avbceoOmKWn2ovQKrYyYuaFK/1KFgo26ChFQUdCSNo0KtUTRb RFOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9CGCXi9+Tg5mub0B9murOfm8Ay83y93iGvVDRpdfsps=; b=onOwrH3TOjTbFkHlVbkWcLWDXTarHlTaML42/nSKj7YB6O+DN2pQgUN3pmbKQlwbiC A75hl64gsqQjK4bxOQy6vBV0/X9t/SdMpboook/459/9hHo33bE5N+eUgbBtlmjrkD/9 vE+xZXnbJt+JaASq33KSokmhLdsNw29eQ0AJ78Pvgp2ULD73P4GTV75Ub9cRp9JEJWTl lKzgS5OQaOZ9H7464ANjmli8wNUtGlYyAw8AtKrtMCJ6UDCnpr49dGCksBxKiN/es5dS 9Ut2AGd4xbPp5/7DbVxic0uRiL3g2D1sNnyU0yJCdxhfMCZZrXKLpNm4nLOEBi/HxqEq tO6g== X-Gm-Message-State: AOAM530JOC/KZQM/qeoSUnrQ4bQMAqPGuGTE/mNiiiLSg+N//1DDbe4g EZZV/YQCaM71vKoTkw+IIWQ= X-Google-Smtp-Source: ABdhPJxYM063IJN0COFfaPkajKqL++yy+J1PkY9rOTXrR2FtKls2fwIULR4oDLlqPmI4itT1CUeXgw== X-Received: by 2002:adf:fd91:: with SMTP id d17mr815714wrr.0.1614808155948; Wed, 03 Mar 2021 13:49:15 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost Subject: [PATCH v4 23/28] target/i386: Restrict watchpoint code to system emulation Date: Wed, 3 Mar 2021 22:47:03 +0100 Message-Id: <20210303214708.1727801-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We can not use watchpoints in user-mode emulation because we need the softmmu slow path to detect accesses to watchpointed memory. Add #ifdef'ry around it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 994d58aa754..4b8f06f6193 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6182,7 +6182,6 @@ static void x86_cpu_reset(DeviceState *dev) env->dr[6] =3D DR6_FIXED_1; env->dr[7] =3D DR7_FIXED_1; cpu_breakpoint_remove_all(s, BP_CPU); - cpu_watchpoint_remove_all(s, BP_CPU); =20 cr4 =3D 0; xcr0 =3D XSTATE_FP_MASK; @@ -6205,6 +6204,8 @@ static void x86_cpu_reset(DeviceState *dev) if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { cr4 |=3D CR4_FSGSBASE_MASK; } +#else + cpu_watchpoint_remove_all(s, BP_CPU); #endif =20 env->xcr0 =3D xcr0; --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808162; cv=none; d=zohomail.com; s=zohoarc; b=Bnr/HQIOWNtEyHI5e3gtX+1zu9hTVPqYcbq6iNdfD1QUHQQGvmgq15GuvV9Op4NOg2oTfLm8qtxAVNClXpa5CXDUI1mvtORoflZuDeEjsqEjrQzVWdaBQhNNmx2kRMhJHoN9CYQsE9eO+cdU/Hv9+8mPQxNa4cLI5pX/6hKk2/g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808162; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EiAs45/8RrC9+ORKHg3D6zi8PaaattSX1vXVK8lwp1c=; b=BbnN8c1DpI+4OXKqhJOwj08C3nW2moHlutY9Hp6N1OFAK06OL4vVOm2TkEz0M1olkYbDweaaIoWAIyn3WFvFLXXAm7IwxFFsft3KnRgZzW9DTsqb2JnUt5gc7XWo35pM/rC95B01TNjNbbGOm/xx1BQaeXKefwcaDWaF1Xrr2bE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mx.zohomail.com with SMTPS id 1614808162763332.882906457397; Wed, 3 Mar 2021 13:49:22 -0800 (PST) Received: by mail-wr1-f53.google.com with SMTP id u16so7367157wrt.1 for ; Wed, 03 Mar 2021 13:49:22 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id r7sm33806893wre.25.2021.03.03.13.49.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:49:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EiAs45/8RrC9+ORKHg3D6zi8PaaattSX1vXVK8lwp1c=; b=ufEWTYp3p7tj6hEz3k8BTBwooYiH8JE2gOPjzdAVZBAQxBy49PqvCSMtwHVUvmH9tO OF58jteoXSWCt2xb2zqnQgvagPNAI+6QYEg4hgQ43fTnaIOMTMeddrbjhL6ikmFZUfVj s3Ed31LBPh6fVAo1A4RqjaOvcjWhcW3DfVsXsa93SI+qM4H2BwjHwQuykHklyqvjqbSy BWcN/B40cP0uVpQjX7xyktAmzuYFO4hGvSI5E8uFSdzKUL+gRdpsV3P43lpD+QrAzHed pU1E+US1ZSbayHmCTI1+Ig7SAXB5TymhMtHeYnZMKVq2OLycCtcWtbItm9Qx+oYUso+N GVSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EiAs45/8RrC9+ORKHg3D6zi8PaaattSX1vXVK8lwp1c=; b=Oclmn5L5ib9jr8SsEB+Y0jlmizrNclo/V6jOFgI6emgmUAcbOfq2BZdiPUkmdXxSYu xADVS0SyY7/LMjLa16NVqisvbZP0uilHRGWXcv1AXlYi6uHD1BaM01QGTpehG1XpKVnK /2Eelj1t4m7q2ZIurD+vac+htlcE2iJC+o9IldsCIRoBM866cWipANHDpoCuhzdhwR0d 8y0MY169w4Gmt61NroJoDHb7bVGTfKqpI5CvUfWvcZq0TFzVpjYwEgywUsZ3RhNLzaIP 8uKg6A/B1+KUFc7eBHbBOVF0SH1/YROmrOwz4J9RhZEbAdbVDlMHMmcvzQ4h32c6/7Kh sMGg== X-Gm-Message-State: AOAM5328Iz6U6hN/hot8Cn4qvZW9dI7EUvskBBKZeqkI/xaMVtRCaRAI CchcFExcex1Y7NLl+hFUsFI= X-Google-Smtp-Source: ABdhPJzuZWFGh3IGPE603zM6dkg+gEydT+i8E3xcrTonUKvbAsPed0eKEbxmkeJkLgl19/unaDBZEg== X-Received: by 2002:a05:6000:191:: with SMTP id p17mr813048wrx.154.1614808161082; Wed, 03 Mar 2021 13:49:21 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Max Filippov Subject: [PATCH v4 24/28] target/xtensa: Restrict watchpoint code to system emulation Date: Wed, 3 Mar 2021 22:47:04 +0100 Message-Id: <20210303214708.1727801-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We can not use watchpoints in user-mode emulation because we need the softmmu slow path to detect accesses to watchpointed memory. Add #ifdef'ry around it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/xtensa/helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index eeffee297d1..85e466b37d2 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -201,6 +201,7 @@ void xtensa_register_core(XtensaConfigList *node) g_free((gpointer)type.name); } =20 +#ifndef CONFIG_USER_ONLY static uint32_t check_hw_breakpoints(CPUXtensaState *env) { unsigned i; @@ -213,9 +214,11 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *e= nv) } return 0; } +#endif =20 void xtensa_breakpoint_handler(CPUState *cs) { +#ifndef CONFIG_USER_ONLY XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; =20 @@ -231,6 +234,7 @@ void xtensa_breakpoint_handler(CPUState *cs) cpu_loop_exit_noexc(cs); } } +#endif } =20 void xtensa_cpu_list(void) --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808168; cv=none; d=zohomail.com; s=zohoarc; b=mlN7VAk199wm2e3LPbzBh2sInC8+xOaEf0SuShBUvBIE+7FS8+OB3BgAL+xzhqJfHQ7fXQJCwjUm0e5QSPhl1MQKHQ08rgk2kAXFAVA7L5QjGWmR863jcpqQT9IRA41Idj6IAvovNtNeaGYPxiRnKpFuq42KXmXpazwT+oT8NcA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808168; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4R5DcpwiVyH1crneA2P/IW+Ft2bwjopPdJYmPr1uTds=; b=I3umkX9zvN1WflXBr0+yMIzHM4JfTgcLAfybU1Ml/F9K6VKdD6VzKH7SfyfhpthjaB9SHrZoSHZQqcuC786WcLIGk2M4R/JAXCjb4nVaLVWjoGkVeOLR72w2QmSZstdV8NS2Ig69N6RjLXlHuH/onV7oNMVdvBLsgr/cKddOfJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1614808168777749.5987470439259; Wed, 3 Mar 2021 13:49:28 -0800 (PST) Received: by mail-wr1-f50.google.com with SMTP id l12so25366742wry.2 for ; Wed, 03 Mar 2021 13:49:27 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id o13sm38037052wro.15.2021.03.03.13.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:49:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4R5DcpwiVyH1crneA2P/IW+Ft2bwjopPdJYmPr1uTds=; b=NbAIWa7c7wZe+GDH8szDSnlBZPWxefFR6ntjrAyy3SKVtlc+p67YkOygXelyZmOmah OacmPQiMQ0lbJXnBe+33mRgfmD5dw7+k+5Ow/5Pn1Ci9mGYzyOz5bhtpFfpCkY3+QQrZ 5OpMSLo+GrtqvuQrFkRHoCmjX4zqF9222pqR0ZAzPPMiqRDPvrAK4bs5UwU7ZNOVznZF f9Xvgwp06LFaXUxDXE7xbatRKqokXNme+UMnhRg/a+IFQ5sisTntQew93UxnY+Pof4nA KfW9JorwSMGyM8dJqxFIBkOk5Xngz0MR+vlqm+6W06idIcZ7v2TDzmRgin0C7txbfgFy 8uTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4R5DcpwiVyH1crneA2P/IW+Ft2bwjopPdJYmPr1uTds=; b=fiDtzZ6rc+1hntZo4p5U6ZzTrc+1uub0N4QlKcsmwRHlpXNUSz6V4XYsnLeTYrDF6v ZXUucbwO0Qs/5CAIZcsETyhoiOKNKF1UTMnu0ur73qskYejPtJ9CmhkTDmemAz4WBjjR 3Rv9/CaIsIdyyjaGynwCimNfeO30xeMBtVU99cKZ1dxKvi1JBFERi0NtqTmXqO/z2/J2 WCdX+RZF61ODgj7rDh5IRRg8nhEE1D3iMlHIgS6Ucsc2aDYm8xS6DQR9qHkIyXl8RpDo TbHyHC98MGLQ5f3LqtDCSD4vCyILveTeca2WC79iAm4tfUaps14If49pI9RMv0PuqRK2 OfKA== X-Gm-Message-State: AOAM531+lwJ8SDL+pOM63DVDr2uKZvTkaFsk3zfQLufQCnVNW1HCP3Cd VP5volvovKHBdigGeyodxhA= X-Google-Smtp-Source: ABdhPJw5M5BRw3KaT9S7Kgh8uaaWjhLQQiXmBsGhFLwNCBpvbqOZzXsB1MohyDvx9cI1GkLbED4wdA== X-Received: by 2002:adf:a418:: with SMTP id d24mr663327wra.187.1614808166003; Wed, 03 Mar 2021 13:49:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 25/28] accel/tcg/cpu-exec: Restrict watchpoint code to system emulation Date: Wed, 3 Mar 2021 22:47:05 +0100 Message-Id: <20210303214708.1727801-26-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We can not use watchpoints in user-mode emulation because we need the softmmu slow path to detect accesses to watchpointed memory. Add #ifdef'ry around it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 16e4fe3ccd8..3a6436013ea 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -471,13 +471,16 @@ static inline bool cpu_handle_halt(CPUState *cpu) static inline void cpu_handle_debug_exception(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUWatchpoint *wp; =20 +#ifndef CONFIG_USER_ONLY if (!cpu->watchpoint_hit) { + CPUWatchpoint *wp; + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { wp->flags &=3D ~BP_WATCHPOINT_HIT; } } +#endif =20 if (cc->tcg_ops->debug_excp_handler) { cc->tcg_ops->debug_excp_handler(cpu); --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808172; cv=none; d=zohomail.com; s=zohoarc; b=QSDtMPir117WrKhbUT+Ni4h2ffbE3qWa5lwp7/WAVxNHxfN5LJNbkler844FFot9AXrK7ZWIPoo9GNg9vS5mUOIR5e2s1Fl1TMfgLsBLnkFwS2nQ0rj9HRZkz4/Ry0uVdV/ny0oDJLu4ljs6GMbeBXe7w7D+VE7OH/o8lXFmrVs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808172; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bxkFypL9ynYmWsntppZ7LktvbyLhxQp4d+/kAn8sAgo=; b=ZEK3SGaH6NRSeoUA80fV9whEK1zLU2/ORayIwh6BQEF8M6uZzMqJa5RwuOMpIwKUAYBbFzOhsfPv7Iq2/Pop1bnMP0Uef5eYK7aU1d9iygXO8BcT32WO56hEhv9IvbwxtrZ2HbOqkhoETB0AUgwvmMp6EAduqhSU2K1Z/0D8b0w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1614808172817608.14182398092; Wed, 3 Mar 2021 13:49:32 -0800 (PST) Received: by mail-wr1-f49.google.com with SMTP id w11so25345851wrr.10 for ; Wed, 03 Mar 2021 13:49:32 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id o2sm6723019wme.16.2021.03.03.13.49.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:49:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bxkFypL9ynYmWsntppZ7LktvbyLhxQp4d+/kAn8sAgo=; b=MBF4+lTxuVvAnOCUmds0Qif+mBC839/cwZpVlFExnBSDxJq0zPe9fiuu+X20wPaSKp HUA2DhHdtUnQPmmwONDZVz2FtdSMAXVJjHBrkFo5Y7eWWMWWmMlJB91E/1q/xGdRLC5g E1K7DnDmYmFhlPAwNEPUCYeVHf00vOQukF+hvEJihnNa/47ymr5qPHXg3OOVdLoW2a1q t4hLkJqznaHlZZ3Wu+Z9qYcqzsKlwtQP9LhVkIsBOK4RZkudywiesPTs70J4Nn7IfYvi HOuMj3ZvWNav8bhX8wTzcbEOeB8c3dr7D658TkZdiKL8bhMEYmrmifgud+63wr9HdA4T aXmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=bxkFypL9ynYmWsntppZ7LktvbyLhxQp4d+/kAn8sAgo=; b=cOc1RFWzGrAjyRT9t0L7Pr798Xt+Rm+L8DgklDagqSOeAOb8TCGTqV+e8kPvgiE96h OiWfAABAQYg6Am3ae85b/UlPmCn/KEUmdXfkf8f0+7Vk/Wk1+Ccjrxj4z+4FOLcJG2LN 929EJl1Bw6b7nHyWDc4HgW9fhbbz9/whHdD234IxGteCfa5TSES81UidwEek1HWXREtb p5hjTb9TVaG4PNCPJEcZkKImWrfgrKWH6k+xQdNCpV3ee0jQ79XScFCWMDmu3drEQ3pH TdK/RFJmaWxqQESUEy9AP7HNfLMAcijAM6fKCaHtkeU/poLkYkvjnEzETDTunUZw2s+s EdRw== X-Gm-Message-State: AOAM532UeDR5cFoBqy+uFpj1x6kalms2CY9ZOg7z3NzxYxxBH/ttZhlB mRKFeSsw/HWAEFU9067FLbg= X-Google-Smtp-Source: ABdhPJzZfI7TQhb4TmfrwYHeRw812f6SyR8WPbICKpu/1KKUh9xn2khVtehQMbw0VqHf6UkDh81hMA== X-Received: by 2002:adf:a18a:: with SMTP id u10mr681832wru.197.1614808171102; Wed, 03 Mar 2021 13:49:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 26/28] cpu: Remove watchpoint stubs for user emulation Date: Wed, 3 Mar 2021 22:47:06 +0100 Message-Id: <20210303214708.1727801-27-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since we remove all access to the watchpoint methods from user-mode code, we can now remove them, as they are not used anymore. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 34 +--------------------------------- 1 file changed, 1 insertion(+), 33 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fe4206b540f..b708f365a7a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -916,39 +916,7 @@ static inline bool cpu_breakpoint_test(CPUState *cpu, = vaddr pc, int mask) return false; } =20 -#ifdef CONFIG_USER_ONLY -static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr l= en, - int flags, CPUWatchpoint **watchpo= int) -{ - return -ENOSYS; -} - -static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, - vaddr len, int flags) -{ - return -ENOSYS; -} - -static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, - CPUWatchpoint *wp) -{ -} - -static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) -{ -} - -static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr l= en, - MemTxAttrs atr, int fl, uintptr_t = ra) -{ -} - -static inline int cpu_watchpoint_address_matches(CPUState *cpu, - vaddr addr, vaddr len) -{ - return 0; -} -#else +#ifndef CONFIG_USER_ONLY int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) client-ip=209.85.128.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614808177; cv=none; d=zohomail.com; s=zohoarc; b=PMFd6IEmfJuVoZ0JYXTZjjafcQQ2lIo13duku6sjnUV/Vh84QV08lp4kn6N8tfOyaSqlufJz6jTkjpExyou+4NJD8pfFkcRvT2/hjTDGfqXd4+QP572USne6/P73NDBkbZ9cotL268NlitCghbhv71H2bmYnITgJx0YiY1ZQImw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808177; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=thZpYEs3ORtBK7nisq+USWMtn89YjLX4bCvj3GSE47w=; b=SL92teo2cK1eoshaVMvOxwHw2XLKuKO1BU29WFUHJ9S45NJGl4RHFT6GU1LxIF5MSFUgF14mXbNjXDnxNllt5ZMX/ZUEsePHu7SZ6dlukvWE2zVf57m0+2QGMqwye3TfIcUfv9kMqiMvXv9k6ebKdYf69UzlLBCSmVRG9EcoyDM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.zohomail.com with SMTPS id 1614808177983203.94002898647625; Wed, 3 Mar 2021 13:49:37 -0800 (PST) Received: by mail-wm1-f49.google.com with SMTP id i9so6350411wml.0 for ; Wed, 03 Mar 2021 13:49:37 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 4sm7508807wma.0.2021.03.03.13.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:49:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=thZpYEs3ORtBK7nisq+USWMtn89YjLX4bCvj3GSE47w=; b=mkP6p9uiQajrOH2sw9/hu/XEYG69bOwqb06XtRpvogIUyzs/80G7oxXFzln5SM5g5W Qoy9Lr+OQJT4RDzMBqPnVWtAfXK863wSrkwRefO3fJOI3yn11sp21rwIYcV6YX+vOW6B QTqrnZZpotMGJ/O6kuNCpfDJZgjCh1pDZuyvu9nOhFKPjlabCMZIV5514UvBnPU8XkPu NGUC1QHfgWDIgMkgoqKJbmbzNsoMfZll8PLZ4nvsYYIb2OEQ6zED0jUC3lCm9BOi7f1u jwx1cEXNVROlPZhqPQc+rvFBNItrzyCjNvYLAGqXraBzFhstquC0pvMSamn+QRkNRHwd ZMPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=thZpYEs3ORtBK7nisq+USWMtn89YjLX4bCvj3GSE47w=; b=gmCQ1Y0gHp1Obvn4A9mc7wueFR2H3PljZfPRevGmVT1Q8G5BOH1hO/JlyVYexkij/h ZdSZ56ksOAP30ewlMNXVpJ/VBnAccAVNRmMDDbx8dCHcam0VAOXJgU+KZM4hF8LDoCiy A9Oetiecq9DM6QptWrFUHiZ0bpAEs+ncHUezFJQZN0nfpc4qyaGGxmASUSnzN8VQuAUn o9yUXmjnL8S6JkXO4ws/vgz7T/rE+DEp+E/tet0omjZGpkIat7KUqMh0bAoRHCszghQe DcChHEKWGEi8gzMACc4BUe22OhZsldeq37ek2YrCwA4yXLIJetr/GaydsGerZFaa0J+m XkgA== X-Gm-Message-State: AOAM533BXmvkLELU6HyNN0N6hmlEAg6ydE0lnKp5iySwfbhE5pJyuyKR KKgQPqukeQmJuGc6N8DuM1c= X-Google-Smtp-Source: ABdhPJyVSlK14c0CczyHFZYx/XdOuM8JjnuE33R8uVycsbyotkDZItB77zBGfhNGQkSu9yOWAq3N5w== X-Received: by 2002:a1c:1d82:: with SMTP id d124mr851659wmd.1.1614808176266; Wed, 03 Mar 2021 13:49:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 27/28] cpu: Fix code style for checkpatch.pl Date: Wed, 3 Mar 2021 22:47:07 +0100 Message-Id: <20210303214708.1727801-28-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b708f365a7a..79dcc9a4e42 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -558,7 +558,8 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, */ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 -/** cpu_asidx_from_attrs: +/** + * cpu_asidx_from_attrs: * @cpu: CPU * @attrs: memory transaction attributes * --=20 2.26.2 From nobody Mon Feb 9 13:05:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614808183; cv=none; d=zohomail.com; s=zohoarc; b=JByJDjy3uMolh9c3PGnPCSNFw4J1viZ36YomQsS4SNDWkuF3wiDLnyvoC3uDqToNs8AHxE+8ttcoCLYofcqJyCtUEIeb7f8JyPYrJA8HFenXBo46FxHOxsM0AgnUGEAQ5P4lEl2zavPAHUqNeetTrePMH6doOYhqp5LM0v8oo2Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614808183; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ottfGjPoqRC/3E22juptG3JE4v6fY+pwU7Kpo+LVFR4=; b=gijaWFOuvWSUpPeDcIAqCQE95h2QF1QkUQ7rZSnkBsdSL2yqUR51gH0Ve3j7etCdvzoCdF6k6PjJHJ1gDGEUvguHfNomGyjAKbJEdIp3QS/9UzO/8ZoWb0kIqNXuW1ALguVSuhy5KqIvNuUFyeuEBTX3sUBPgpfiwXzhRQiWKE0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1614808183584706.6968884904654; Wed, 3 Mar 2021 13:49:43 -0800 (PST) Received: by mail-wr1-f49.google.com with SMTP id b18so18892751wrn.6 for ; Wed, 03 Mar 2021 13:49:42 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 12sm6911543wmw.43.2021.03.03.13.49.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 13:49:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ottfGjPoqRC/3E22juptG3JE4v6fY+pwU7Kpo+LVFR4=; b=nRIMcl+LiFaWh3K55iqaiz2Z18tEC4lkXVlScAIVZ+e87BdBMRRLTLgrXVTQWilmor 5j8rq6JDw8aCp5pfzEiqJ7dtDzoj2ctdnHRQoDUl4cW1VFFw3TMZZIK1/MUFxlPfYn9g 97NuDuxgleN6bcDoF7zC9wAqFOwduj+w2Ky5fLD4maWLx20lGDONl6zrjmmPy2oPSc7h Hdgqpr4QwnrJ96qghVkBhFpddsoyEU0botvjgsVK5rmJC5feXVkbfOArL2Ba0tikBtC7 2r2bPQuPncweFR+1JlbjXYStle9CTmdEL+oJAf7eGhMCq7F1+ef+qzsCn1ybl1mbxb8+ a32A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ottfGjPoqRC/3E22juptG3JE4v6fY+pwU7Kpo+LVFR4=; b=lMbP87y6JwXfB7ihxlPqc4e1s0KoXctVUDnncNGgZ9WsSRjKBeR5NkK4PMaW7U5Sa2 jXe9W40bGlaOvYzpziNsLUOd7mnEYBrAy0kKxs10pezWmA/9GAAgCKyJdTyu/RMWXaKH wI5Rqci/n04/eq2pS8tYVOo/tuULmazJWAc/RUCkZhKAq+/ku4heLg/NJy9+ytSvBcPu IQh2anBQ5xW8gcpUtdPr7LjIn8EUJmn9fldd4hJr9XRTFOnmPF1ryJ3utbvVVG8X9cLj Y8utIY+w969D5rg+l0rAZj6OY58y0jIB5wlYOigq9YnKxUT1t2obj5EbSrTngSLCtPy8 Zskw== X-Gm-Message-State: AOAM532ynBg4cW4UGLSvrrRX45//QeyIHysphDtie/ZfI0H3qVwte0du P9i9hluKcD2VCjb1OdYavwA= X-Google-Smtp-Source: ABdhPJzx/NeL6Z/9tjyLRnsi6ODtSzDA70XnjVI2L7w54pMfsZWrBgPlFNiSdqAzd3SRJeKXj2zIEA== X-Received: by 2002:a5d:5047:: with SMTP id h7mr705050wrt.111.1614808181761; Wed, 03 Mar 2021 13:49:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Claudio Fontana , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Richard Henderson , qemu-s390x@nongnu.org, Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Cornelia Huck , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH v4 28/28] cpu: Move sysemu specific declarations to 'sysemu-cpu-ops.h' Date: Wed, 3 Mar 2021 22:47:08 +0100 Message-Id: <20210303214708.1727801-29-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) All these prototypes and declarations don't need to be exposed on user-mode emulation. Move them to "sysemu-cpu-ops.h". Suggested-by: Claudio Fontana Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 164 ------------------------------- include/hw/core/sysemu-cpu-ops.h | 155 +++++++++++++++++++++++++++++ gdbstub.c | 1 + softmmu/physmem.c | 1 + 4 files changed, 157 insertions(+), 164 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 79dcc9a4e42..53598c02187 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -185,15 +185,6 @@ typedef struct CPUBreakpoint { QTAILQ_ENTRY(CPUBreakpoint) entry; } CPUBreakpoint; =20 -struct CPUWatchpoint { - vaddr vaddr; - vaddr len; - vaddr hitaddr; - MemTxAttrs hitattrs; - int flags; /* BP_* */ - QTAILQ_ENTRY(CPUWatchpoint) entry; -}; - #ifdef CONFIG_PLUGIN /* * For plugins we sometime need to save the resolved iotlb data before @@ -428,76 +419,6 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cp= u) extern bool mttcg_enabled; #define qemu_tcg_mttcg_enabled() (mttcg_enabled) =20 -/** - * cpu_paging_enabled: - * @cpu: The CPU whose state is to be inspected. - * - * Returns: %true if paging is enabled, %false otherwise. - */ -bool cpu_paging_enabled(const CPUState *cpu); - -/** - * cpu_get_memory_mapping: - * @cpu: The CPU whose memory mappings are to be obtained. - * @list: Where to write the memory mappings to. - * @errp: Pointer for reporting an #Error. - */ -void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, - Error **errp); - -#if !defined(CONFIG_USER_ONLY) - -/** - * cpu_write_elf64_note: - * @f: pointer to a function that writes memory to a file - * @cpu: The CPU whose memory is to be dumped - * @cpuid: ID number of the CPU - * @opaque: pointer to the CPUState struct - */ -int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - -/** - * cpu_write_elf64_qemunote: - * @f: pointer to a function that writes memory to a file - * @cpu: The CPU whose memory is to be dumped - * @cpuid: ID number of the CPU - * @opaque: pointer to the CPUState struct - */ -int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - -/** - * cpu_write_elf32_note: - * @f: pointer to a function that writes memory to a file - * @cpu: The CPU whose memory is to be dumped - * @cpuid: ID number of the CPU - * @opaque: pointer to the CPUState struct - */ -int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - -/** - * cpu_write_elf32_qemunote: - * @f: pointer to a function that writes memory to a file - * @cpu: The CPU whose memory is to be dumped - * @cpuid: ID number of the CPU - * @opaque: pointer to the CPUState struct - */ -int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - -/** - * cpu_get_crash_info: - * @cpu: The CPU to get crash information for - * - * Gets the previously saved crash information. - * Caller is responsible for freeing the data. - */ -GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); - -#endif /* !CONFIG_USER_ONLY */ - /** * CPUDumpFlags: * @CPU_DUMP_CODE: @@ -529,56 +450,6 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags); */ void cpu_dump_statistics(CPUState *cpu, int flags); =20 -#ifndef CONFIG_USER_ONLY -/** - * cpu_get_phys_page_attrs_debug: - * @cpu: The CPU to obtain the physical page address for. - * @addr: The virtual address. - * @attrs: Updated on return with the memory transaction attributes to use - * for this access. - * - * Obtains the physical page corresponding to a virtual one, together - * with the corresponding memory transaction attributes to use for the acc= ess. - * Use it only for debugging because no protection checks are done. - * - * Returns: Corresponding physical page address or -1 if no page found. - */ -hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); - -/** - * cpu_get_phys_page_debug: - * @cpu: The CPU to obtain the physical page address for. - * @addr: The virtual address. - * - * Obtains the physical page corresponding to a virtual one. - * Use it only for debugging because no protection checks are done. - * - * Returns: Corresponding physical page address or -1 if no page found. - */ -hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); - -/** - * cpu_asidx_from_attrs: - * @cpu: CPU - * @attrs: memory transaction attributes - * - * Returns the address space index specifying the CPU AddressSpace - * to use for a memory access with the given transaction attributes. - */ -int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); - -/** - * cpu_virtio_is_big_endian: - * @cpu: CPU - - * Returns %true if a CPU which supports runtime configurable endianness - * is currently big-endian. - */ -bool cpu_virtio_is_big_endian(CPUState *cpu); - -#endif /* CONFIG_USER_ONLY */ - /** * cpu_list_add: * @cpu: The CPU to be added to the list of CPUs. @@ -917,41 +788,6 @@ static inline bool cpu_breakpoint_test(CPUState *cpu, = vaddr pc, int mask) return false; } =20 -#ifndef CONFIG_USER_ONLY -int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, - int flags, CPUWatchpoint **watchpoint); -int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, - vaddr len, int flags); -void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); -void cpu_watchpoint_remove_all(CPUState *cpu, int mask); - -/** - * cpu_check_watchpoint: - * @cpu: cpu context - * @addr: guest virtual address - * @len: access length - * @attrs: memory access attributes - * @flags: watchpoint access type - * @ra: unwind return address - * - * Check for a watchpoint hit in [addr, addr+len) of the type - * specified by @flags. Exit via exception with a hit. - */ -void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, - MemTxAttrs attrs, int flags, uintptr_t ra); - -/** - * cpu_watchpoint_address_matches: - * @cpu: cpu context - * @addr: guest virtual address - * @len: access length - * - * Return the watchpoint flags that apply to [addr, addr+len). - * If no watchpoint is registered for the range, the result is 0. - */ -int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); -#endif - /** * cpu_get_address_space: * @cpu: CPU to get address space from diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 3f9a5199dd1..da66acdc87f 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -12,6 +12,15 @@ =20 #include "hw/core/cpu.h" =20 +struct CPUWatchpoint { + vaddr vaddr; + vaddr len; + vaddr hitaddr; + MemTxAttrs hitattrs; + int flags; /* BP_* */ + QTAILQ_ENTRY(CPUWatchpoint) entry; +}; + /* * struct SysemuCPUOps: System operations specific to a CPU class */ @@ -86,4 +95,150 @@ typedef struct SysemuCPUOps { const VMStateDescription *vmsd; } SysemuCPUOps; =20 +/** + * cpu_paging_enabled: + * @cpu: The CPU whose state is to be inspected. + * + * Returns: %true if paging is enabled, %false otherwise. + */ +bool cpu_paging_enabled(const CPUState *cpu); + +/** + * cpu_get_memory_mapping: + * @cpu: The CPU whose memory mappings are to be obtained. + * @list: Where to write the memory mappings to. + * @errp: Pointer for reporting an #Error. + */ +void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, + Error **errp); + +/** + * cpu_write_elf64_note: + * @f: pointer to a function that writes memory to a file + * @cpu: The CPU whose memory is to be dumped + * @cpuid: ID number of the CPU + * @opaque: pointer to the CPUState struct + */ +int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + +/** + * cpu_write_elf64_qemunote: + * @f: pointer to a function that writes memory to a file + * @cpu: The CPU whose memory is to be dumped + * @cpuid: ID number of the CPU + * @opaque: pointer to the CPUState struct + */ +int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + +/** + * cpu_write_elf32_note: + * @f: pointer to a function that writes memory to a file + * @cpu: The CPU whose memory is to be dumped + * @cpuid: ID number of the CPU + * @opaque: pointer to the CPUState struct + */ +int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + +/** + * cpu_write_elf32_qemunote: + * @f: pointer to a function that writes memory to a file + * @cpu: The CPU whose memory is to be dumped + * @cpuid: ID number of the CPU + * @opaque: pointer to the CPUState struct + */ +int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + +/** + * cpu_get_crash_info: + * @cpu: The CPU to get crash information for + * + * Gets the previously saved crash information. + * Caller is responsible for freeing the data. + */ +GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); + +/** + * cpu_get_phys_page_attrs_debug: + * @cpu: The CPU to obtain the physical page address for. + * @addr: The virtual address. + * @attrs: Updated on return with the memory transaction attributes to use + * for this access. + * + * Obtains the physical page corresponding to a virtual one, together + * with the corresponding memory transaction attributes to use for the acc= ess. + * Use it only for debugging because no protection checks are done. + * + * Returns: Corresponding physical page address or -1 if no page found. + */ +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); + +/** + * cpu_get_phys_page_debug: + * @cpu: The CPU to obtain the physical page address for. + * @addr: The virtual address. + * + * Obtains the physical page corresponding to a virtual one. + * Use it only for debugging because no protection checks are done. + * + * Returns: Corresponding physical page address or -1 if no page found. + */ +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + +/** + * cpu_asidx_from_attrs: + * @cpu: CPU + * @attrs: memory transaction attributes + * + * Returns the address space index specifying the CPU AddressSpace + * to use for a memory access with the given transaction attributes. + */ +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); + +/** + * cpu_virtio_is_big_endian: + * @cpu: CPU + + * Returns %true if a CPU which supports runtime configurable endianness + * is currently big-endian. + */ +bool cpu_virtio_is_big_endian(CPUState *cpu); + +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, + int flags, CPUWatchpoint **watchpoint); +int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, + vaddr len, int flags); +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint= ); +void cpu_watchpoint_remove_all(CPUState *cpu, int mask); + +/** + * cpu_check_watchpoint: + * @cpu: cpu context + * @addr: guest virtual address + * @len: access length + * @attrs: memory access attributes + * @flags: watchpoint access type + * @ra: unwind return address + * + * Check for a watchpoint hit in [addr, addr+len) of the type + * specified by @flags. Exit via exception with a hit. + */ +void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, + MemTxAttrs attrs, int flags, uintptr_t ra); + +/** + * cpu_watchpoint_address_matches: + * @cpu: cpu context + * @addr: guest virtual address + * @len: access length + * + * Return the watchpoint flags that apply to [addr, addr+len). + * If no watchpoint is registered for the range, the result is 0. + */ +int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); + #endif /* SYSEMU_CPU_OPS_H */ diff --git a/gdbstub.c b/gdbstub.c index f3614ebcc7a..0bc609fbf24 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -41,6 +41,7 @@ #include "exec/gdbstub.h" #include "hw/cpu/cluster.h" #include "hw/boards.h" +#include "hw/core/sysemu-cpu-ops.h" #endif =20 #define MAX_PACKET_LENGTH 4096 diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 19e0aa9836a..00e9729fa8a 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -28,6 +28,7 @@ #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ +#include "hw/core/sysemu-cpu-ops.h" =20 #include "exec/exec-all.h" #include "exec/target_page.h" --=20 2.26.2