From nobody Fri May 17 07:47:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614779747; cv=none; d=zohomail.com; s=zohoarc; b=V2rjmz+GtTPutHYLPgXTiUPlb8lL6kXtW0bapt7aocaN/CxwwtzoBcdcMH5fXQlAT2FH619osGdpe7JZ/L07yrh5fw2omxvXnqnPcKiMEGQy7kze90/QMRvjxX4aq41jSiasnSf3DDKpvUKbJ6U7QyrLHGb8p20aWI6LREVMl30= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614779747; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wKeK8GP/rmQ+3iN7LvLEbnwQyfX24U4AdlKPJNnKGSo=; b=c7RXrnFhiUAq9ahvZiu2xdiFLnOqq+UpB6EfCV6ib3AWoCc2DDp9s5kik0vSUCfnNBzZ4UipVlMr46xF9eIh7hYC+JOH4JKoqxJb22+4M9VbdzSUCQALbMsAmKrjU4otAI0XlqXz+VidjLyCW3RKSkfIZV+eFFPtetb7Uv9DkNs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614779747280407.432647672902; Wed, 3 Mar 2021 05:55:47 -0800 (PST) Received: from localhost ([::1]:41580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHRyc-0006wI-5L for importer@patchew.org; Wed, 03 Mar 2021 08:55:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHRwM-0005JI-PD; Wed, 03 Mar 2021 08:53:27 -0500 Received: from mail-qk1-x72b.google.com ([2607:f8b0:4864:20::72b]:38263) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHRwJ-0002AL-EB; Wed, 03 Mar 2021 08:53:26 -0500 Received: by mail-qk1-x72b.google.com with SMTP id f124so5774554qkj.5; Wed, 03 Mar 2021 05:53:22 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id x187sm17425500qkd.83.2021.03.03.05.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 05:53:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wKeK8GP/rmQ+3iN7LvLEbnwQyfX24U4AdlKPJNnKGSo=; b=CuvWhUnLutoEsknDlOdDbMKgI0EQLb2rdd7soyTEBI10eetO/npyTJv5w5kQrlULzR bm2ybhwFNv1vt8li5XaTwmNyk1c6T4L5v2S29FV8r/z4KqM/z3bf4h62OHjwDYlYvia5 taklGkLFK9FSRDcenH6EJyZe7CSpoSH3pBYxZuk5z7o3B0g4HnbrJUeu7MKt2lBwQueS Zy5URr2xi6gMNSSICkl0s+N8gi9Oy6PHeydwnXDKvlAmtrkMVBn10mBEjLnH3Z0Ipmb7 1VOlLR730Okg6WybPC01IcGuoE75469xlB4ci11idaV9C1oYjPB6TZTZ6eNm5OADI4q/ cL/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wKeK8GP/rmQ+3iN7LvLEbnwQyfX24U4AdlKPJNnKGSo=; b=B0cock/S7L4twLvtAXcA09pTic1Y363+Aqm4u2/dul9PBCP0eQq/yhXjAYpNK0OjuO 7Zt9T6v4+cxoWPEJ5yV6R+HLwoKhva+Wms16w+TJBUvd0KOQwfn9tq1onUbLGBCrk38d yVV1Vaw82yQhSeGHZoUvc8HzM/GnvP9k+NhDq0EjrJsjUNt/ON4KrsoGFxRHQeQle1Tq nqXljKNnY0VPumEKdE2rt1WUKP1eEW4BRaeBRGDyuUl97OAKYaIGfv7qDMl8t4H0lfve B1ZT0UPOEoRB+HaLBSrAuHk3qUqn3Dyn0IaXIzTsVGMq9oXThyK/JzD5fQFMIBsoKmXS 06xA== X-Gm-Message-State: AOAM530DTSrpklTH5+L0nsLWySqaL7Z8mNni2peCIZDkjzX1udfFgJP3 sR8PF+nJoH1JJbKen6QQNKg= X-Google-Smtp-Source: ABdhPJyb6ugjvBmvhlahqUw7wFC22WYoTNJTXnj4QZDpH40Ei2SX/RUJ2oo7RRYqD+lXyNDQf/qF8Q== X-Received: by 2002:a37:7ac7:: with SMTP id v190mr25427015qkc.373.1614779602047; Wed, 03 Mar 2021 05:53:22 -0800 (PST) From: Bin Meng To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell Subject: [PATCH v7 1/5] hw/dma: Implement a Xilinx CSU DMA model Date: Wed, 3 Mar 2021 21:52:50 +0800 Message-Id: <20210303135254.3970-2-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210303135254.3970-1-bmeng.cn@gmail.com> References: <20210303135254.3970-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=bmeng.cn@gmail.com; helo=mail-qk1-x72b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Xuzhou Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Xuzhou Cheng ZynqMP QSPI supports SPI transfer using DMA mode, but currently this is unimplemented. When QSPI is programmed to use DMA mode, QEMU will crash. This is observed when testing VxWorks 7. This adds a Xilinx CSU DMA model and the implementation is based on https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c. The DST part of the model is verified along with ZynqMP GQSPI model. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Tested-by: Edgar E. Iglesias Reviewed-by: Edgar E. Iglesias --- Changes in v7: - merge the diffs from Edgar Changes in v6: - int_enable and int_disable do not have its own state - return 0 in int_enable_pre_write() and int_disable_pre_write() - remove XLNX_CSU_DMA_INT_R_MASK in int_status_pre_write() Changes in v5: - int_enable and int_disable do not affect each other - do not modify int_status int_disable_pre_write - set MEM_DONE in xlnx_csu_dma_done if it's SRC Changes in v4: - Add complete CSU DMA model based on Edgar's branch - Differences with Edgar's branch: 1. Match the registers' FIELD to UG1807. 2. Remove "byte-align" property. Per UG1807, SIZE and ADDR registers must be word aligned. 3. Make the values of int_enable and int_disable mutually exclusive otherwise IRQ cannot be delivered. 4. Clear int_status after int_disable is set. 5. Coding convention issues clean-up Changes in v3: - Implement DMA as a separate CSU DMA model Changes in v2: - Remove unconnected TYPE_STREAM_SINK link property - Add a TYPE_MEMORY_REGION link property, to allow board codes to tell the device what its view of the world that it is doing DMA to is - Replace cpu_physical_memory_write() with address_space_write() include/hw/dma/xlnx_csu_dma.h | 52 +++ hw/dma/xlnx_csu_dma.c | 745 ++++++++++++++++++++++++++++++++++ hw/dma/Kconfig | 4 + hw/dma/meson.build | 1 + 4 files changed, 802 insertions(+) create mode 100644 include/hw/dma/xlnx_csu_dma.h create mode 100644 hw/dma/xlnx_csu_dma.c diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h new file mode 100644 index 0000000000..204d94c673 --- /dev/null +++ b/include/hw/dma/xlnx_csu_dma.h @@ -0,0 +1,52 @@ +/* + * Xilinx Platform CSU Stream DMA emulation + * + * This implementation is based on + * https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef XLNX_CSU_DMA_H +#define XLNX_CSU_DMA_H + +#define TYPE_XLNX_CSU_DMA "xlnx.csu_dma" + +#define XLNX_CSU_DMA_R_MAX (0x2c / 4) + +typedef struct XlnxCSUDMA { + SysBusDevice busdev; + MemoryRegion iomem; + MemTxAttrs attr; + MemoryRegion *dma_mr; + AddressSpace *dma_as; + qemu_irq irq; + StreamSink *tx_dev; /* Used as generic StreamSink */ + ptimer_state *src_timer; + + uint16_t width; + bool is_dst; + bool r_size_last_word; + + StreamCanPushNotifyFn notify; + void *notify_opaque; + + uint32_t regs[XLNX_CSU_DMA_R_MAX]; + RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX]; +} XlnxCSUDMA; + +#define XLNX_CSU_DMA(obj) \ + OBJECT_CHECK(XlnxCSUDMA, (obj), TYPE_XLNX_CSU_DMA) + +#endif diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c new file mode 100644 index 0000000000..50709a3909 --- /dev/null +++ b/hw/dma/xlnx_csu_dma.c @@ -0,0 +1,745 @@ +/* + * Xilinx Platform CSU Stream DMA emulation + * + * This implementation is based on + * https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "sysemu/dma.h" +#include "hw/ptimer.h" +#include "hw/stream.h" +#include "hw/register.h" +#include "hw/dma/xlnx_csu_dma.h" + +/* + * Ref: UG1087 (v1.7) February 8, 2019 + * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascal= e-registers.html + * CSUDMA Module section + */ +REG32(ADDR, 0x0) + FIELD(ADDR, ADDR, 2, 30) /* wo */ +REG32(SIZE, 0x4) + FIELD(SIZE, SIZE, 2, 27) /* wo */ + FIELD(SIZE, LAST_WORD, 0, 1) /* rw, only exists in SRC */ +REG32(STATUS, 0x8) + FIELD(STATUS, DONE_CNT, 13, 3) /* wtc */ + FIELD(STATUS, FIFO_LEVEL, 5, 8) /* ro */ + FIELD(STATUS, OUTSTANDING, 1, 4) /* ro */ + FIELD(STATUS, BUSY, 0, 1) /* ro */ +REG32(CTRL, 0xc) + FIELD(CTRL, FIFOTHRESH, 25, 7) /* rw, only exists in DST, reset 0x40 */ + FIELD(CTRL, APB_ERR_RESP, 24, 1) /* rw */ + FIELD(CTRL, ENDIANNESS, 23, 1) /* rw */ + FIELD(CTRL, AXI_BRST_TYPE, 22, 1) /* rw */ + FIELD(CTRL, TIMEOUT_VAL, 10, 12) /* rw, reset: 0xFFE */ + FIELD(CTRL, FIFO_THRESH, 2, 8) /* rw, reset: 0x80 */ + FIELD(CTRL, PAUSE_STRM, 1, 1) /* rw */ + FIELD(CTRL, PAUSE_MEM, 0, 1) /* rw */ +REG32(CRC, 0x10) +REG32(INT_STATUS, 0x14) + FIELD(INT_STATUS, FIFO_OVERFLOW, 7, 1) /* wtc */ + FIELD(INT_STATUS, INVALID_APB, 6, 1) /* wtc */ + FIELD(INT_STATUS, THRESH_HIT, 5, 1) /* wtc */ + FIELD(INT_STATUS, TIMEOUT_MEM, 4, 1) /* wtc */ + FIELD(INT_STATUS, TIMEOUT_STRM, 3, 1) /* wtc */ + FIELD(INT_STATUS, AXI_BRESP_ERR, 2, 1) /* wtc, SRC: AXI_RDERR */ + FIELD(INT_STATUS, DONE, 1, 1) /* wtc */ + FIELD(INT_STATUS, MEM_DONE, 0, 1) /* wtc */ +REG32(INT_ENABLE, 0x18) + FIELD(INT_ENABLE, FIFO_OVERFLOW, 7, 1) /* wtc */ + FIELD(INT_ENABLE, INVALID_APB, 6, 1) /* wtc */ + FIELD(INT_ENABLE, THRESH_HIT, 5, 1) /* wtc */ + FIELD(INT_ENABLE, TIMEOUT_MEM, 4, 1) /* wtc */ + FIELD(INT_ENABLE, TIMEOUT_STRM, 3, 1) /* wtc */ + FIELD(INT_ENABLE, AXI_BRESP_ERR, 2, 1) /* wtc, SRC: AXI_RDERR */ + FIELD(INT_ENABLE, DONE, 1, 1) /* wtc */ + FIELD(INT_ENABLE, MEM_DONE, 0, 1) /* wtc */ +REG32(INT_DISABLE, 0x1c) + FIELD(INT_DISABLE, FIFO_OVERFLOW, 7, 1) /* wtc */ + FIELD(INT_DISABLE, INVALID_APB, 6, 1) /* wtc */ + FIELD(INT_DISABLE, THRESH_HIT, 5, 1) /* wtc */ + FIELD(INT_DISABLE, TIMEOUT_MEM, 4, 1) /* wtc */ + FIELD(INT_DISABLE, TIMEOUT_STRM, 3, 1) /* wtc */ + FIELD(INT_DISABLE, AXI_BRESP_ERR, 2, 1) /* wtc, SRC: AXI_RDERR */ + FIELD(INT_DISABLE, DONE, 1, 1) /* wtc */ + FIELD(INT_DISABLE, MEM_DONE, 0, 1) /* wtc */ +REG32(INT_MASK, 0x20) + FIELD(INT_MASK, FIFO_OVERFLOW, 7, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, INVALID_APB, 6, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, THRESH_HIT, 5, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, TIMEOUT_MEM, 4, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, TIMEOUT_STRM, 3, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, AXI_BRESP_ERR, 2, 1) /* ro, reset: 0x1, SRC: AXI_RDERR= */ + FIELD(INT_MASK, DONE, 1, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, MEM_DONE, 0, 1) /* ro, reset: 0x1 */ +REG32(CTRL2, 0x24) + FIELD(CTRL2, ARCACHE, 24, 3) /* rw */ + FIELD(CTRL2, ROUTE_BIT, 23, 1) /* rw */ + FIELD(CTRL2, TIMEOUT_EN, 22, 1) /* rw */ + FIELD(CTRL2, TIMEOUT_PRE, 4, 12) /* rw, reset: 0xFFF */ + FIELD(CTRL2, MAX_OUTS_CMDS, 0, 4) /* rw, reset: 0x8 */ +REG32(ADDR_MSB, 0x28) + FIELD(ADDR_MSB, ADDR_MSB, 0, 17) /* wo */ + +#define R_CTRL_TIMEOUT_VAL_RESET (0xFFE) +#define R_CTRL_FIFO_THRESH_RESET (0x80) +#define R_CTRL_FIFOTHRESH_RESET (0x40) + +#define R_CTRL2_TIMEOUT_PRE_RESET (0xFFF) +#define R_CTRL2_MAX_OUTS_CMDS_RESET (0x8) + +#define XLNX_CSU_DMA_ERR_DEBUG (0) +#define XLNX_CSU_DMA_INT_R_MASK (0xff) + +/* UG1807: Set the prescaler value for the timeout in clk (~2.5ns) cycles = */ +#define XLNX_CSU_DMA_TIMER_FREQ (400 * 1000 * 1000) + +static bool xlnx_csu_dma_is_paused(XlnxCSUDMA *s) +{ + bool paused; + + paused =3D !!(s->regs[R_CTRL] & R_CTRL_PAUSE_STRM_MASK); + paused |=3D !!(s->regs[R_CTRL] & R_CTRL_PAUSE_MEM_MASK); + + return paused; +} + +static bool xlnx_csu_dma_get_eop(XlnxCSUDMA *s) +{ + return s->r_size_last_word; +} + +static bool xlnx_csu_dma_burst_is_fixed(XlnxCSUDMA *s) +{ + return !!(s->regs[R_CTRL] & R_CTRL_AXI_BRST_TYPE_MASK); +} + +static bool xlnx_csu_dma_timeout_enabled(XlnxCSUDMA *s) +{ + return !!(s->regs[R_CTRL2] & R_CTRL2_TIMEOUT_EN_MASK); +} + +static void xlnx_csu_dma_update_done_cnt(XlnxCSUDMA *s, int a) +{ + int cnt; + + /* Increase DONE_CNT */ + cnt =3D ARRAY_FIELD_EX32(s->regs, STATUS, DONE_CNT) + a; + ARRAY_FIELD_DP32(s->regs, STATUS, DONE_CNT, cnt); +} + +static void xlnx_csu_dma_data_process(XlnxCSUDMA *s, uint8_t *buf, uint32_= t len) +{ + uint32_t bswap; + uint32_t i; + + bswap =3D s->regs[R_CTRL] & R_CTRL_ENDIANNESS_MASK; + if (s->is_dst && !bswap) { + /* Fast when ENDIANNESS cleared */ + return; + } + + for (i =3D 0; i < len; i +=3D 4) { + uint8_t *b =3D &buf[i]; + union { + uint8_t u8[4]; + uint32_t u32; + } v =3D { + .u8 =3D { b[0], b[1], b[2], b[3] } + }; + + if (!s->is_dst) { + s->regs[R_CRC] +=3D v.u32; + } + if (bswap) { + /* + * No point using bswap, we need to writeback + * into a potentially unaligned pointer. + */ + b[0] =3D v.u8[3]; + b[1] =3D v.u8[2]; + b[2] =3D v.u8[1]; + b[3] =3D v.u8[0]; + } + } +} + +static void xlnx_csu_dma_update_irq(XlnxCSUDMA *s) +{ + qemu_set_irq(s->irq, !!(s->regs[R_INT_STATUS] & ~s->regs[R_INT_MASK])); +} + +/* len is in bytes */ +static uint32_t xlnx_csu_dma_read(XlnxCSUDMA *s, uint8_t *buf, uint32_t le= n) +{ + hwaddr addr =3D (hwaddr)s->regs[R_ADDR_MSB] << 32 | s->regs[R_ADDR]; + MemTxResult result =3D MEMTX_OK; + + if (xlnx_csu_dma_burst_is_fixed(s)) { + uint32_t i; + + for (i =3D 0; i < len && (result =3D=3D MEMTX_OK); i +=3D s->width= ) { + uint32_t mlen =3D MIN(len - i, s->width); + + result =3D address_space_rw(s->dma_as, addr, s->attr, + buf + i, mlen, false); + } + } else { + result =3D address_space_rw(s->dma_as, addr, s->attr, buf, len, fa= lse); + } + + if (result =3D=3D MEMTX_OK) { + xlnx_csu_dma_data_process(s, buf, len); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%lx for mem read= ", + __func__, addr); + s->regs[R_INT_STATUS] |=3D R_INT_STATUS_AXI_BRESP_ERR_MASK; + xlnx_csu_dma_update_irq(s); + } + return len; +} + +/* len is in bytes */ +static uint32_t xlnx_csu_dma_write(XlnxCSUDMA *s, uint8_t *buf, uint32_t l= en) +{ + hwaddr addr =3D (hwaddr)s->regs[R_ADDR_MSB] << 32 | s->regs[R_ADDR]; + MemTxResult result =3D MEMTX_OK; + + xlnx_csu_dma_data_process(s, buf, len); + if (xlnx_csu_dma_burst_is_fixed(s)) { + uint32_t i; + + for (i =3D 0; i < len && (result =3D=3D MEMTX_OK); i +=3D s->width= ) { + uint32_t mlen =3D MIN(len - i, s->width); + + result =3D address_space_rw(s->dma_as, addr, s->attr, + buf, mlen, true); + buf +=3D mlen; + } + } else { + result =3D address_space_rw(s->dma_as, addr, s->attr, buf, len, tr= ue); + } + + if (result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%lx for mem writ= e", + __func__, addr); + s->regs[R_INT_STATUS] |=3D R_INT_STATUS_AXI_BRESP_ERR_MASK; + xlnx_csu_dma_update_irq(s); + } + return len; +} + +static void xlnx_csu_dma_done(XlnxCSUDMA *s) +{ + s->regs[R_STATUS] &=3D ~R_STATUS_BUSY_MASK; + s->regs[R_INT_STATUS] |=3D R_INT_STATUS_DONE_MASK; + + if (!s->is_dst) { + s->regs[R_INT_STATUS] |=3D R_INT_STATUS_MEM_DONE_MASK; + } + + xlnx_csu_dma_update_done_cnt(s, 1); +} + +static uint32_t xlnx_csu_dma_advance(XlnxCSUDMA *s, uint32_t len) +{ + uint32_t size =3D s->regs[R_SIZE]; + hwaddr dst =3D (hwaddr)s->regs[R_ADDR_MSB] << 32 | s->regs[R_ADDR]; + + assert(len <=3D size); + + size -=3D len; + s->regs[R_SIZE] =3D size; + + if (!xlnx_csu_dma_burst_is_fixed(s)) { + dst +=3D len; + s->regs[R_ADDR] =3D (uint32_t) dst; + s->regs[R_ADDR_MSB] =3D dst >> 32; + } + + if (size =3D=3D 0) { + xlnx_csu_dma_done(s); + } + + return size; +} + +static void xlnx_csu_dma_src_notify(void *opaque) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(opaque); + unsigned char buf[4 * 1024]; + size_t rlen =3D 0; + + ptimer_transaction_begin(s->src_timer); + /* Stop the backpreassure timer */ + ptimer_stop(s->src_timer); + + while (s->regs[R_SIZE] && !xlnx_csu_dma_is_paused(s) && + stream_can_push(s->tx_dev, xlnx_csu_dma_src_notify, s)) { + uint32_t plen =3D MIN(s->regs[R_SIZE], sizeof buf); + bool eop =3D false; + + /* Did we fit it all? */ + if (s->regs[R_SIZE] =3D=3D plen && xlnx_csu_dma_get_eop(s)) { + eop =3D true; + } + + /* DMA transfer */ + xlnx_csu_dma_read(s, buf, plen); + rlen =3D stream_push(s->tx_dev, buf, plen, eop); + xlnx_csu_dma_advance(s, rlen); + } + + if (xlnx_csu_dma_timeout_enabled(s) && s->regs[R_SIZE] && + !stream_can_push(s->tx_dev, xlnx_csu_dma_src_notify, s)) { + uint32_t timeout =3D ARRAY_FIELD_EX32(s->regs, CTRL, TIMEOUT_VAL); + uint32_t div =3D ARRAY_FIELD_EX32(s->regs, CTRL2, TIMEOUT_PRE) + 1; + uint32_t freq =3D XLNX_CSU_DMA_TIMER_FREQ; + + freq /=3D div; + ptimer_set_freq(s->src_timer, freq); + ptimer_set_count(s->src_timer, timeout); + ptimer_run(s->src_timer, 1); + } + + ptimer_transaction_commit(s->src_timer); + xlnx_csu_dma_update_irq(s); +} + +static uint64_t addr_pre_write(RegisterInfo *reg, uint64_t val) +{ + /* Address is word aligned */ + return val & R_ADDR_ADDR_MASK; +} + +static uint64_t size_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + if (s->regs[R_SIZE] !=3D 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Starting DMA while already running.\n", __func_= _); + } + + if (!s->is_dst) { + s->r_size_last_word =3D !!(val & R_SIZE_LAST_WORD_MASK); + } + + /* Size is word aligned */ + return val & R_SIZE_SIZE_MASK; +} + +static uint64_t size_post_read(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + return val | s->r_size_last_word; +} + +static void size_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + s->regs[R_STATUS] |=3D R_STATUS_BUSY_MASK; + + /* + * Note that if SIZE is programmed to 0, and the DMA is started, + * the interrupts DONE and MEM_DONE will be asserted. + */ + if (s->regs[R_SIZE] =3D=3D 0) { + xlnx_csu_dma_done(s); + xlnx_csu_dma_update_irq(s); + return; + } + + /* Set SIZE is considered the last step in transfer configuration */ + if (!s->is_dst) { + xlnx_csu_dma_src_notify(s); + } else { + if (s->notify) { + s->notify(s->notify_opaque); + } + } +} + +static uint64_t status_pre_write(RegisterInfo *reg, uint64_t val) +{ + return val & (R_STATUS_DONE_CNT_MASK | R_STATUS_BUSY_MASK); +} + +static void ctrl_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + if (!s->is_dst) { + if (!xlnx_csu_dma_is_paused(s)) { + xlnx_csu_dma_src_notify(s); + } + } else { + if (!xlnx_csu_dma_is_paused(s) && s->notify) { + s->notify(s->notify_opaque); + } + } +} + +static uint64_t int_status_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + /* DMA counter decrements when flag 'DONE' is cleared */ + if ((val & s->regs[R_INT_STATUS] & R_INT_STATUS_DONE_MASK)) { + xlnx_csu_dma_update_done_cnt(s, -1); + } + + return s->regs[R_INT_STATUS] & ~val; +} + +static void int_status_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + xlnx_csu_dma_update_irq(s); +} + +static uint64_t int_enable_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + uint32_t v32 =3D val; + + /* + * R_INT_ENABLE doesn't have its own state. + * It is used to indirectly modify R_INT_MASK. + * + * 1: Enable this interrupt field (the mask bit will be cleared to 0) + * 0: No effect + */ + s->regs[R_INT_MASK] &=3D ~v32; + return 0; +} + +static void int_enable_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + xlnx_csu_dma_update_irq(s); +} + +static uint64_t int_disable_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + uint32_t v32 =3D val; + + /* + * R_INT_DISABLE doesn't have its own state. + * It is used to indirectly modify R_INT_MASK. + * + * 1: Disable this interrupt field (the mask bit will be set to 1) + * 0: No effect + */ + s->regs[R_INT_MASK] |=3D v32; + return 0; +} + +static void int_disable_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + xlnx_csu_dma_update_irq(s); +} + +static uint64_t addr_msb_pre_write(RegisterInfo *reg, uint64_t val) +{ + return val & R_ADDR_MSB_ADDR_MSB_MASK; +} + +static const RegisterAccessInfo *xlnx_csu_dma_regs_info[] =3D { +#define DMACH_REGINFO(NAME, snd) = \ + (const RegisterAccessInfo []) { = \ + { = \ + .name =3D #NAME "_ADDR", = \ + .addr =3D A_ADDR, = \ + .pre_write =3D addr_pre_write = \ + }, { = \ + .name =3D #NAME "_SIZE", = \ + .addr =3D A_SIZE, = \ + .pre_write =3D size_pre_write, = \ + .post_write =3D size_post_write, = \ + .post_read =3D size_post_read = \ + }, { = \ + .name =3D #NAME "_STATUS", = \ + .addr =3D A_STATUS, = \ + .pre_write =3D status_pre_write, = \ + .w1c =3D R_STATUS_DONE_CNT_MASK, = \ + .ro =3D (R_STATUS_BUSY_MASK = \ + | R_STATUS_FIFO_LEVEL_MASK = \ + | R_STATUS_OUTSTANDING_MASK) = \ + }, { = \ + .name =3D #NAME "_CTRL", = \ + .addr =3D A_CTRL, = \ + .post_write =3D ctrl_post_write, = \ + .reset =3D ((R_CTRL_TIMEOUT_VAL_RESET << R_CTRL_TIMEOUT_VAL_SH= IFT) \ + | (R_CTRL_FIFO_THRESH_RESET << R_CTRL_FIFO_THRESH_SH= IFT)\ + | (snd ? 0 : R_CTRL_FIFOTHRESH_RESET = \ + << R_CTRL_FIFOTHRESH_SHIFT)) = \ + }, { = \ + .name =3D #NAME "_CRC", = \ + .addr =3D A_CRC, = \ + }, { = \ + .name =3D #NAME "_INT_STATUS", = \ + .addr =3D A_INT_STATUS, = \ + .pre_write =3D int_status_pre_write, = \ + .post_write =3D int_status_post_write = \ + }, { = \ + .name =3D #NAME "_INT_ENABLE", = \ + .addr =3D A_INT_ENABLE, = \ + .pre_write =3D int_enable_pre_write, = \ + .post_write =3D int_enable_post_write = \ + }, { = \ + .name =3D #NAME "_INT_DISABLE", = \ + .addr =3D A_INT_DISABLE, = \ + .pre_write =3D int_disable_pre_write, = \ + .post_write =3D int_disable_post_write = \ + }, { = \ + .name =3D #NAME "_INT_MASK", = \ + .addr =3D A_INT_MASK, = \ + .ro =3D ~0, = \ + .reset =3D XLNX_CSU_DMA_INT_R_MASK = \ + }, { = \ + .name =3D #NAME "_CTRL2", = \ + .addr =3D A_CTRL2, = \ + .reset =3D ((R_CTRL2_TIMEOUT_PRE_RESET = \ + << R_CTRL2_TIMEOUT_PRE_SHIFT) = \ + | (R_CTRL2_MAX_OUTS_CMDS_RESET = \ + << R_CTRL2_MAX_OUTS_CMDS_SHIFT)) = \ + }, { = \ + .name =3D #NAME "_ADDR_MSB", = \ + .addr =3D A_ADDR_MSB, = \ + .pre_write =3D addr_msb_pre_write = \ + } = \ + } + + DMACH_REGINFO(DMA_SRC, true), + DMACH_REGINFO(DMA_DST, false) +}; + +static const MemoryRegionOps xlnx_csu_dma_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + } +}; + +static void xlnx_csu_dma_src_timeout_hit(void *opaque) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(opaque); + + /* Ignore if the timeout is masked */ + if (!xlnx_csu_dma_timeout_enabled(s)) { + return; + } + + s->regs[R_INT_STATUS] |=3D R_INT_STATUS_TIMEOUT_STRM_MASK; + xlnx_csu_dma_update_irq(s); +} + +static size_t xlnx_csu_dma_stream_push(StreamSink *obj, uint8_t *buf, + size_t len, bool eop) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(obj); + uint32_t size =3D s->regs[R_SIZE]; + uint32_t mlen =3D MIN(size, len) & (~3); /* Size is word aligned */ + + /* Be called when it's DST */ + assert(s->is_dst); + + if (size =3D=3D 0 || len <=3D 0) { + return 0; + } + + if (len && (xlnx_csu_dma_is_paused(s) || mlen =3D=3D 0)) { + qemu_log_mask(LOG_GUEST_ERROR, + "csu-dma: DST channel dropping %zd b of data.\n", le= n); + s->regs[R_INT_STATUS] |=3D R_INT_STATUS_FIFO_OVERFLOW_MASK; + return len; + } + + if (xlnx_csu_dma_write(s, buf, mlen) !=3D mlen) { + return 0; + } + + xlnx_csu_dma_advance(s, mlen); + xlnx_csu_dma_update_irq(s); + + return mlen; +} + +static bool xlnx_csu_dma_stream_can_push(StreamSink *obj, + StreamCanPushNotifyFn notify, + void *notify_opaque) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(obj); + + if (s->regs[R_SIZE] !=3D 0) { + return true; + } else { + s->notify =3D notify; + s->notify_opaque =3D notify_opaque; + return false; + } +} + +static void xlnx_csu_dma_reset(DeviceState *dev) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(dev); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void xlnx_csu_dma_realize(DeviceState *dev, Error **errp) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(dev); + RegisterInfoArray *reg_array; + + reg_array =3D + register_init_block32(dev, xlnx_csu_dma_regs_info[!!s->is_dst], + XLNX_CSU_DMA_R_MAX, + s->regs_info, s->regs, + &xlnx_csu_dma_ops, + XLNX_CSU_DMA_ERR_DEBUG, + XLNX_CSU_DMA_R_MAX * 4); + memory_region_add_subregion(&s->iomem, + 0x0, + ®_array->mem); + + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); + + if (!s->is_dst && !s->tx_dev) { + error_setg(errp, "zynqmp.csu-dma: Stream not connected"); + return; + } + + s->src_timer =3D ptimer_init(xlnx_csu_dma_src_timeout_hit, + s, PTIMER_POLICY_DEFAULT); + + if (s->dma_mr) { + s->dma_as =3D g_malloc0(sizeof(AddressSpace)); + address_space_init(s->dma_as, s->dma_mr, NULL); + } else { + s->dma_as =3D &address_space_memory; + } + + s->attr =3D MEMTXATTRS_UNSPECIFIED; + + s->r_size_last_word =3D 0; +} + +static const VMStateDescription vmstate_xlnx_csu_dma =3D { + .name =3D TYPE_XLNX_CSU_DMA, + .version_id =3D 0, + .minimum_version_id =3D 0, + .minimum_version_id_old =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_PTIMER(src_timer, XlnxCSUDMA), + VMSTATE_UINT16(width, XlnxCSUDMA), + VMSTATE_BOOL(is_dst, XlnxCSUDMA), + VMSTATE_BOOL(r_size_last_word, XlnxCSUDMA), + VMSTATE_UINT32_ARRAY(regs, XlnxCSUDMA, XLNX_CSU_DMA_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static Property xlnx_csu_dma_properties[] =3D { + /* + * Ref PG021, Stream Data Width: + * Data width in bits of the AXI S2MM AXI4-Stream Data bus. + * This value must be equal or less than the Memory Map Data Width. + * Valid values are 8, 16, 32, 64, 128, 512 and 1024. + * "dma-width" is the byte value of the "Stream Data Width". + */ + DEFINE_PROP_UINT16("dma-width", XlnxCSUDMA, width, 4), + /* + * The CSU DMA is a two-channel, simple DMA, allowing separate control= of + * the SRC (read) channel and DST (write) channel. "is-dst" is used to= mark + * which channel the device is connected to. + */ + DEFINE_PROP_BOOL("is-dst", XlnxCSUDMA, is_dst, true), + DEFINE_PROP_END_OF_LIST(), +}; + +static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + StreamSinkClass *ssc =3D STREAM_SINK_CLASS(klass); + + dc->reset =3D xlnx_csu_dma_reset; + dc->realize =3D xlnx_csu_dma_realize; + dc->vmsd =3D &vmstate_xlnx_csu_dma; + device_class_set_props(dc, xlnx_csu_dma_properties); + + ssc->push =3D xlnx_csu_dma_stream_push; + ssc->can_push =3D xlnx_csu_dma_stream_can_push; +} + +static void xlnx_csu_dma_init(Object *obj) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(obj); + + memory_region_init(&s->iomem, obj, TYPE_XLNX_CSU_DMA, + XLNX_CSU_DMA_R_MAX * 4); + + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK, + (Object **)&s->tx_dev, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, + (Object **)&s->dma_mr, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); +} + +static const TypeInfo xlnx_csu_dma_info =3D { + .name =3D TYPE_XLNX_CSU_DMA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(XlnxCSUDMA), + .class_init =3D xlnx_csu_dma_class_init, + .instance_init =3D xlnx_csu_dma_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_STREAM_SINK }, + { } + } +}; + +static void xlnx_csu_dma_register_types(void) +{ + type_register_static(&xlnx_csu_dma_info); +} + +type_init(xlnx_csu_dma_register_types) diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig index 5d6be1a7a7..98fbb1bb04 100644 --- a/hw/dma/Kconfig +++ b/hw/dma/Kconfig @@ -26,3 +26,7 @@ config STP2000 =20 config SIFIVE_PDMA bool + +config XLNX_CSU_DMA + bool + select REGISTER diff --git a/hw/dma/meson.build b/hw/dma/meson.build index 47b4a7cb47..5c78a4e05f 100644 --- a/hw/dma/meson.build +++ b/hw/dma/meson.build @@ -14,3 +14,4 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_= dma.c', 'soc_dma.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_CSU_DMA', if_true: files('xlnx_csu_dma.c= ')) --=20 2.25.1 From nobody Fri May 17 07:47:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614779864; cv=none; d=zohomail.com; s=zohoarc; b=IlMAAv+Pi1Uygt/0rLXD+3pD+RvZz6SkHHnk2TafPzT948y2KOPfpBhItiGw0gsX/uqTkrJJMpPrf+iWjpggMXAVCpcMtM5hXZrFMw4ajkzcVVUCvM76NinQseRN3BikI9mAFqs8ZkgH0r1YokvzkwKl7NM44ldSmlWCToUx/Ms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614779864; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QdPd6+T9TYulDYan4MqsgMWZ2nXNjoGfebenRUzAWpA=; b=ZfCi0iJ5fK/PUmae+feTrKHDA6YaJleYrr+dbyWmd8Xe462U6ZLNvABYfoFpnwVo+nIRy8SFdg65C3cC4xaPc7AONok50xgKHtoq7JCwv3N0MgLB69T/8sxPdZxD5sEY2lFB7BKWdB3LtPHnkAwvxtvNC2ZnQCiTjgXhKnb/5YU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614779864419213.3794251221849; Wed, 3 Mar 2021 05:57:44 -0800 (PST) Received: from localhost ([::1]:50846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHS0V-0002IP-E5 for importer@patchew.org; Wed, 03 Mar 2021 08:57:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHRwO-0005Kx-KQ; Wed, 03 Mar 2021 08:53:28 -0500 Received: from mail-qv1-xf2b.google.com ([2607:f8b0:4864:20::f2b]:37320) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHRwN-0002B8-3n; Wed, 03 Mar 2021 08:53:28 -0500 Received: by mail-qv1-xf2b.google.com with SMTP id n4so9373699qvl.4; Wed, 03 Mar 2021 05:53:26 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id x187sm17425500qkd.83.2021.03.03.05.53.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 05:53:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QdPd6+T9TYulDYan4MqsgMWZ2nXNjoGfebenRUzAWpA=; b=cmMk2DzVL05NQGTnFI27wpv8wj2V8yOnPQMsZ15mwEtaNlLi+KW20LgNLjiGMZscuO RBcZjyEk6eMwo99Y+94uUoIaES/Fq0WruRlApc7vbFG0dfsdiQfjaTIRYfnnvSjEJlZJ qZZ5OCbBWuRnD9hzVHllj/Vq1xKUF6zGXnN/Zl1KF13mNdVFLMYda7KfTNIWACwNbXLV v8QEjPgd17RRZHJhdvSKwjGAwOWjVURiOwWSQ4Qij9VxHVm34bLQGOOuvj1+f5sPundy 4vs14xMqpfcsxXFb/nmP6aKRxj3K50iFcknFe4DfB0Ndun/SsmBKTZOwrenT4Miq1JJL 6EFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QdPd6+T9TYulDYan4MqsgMWZ2nXNjoGfebenRUzAWpA=; b=GkFWS664wvGo7z8CyKteoxoEyKi2RFmZiHbQakId/avt14OzMr3QZ6rnjobuR7nUAG 3zzT78mCFMKfiKcxJdFsA3lz7hOu7CMHr5NbB4rQrCtK9Qj/jep0DDIyvZBEQxIo/ESl +gWT47iZs3B9hbs7q9zm4Dw5PJs6WCgR4kT5Ja54A5jxXKfZv2O69KzufYKEPhPvCEBx oNA0ruWuT2uLauBTZu2xNL9xP3uC+bfqUN9kFOyg9P2OSih61Z3rmUjU+KhsPfMbXRzR VyQae9TFzvF10pnZohN9gElfVB9Gn1pNWjmMuI7U52+Q7LX/SjUhFC+rbkyrceurbVWW SRLA== X-Gm-Message-State: AOAM533nR0j48CQod8Vq3d2ku4Dhx9cHuwWWM5T5ybRz3epjzulmaw3K poUJEv++dXjgCLu5LhAfj9c= X-Google-Smtp-Source: ABdhPJwP9mWTqCtfgo0z/H9jZzT1stZux6IduqlUiPKtOqNcTRySTRlqb0eZXwLmhvZRmAUXHfpiIw== X-Received: by 2002:a05:6214:5af:: with SMTP id by15mr2695342qvb.37.1614779605846; Wed, 03 Mar 2021 05:53:25 -0800 (PST) From: Bin Meng To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell Subject: [PATCH v7 2/5] hw/arm: xlnx-zynqmp: Clean up coding convention issues Date: Wed, 3 Mar 2021 21:52:51 +0800 Message-Id: <20210303135254.3970-3-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210303135254.3970-1-bmeng.cn@gmail.com> References: <20210303135254.3970-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2b; envelope-from=bmeng.cn@gmail.com; helo=mail-qv1-xf2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Xuzhou Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Xuzhou Cheng There are some coding convention warnings in xlnx-zynqmp.c and xlnx-zynqmp.h, as reported by: $ ./scripts/checkpatch.pl include/hw/arm/xlnx-zynqmp.h $ ./scripts/checkpatch.pl hw/arm/xlnx-zynqmp.c Let's clean them up. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Edgar E. Iglesias --- (no changes since v4) Changes in v4: - remove one change that is not a checkpatch warning include/hw/arm/xlnx-zynqmp.h | 3 ++- hw/arm/xlnx-zynqmp.c | 9 ++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6f45387a17..be15cc8814 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -60,7 +60,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) =20 #define XLNX_ZYNQMP_GIC_REGIONS 6 =20 -/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k off= sets +/* + * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k off= sets * and under-decodes the 64k region. This mirrors the 4k regions to every = 4k * aligned address in the 64k region. To implement each GIC region needs a * number of memory region aliases. diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 881847255b..49465a2794 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -301,11 +301,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) =20 ram_size =3D memory_region_size(s->ddr_ram); =20 - /* Create the DDR Memory Regions. User friendly checks should happen at + /* + * Create the DDR Memory Regions. User friendly checks should happen at * the board level */ if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { - /* The RAM size is above the maximum available for the low DDR. + /* + * The RAM size is above the maximum available for the low DDR. * Create the high DDR memory region as well. */ assert(ram_size <=3D XLNX_ZYNQMP_MAX_RAM_SIZE); @@ -526,7 +528,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->sdhci[i]); Object *sdhci =3D OBJECT(&s->sdhci[i]); =20 - /* Compatible with: + /* + * Compatible with: * - SD Host Controller Specification Version 3.00 * - SDIO Specification Version 3.0 * - eMMC Specification Version 4.51 --=20 2.25.1 From nobody Fri May 17 07:47:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614779901; cv=none; d=zohomail.com; s=zohoarc; b=MDnFxCnygYg4KIVld7A7tDJe75ePN9R9RIVCS61g51n2zY1NIabSvWGgFUBUbHrPL++/hGuOG5Z2srZwMgoCbL8mxdVPLmSp0MuvssfTgN9xTqTx9eVHdEJIWh/GNH0hxQBrUAwVgtz49Bgt6iaEtnioMidRJmU7dI1A+sRRpsk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614779901; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E8/sVwG2wDDumeb0HVHtgZ67kaGTJTkb0zPWfTfzhtU=; b=KLpaK1Iq7h4mOcaxABFbpmAk5I4x1Z3H98JyZw9uKfGGSXMp3ZToEN1hfpINse2RYSpvOzPp9KDpJ9OK8LsS1tpWBhhLKb2R2ryavDdcb4w2MdQ9OySQiMzrBcWfpQ62g04ObXaU/CzEGJF3emx4k8Llbg/O2EkIFbZF7CywErQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614779901861484.1954719273218; Wed, 3 Mar 2021 05:58:21 -0800 (PST) Received: from localhost ([::1]:52626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHS16-00031L-Rk for importer@patchew.org; Wed, 03 Mar 2021 08:58:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHRwS-0005NG-8K; Wed, 03 Mar 2021 08:53:33 -0500 Received: from mail-qk1-x72b.google.com ([2607:f8b0:4864:20::72b]:44117) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHRwQ-0002Cg-IZ; Wed, 03 Mar 2021 08:53:32 -0500 Received: by mail-qk1-x72b.google.com with SMTP id 130so9314833qkh.11; Wed, 03 Mar 2021 05:53:29 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id x187sm17425500qkd.83.2021.03.03.05.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 05:53:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E8/sVwG2wDDumeb0HVHtgZ67kaGTJTkb0zPWfTfzhtU=; b=G22V3PeE/nBgIaZgtfvlHTy0jbU/p///+Y1J0CR5uOne24Fvy27ZSzGYWnhMfOkp/D zTPC+YYsP9rtupC70LBsUqEoTflT1TR2DsDxRJk0XjP0s0RE2guFLrdL3yq0P9GiqcTr wq3VS7mOP30F3nXyVGlHBTOxxMypbbXakDLGKiwYqJaYmh9ZOixCt5M5TL6BwtRFuSbD uE+Acjg87/v8kK77NuMXtZICRUSCwK3O+33XKOQkYkzM3hcf1ZLu0asQmXG08uIqiBYK FWCiEnSECH6IvAR540Q1Ms4+EgMFYP1XC8srrgxCxrEYKxkxTvye9Tm1dhKTbkBUJCq8 bycg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E8/sVwG2wDDumeb0HVHtgZ67kaGTJTkb0zPWfTfzhtU=; b=YcAZeEFlV+uEAnRIVJrCTLGQVO8a+J1iHmTBN0n1otm7V7dcUL0u0Irtass7xX+gPT 2uDncSOm83c230XWTNGMwM310TkX0Kspj7WlVYnhvha565sYIGFK2+U8ofJ5nmp8LJaO GNxV2dynXCyO4DGPepfRRRCDF+Vbz1tTH9VHntJdRee/CY4L+XW49xQsrTdp8TV2DHQ8 7Tl3StCFI1QSYaAbe/5Q5P6ZAZ0SnVxtrEFtrrqMdfCrtEyFs/veeS40muS9HWZ8obrH RE4T51r9vcZpEprc8fLnn/kVrHRejv1y6zcNR61sXA6x5C4uXGGITBhDRWe8X6L3z5bw 2Kpg== X-Gm-Message-State: AOAM532/3f4Ws/W3EKE2OimaWDqZ8uOKQ7/HXtK4beyMEVRMbPiEL5Ri 9WSRK3hSuGW9Dyj+sV0eif6awTsfr4s= X-Google-Smtp-Source: ABdhPJxXTAX4tAsaQuhDMbe5EUrWc9NSri5PYzffalIIJJU3x4gbb14DvTt9O19EcyX8+JGdWGkaTw== X-Received: by 2002:ae9:dcc4:: with SMTP id q187mr22694501qkf.5.1614779609596; Wed, 03 Mar 2021 05:53:29 -0800 (PST) From: Bin Meng To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell Subject: [PATCH v7 3/5] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI Date: Wed, 3 Mar 2021 21:52:52 +0800 Message-Id: <20210303135254.3970-4-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210303135254.3970-1-bmeng.cn@gmail.com> References: <20210303135254.3970-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72b; envelope-from=bmeng.cn@gmail.com; helo=mail-qk1-x72b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Xuzhou Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Xuzhou Cheng Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream link of GQSPI to CSU DMA. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Edgar E. Iglesias --- (no changes since v4) Changes in v4: - Rename "csu_dma" to "qspi_dma" Changes in v3: - new patch: xlnx-zynqmp: Add XLNX CSU DMA module include/hw/arm/xlnx-zynqmp.h | 2 ++ hw/arm/xlnx-zynqmp.c | 12 ++++++++++++ hw/arm/Kconfig | 1 + 3 files changed, 15 insertions(+) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index be15cc8814..2edeed911c 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -35,6 +35,7 @@ #include "target/arm/cpu.h" #include "qom/object.h" #include "net/can_emu.h" +#include "hw/dma/xlnx_csu_dma.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -108,6 +109,7 @@ struct XlnxZynqMPState { XlnxZynqMPRTC rtc; XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; + XlnxCSUDMA qspi_dma; =20 char *boot_cpu; ARMCPU *boot_cpu_ptr; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 49465a2794..76cc3b5e78 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -50,6 +50,7 @@ #define QSPI_ADDR 0xff0f0000 #define LQSPI_ADDR 0xc0000000 #define QSPI_IRQ 15 +#define QSPI_DMA_ADDR 0xff0f0800 =20 #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 @@ -284,6 +285,8 @@ static void xlnx_zynqmp_init(Object *obj) for (i =3D 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDM= A); } + + object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_D= MA); } =20 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -643,6 +646,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, gic_spi[adma_ch_intr[i]]); } + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, gic_spi[QSPI_IRQ]); + object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", + OBJECT(&s->qspi_dma), errp); } =20 static Property xlnx_zynqmp_props[] =3D { diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4e6f4ffe90..27ec10f89b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -353,6 +353,7 @@ config XLNX_ZYNQMP_ARM select SSI_M25P80 select XILINX_AXI select XILINX_SPIPS + select XLNX_CSU_DMA select XLNX_ZYNQMP select XLNX_ZDMA =20 --=20 2.25.1 From nobody Fri May 17 07:47:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614779872; cv=none; d=zohomail.com; s=zohoarc; b=l4KdHL6Ndsgv5Zu5SDw6Q7qEQHXOoxB/cg25ylyBwMoRIy51FvJEJA9au3ppcfuT2VySfsZvLxGhhq8gyoNnT7boMTV0VaAXLBPPwTQ1jbbaCiZYWA3Q3n/Ta8l4ymYDjSW1HoZpaWvmFNFCn7k8HRipkgpjxCAoL4tAlE44WGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614779872; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+UzSdyjSd904zCeIE0aTyBCjawmbJBRlBQ1EDG6ABek=; b=RIgm+g5SdeGpgfNROB5Knmkcov4oWzxOacVfQpLBhg8wDdSn94o7u7DX4wE6b/0l6PtZxZApq/VZ7ilZAkym5bKg6//TwQQrIzMtCX9dicBEZtkSoZhogLBq+L2wLZHKGVs7lTp/7skKzJer2YyK1MxcMpa+dagjHeKSD7fimw4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614779872534567.7494489329325; Wed, 3 Mar 2021 05:57:52 -0800 (PST) Received: from localhost ([::1]:51050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHS0d-0002NK-ER for importer@patchew.org; Wed, 03 Mar 2021 08:57:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHRwd-0005P3-Vw; Wed, 03 Mar 2021 08:53:45 -0500 Received: from mail-qk1-x72c.google.com ([2607:f8b0:4864:20::72c]:46653) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHRwU-0002DZ-MM; Wed, 03 Mar 2021 08:53:40 -0500 Received: by mail-qk1-x72c.google.com with SMTP id a9so9392467qkn.13; Wed, 03 Mar 2021 05:53:34 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id x187sm17425500qkd.83.2021.03.03.05.53.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 05:53:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+UzSdyjSd904zCeIE0aTyBCjawmbJBRlBQ1EDG6ABek=; b=V+EQ6Fyf5AnNl61yGsasz69JBqU209a/EG7DjwAxCVqsoOoLNw+iwpVCEraJzfDlzp aXinS4kWO5fqOY3pQO8VNjDTfdXEw1K4cI6jKWjJhGeefiD79E4FufJi/vKEy0sPTHsq 9ZVeQWP3pIwMPgrocTH12GFntcR7yjHvNKJ3GwfmqPqz32xN4ZXIryHoCnEO5dycOH3f qAbjMar7FEzbYJG7lUFGn4gCT3dadsdOaYNfjAdjVmuvWFaPQ/u34fW1p+Mzlret+NlL SnDoAxizDOeg5WJGKGyTVVTfHpNu3jOLN9CS9xLH9ENW2GSxwyTonbcZGh0YIp00eDuo Gq6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+UzSdyjSd904zCeIE0aTyBCjawmbJBRlBQ1EDG6ABek=; b=BLCPVNZEj4EvZBqJ0MRM2iLYuW6MFLQhMpxguKY1iDIZHZ9XKBWwQqHV3taKJm8teh Iaxo67K2FmoENwSZdTulwO6q/XWXtwZXrUJ/uyB3FBeTqtGdejbFC6PQSIzSQ0XFsIAN YzIpJy8aAVxk8bKcMBPtpf/WWE3UFvXPsrCr5YkggykiQl8YPZVeabU79ztqczTHyNaZ E3Fxi805KrZ27Y+vDDq3/uisFLQeicCTdkP1FttTKk8BOceGWj3/FXj6w1zEolSFFmM3 UYl0WGx0CnKix5mL6BrSM8zWx13VYSE/zzrZ/3FBkK/SNO1U7pz1+G7jw7bWgU3Gcyui w58A== X-Gm-Message-State: AOAM530atnsLrUp12oi6NSxRGTfAYgEhRNyc4oNu26HhILAGUxi/N4Q2 0dPiVZ33uINmAcKGzfk9673fxKpvuuY= X-Google-Smtp-Source: ABdhPJwaYqQ8eKtENreYWh1QGQAly0kzqJZleVsgFFKKlHKil5R5ynymGbvaawrzY+oid5iavQm10g== X-Received: by 2002:a37:c16:: with SMTP id 22mr24802191qkm.84.1614779613628; Wed, 03 Mar 2021 05:53:33 -0800 (PST) From: Bin Meng To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell Subject: [PATCH v7 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues Date: Wed, 3 Mar 2021 21:52:53 +0800 Message-Id: <20210303135254.3970-5-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210303135254.3970-1-bmeng.cn@gmail.com> References: <20210303135254.3970-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=bmeng.cn@gmail.com; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xuzhou Cheng , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Francisco Iglesias , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Xuzhou Cheng There are some coding convention warnings in xilinx_spips.c, as reported by: $ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c Let's clean them up. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- (no changes since v1) hw/ssi/xilinx_spips.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a897034601..8a0cc22d42 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -176,7 +176,8 @@ FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) #define R_GQSPI_GFIFO_THRESH (0x150 / 4) #define R_GQSPI_DATA_STS (0x15c / 4) -/* We use the snapshot register to hold the core state for the currently +/* + * We use the snapshot register to hold the core state for the currently * or most recently executed command. So the generic fifo format is defined * for the snapshot register */ @@ -424,7 +425,8 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) xlnx_zynqmp_qspips_update_ixr(s); } =20 -/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) +/* + * N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: * Each digit in the below array is a single bit (num =3D=3D 3): @@ -637,8 +639,10 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) tx_rx[i] =3D tx; } } else { - /* Extract a dummy byte and generate dummy cycles according to= the - * link state */ + /* + * Extract a dummy byte and generate dummy cycles according to= the + * link state + */ tx =3D fifo8_pop(&s->tx_fifo); dummy_cycles =3D 8 / s->link_state; } @@ -721,8 +725,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } break; case (SNOOP_ADDR): - /* Address has been transmitted, transmit dummy cycles now if - * needed */ + /* + * Address has been transmitted, transmit dummy cycles now if = needed + */ if (s->cmd_dummies < 0) { s->snoop_state =3D SNOOP_NONE; } else { @@ -876,7 +881,7 @@ static void xlnx_zynqmp_qspips_notify(void *opaque) } =20 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, - unsigned size) + unsigned size) { XilinxSPIPS *s =3D opaque; uint32_t mask =3D ~0; @@ -970,7 +975,7 @@ static uint64_t xlnx_zynqmp_qspips_read(void *opaque, } =20 static void xilinx_spips_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) + uint64_t value, unsigned size) { int mask =3D ~0; XilinxSPIPS *s =3D opaque; @@ -1072,7 +1077,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr = addr, } =20 static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) + uint64_t value, unsigned size) { XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(opaque); uint32_t reg =3D addr / 4; --=20 2.25.1 From nobody Fri May 17 07:47:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614780004; cv=none; d=zohomail.com; s=zohoarc; b=RBfbnWpLDc5Ns3+5977OJ2MYWGPX4BmAdT7qlK8ptQM6xe0dCRtfqU6aIHdvc7GQ9bhZiZkNeCiijJyQu7u/WAmXNUJig814ryYtswX0HapqTmEsLHQQPA9bX1dpkxDWQuYaxi7SNjjIGjVpCq4q7p2m4I0wMdv5Ii5D6fVzSOs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614780004; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AvmXxELlSPq/Cqpu0ZFOXyo28njZpHc7YVv+Gg5cBAE=; b=BAHDt0Wxf8T+BwJTzZD6Tk1FJezea2LlvrL0TJk02wMO68SjB7PRsYlBMzjp0t741gPabpOsnnKSYIKziV7mmN+q+5eGvSV2PwYjXBBEtWpyFYCS0r5Nn75Q7izJ/Eu75Nsybm2/9eZDtM+f5+b7QQ7M6SJn+pb7IPkPC1cE6fY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 161478000424493.3574924248818; Wed, 3 Mar 2021 06:00:04 -0800 (PST) Received: from localhost ([::1]:58380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lHS2l-0005OS-61 for importer@patchew.org; Wed, 03 Mar 2021 09:00:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56246) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lHRwl-0005RD-Mr; Wed, 03 Mar 2021 08:53:53 -0500 Received: from mail-qt1-x830.google.com ([2607:f8b0:4864:20::830]:42936) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lHRwb-0002ET-70; Wed, 03 Mar 2021 08:53:46 -0500 Received: by mail-qt1-x830.google.com with SMTP id d11so16789384qtx.9; Wed, 03 Mar 2021 05:53:38 -0800 (PST) Received: from i9-aorus-gtx1080.localdomain (144.168.56.201.16clouds.com. [144.168.56.201]) by smtp.gmail.com with ESMTPSA id x187sm17425500qkd.83.2021.03.03.05.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 05:53:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AvmXxELlSPq/Cqpu0ZFOXyo28njZpHc7YVv+Gg5cBAE=; b=JYw24AjKaKuedRhgHkirdQ5Ih/cpHdsyQbXqOl/ExsD80e16ggCtO0vLiXKIvHZO69 +mX21bmsomvSBMrhihAiREOdAdTmHumxZz7mJI4KB8yE1dGUgLMJ/zia9TMkxWqYNRo6 kqUm36qaFFZevoFdvsuE40PyrxC6jP1q1rCI1aszWFZcealBQa8cDp9wAdI4BdY3ZnsH blwv5HmWIhE6wBLUpaOb2/7Ge0gy568slhdLVePxpNvLjUBqfUnnsZajJYITV5qIU9IK IN4zkRTmJM32HsuIntG9AGcq64Ya4eFDdaM3KGDZZpmUVQtejIgMBa3y/sze1+0BVMaW Ej1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AvmXxELlSPq/Cqpu0ZFOXyo28njZpHc7YVv+Gg5cBAE=; b=PM6i3XzJE1Ur8TB2xP8nLpRUQEjkGzHU1JU0m7QJDmjKvxleSgfIZHp2heDpDLs2++ fFokJgB6P0sSIFMRdaff8gE3N+Qr83AQFRFndQ71tX2TpSNUWjUEjr9BQFXQPUSdxvH1 NGuV/oFcBiCCaTNZUHwOW+OGP36tOmh+iD1Y+3tqCoQ/yjjPXTDHY+IdOmwjlae7vIg9 MKq5jFCVxlNp6N2/aumJiD1y+Tg1+CrtzqqefWQbSIGdzjhzFFMzTaeP8ydvisZIKTqX Ut1kSSKkRfA6g81vGUO+6WwL48ReFebY4EMGDZUaUfU7Wp6RsLLG0PdW4YSs1ZYssgya 76Eg== X-Gm-Message-State: AOAM5304gSadytluVZy60PlsN5BM311Q+djg5PW2dHoh8pEpYrxPd2vk zlsPSucn5hj6zQfVaUPSw94= X-Google-Smtp-Source: ABdhPJwDiLHWnsBvOxgdeowZvWJ2KGsMCgjVPCOZymllsL03J+ftPU8MwFiAyCHOkIOJ4pvIW7ieGA== X-Received: by 2002:ac8:7257:: with SMTP id l23mr22754643qtp.350.1614779618084; Wed, 03 Mar 2021 05:53:38 -0800 (PST) From: Bin Meng To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell Subject: [PATCH v7 5/5] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips Date: Wed, 3 Mar 2021 21:52:54 +0800 Message-Id: <20210303135254.3970-6-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210303135254.3970-1-bmeng.cn@gmail.com> References: <20210303135254.3970-1-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=bmeng.cn@gmail.com; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Xuzhou Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Xuzhou Cheng Now that the Xilinx CSU DMA model is implemented, the existing DMA related dead codes in the ZynqMP QSPI are useless and should be removed. The maximum register number is also updated to only include the QSPI registers. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Edgar E. Iglesias --- (no changes since v4) Changes in v4: - Modify XLNX_ZYNQMP_SPIPS_R_MAX Changes in v3: - new patch: xilinx_spips: Remove DMA related code from zynqmp_qspips include/hw/ssi/xilinx_spips.h | 2 +- hw/ssi/xilinx_spips.c | 10 ---------- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 3eae73480e..06bfd18312 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -34,7 +34,7 @@ typedef struct XilinxSPIPS XilinxSPIPS; =20 #define XLNX_SPIPS_R_MAX (0x100 / 4) -#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4) +#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) =20 /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 8a0cc22d42..1e9dba2039 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -195,13 +195,6 @@ #define R_GQSPI_MOD_ID (0x1fc / 4) #define R_GQSPI_MOD_ID_RESET (0x10a0000) =20 -#define R_QSPIDMA_DST_CTRL (0x80c / 4) -#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) -#define R_QSPIDMA_DST_I_MASK (0x820 / 4) -#define R_QSPIDMA_DST_I_MASK_RESET (0xfe) -#define R_QSPIDMA_DST_CTRL2 (0x824 / 4) -#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) - /* size of TXRX FIFOs */ #define RXFF_A (128) #define TXFF_A (128) @@ -417,9 +410,6 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) s->regs[R_GQSPI_GPIO] =3D 1; s->regs[R_GQSPI_LPBK_DLY_ADJ] =3D R_GQSPI_LPBK_DLY_ADJ_RESET; s->regs[R_GQSPI_MOD_ID] =3D R_GQSPI_MOD_ID_RESET; - s->regs[R_QSPIDMA_DST_CTRL] =3D R_QSPIDMA_DST_CTRL_RESET; - s->regs[R_QSPIDMA_DST_I_MASK] =3D R_QSPIDMA_DST_I_MASK_RESET; - s->regs[R_QSPIDMA_DST_CTRL2] =3D R_QSPIDMA_DST_CTRL2_RESET; s->man_start_com_g =3D false; s->gqspi_irqline =3D 0; xlnx_zynqmp_qspips_update_ixr(s); --=20 2.25.1