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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id gf20sm4232234pjb.39.2021.03.02.09.58.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 09:58:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=acclXejcPgSIlezM5omUXEx8bJfnemtIS24m5TCaM+g=; b=qx5nSJKXwokyv1pqk6JShVsDwgOsTLloclZQmJjWPqCdHP6uFz/UOqgemfqwsa+HRs EMJwiFNZrYh2MHxFSYB3j7pMomajeG2hVEsreXTpq+dSxo5bQJJ6Dd7hXZTY9daSaxwk mkso0WL/uHE/yZ78wgvpWSOxtp+IV82pmX2/1e5iEyLBVhWs6tB0LoKmQc+gRg8uOLJ/ YiKDMFoIj5xlxazKucy0okPYcO8NtFIXTIHWWxSZNlO+GmNL1fv34QkMqU47BpR8msLE gOjR0cJG8B948yH66foXkFCxtx6ki4htDS28bLyi999ZQyhwNU6Miy3SuZpqafIaTlDr wcmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=acclXejcPgSIlezM5omUXEx8bJfnemtIS24m5TCaM+g=; b=Uc/aHY5Hg34XuS24+RlAxVuL4yE7dIfVmd7j2OFTT+3srBWuoo2hLH3SwxlfAVja8D EfIiX86fdNps+pcnQOaIRSObM+lvltzZSNUGR6wQBFohEZbRgW8peXLeku4CBw0EYeYU i2FatW4REBGsYRpFmcebRTpc+OxLFIy7/FPdblk7XunaFhkMq9Xo+LL6eiUkQR+2QvsF acH54uWOVJ1tBqjhxgqWNBOCqjovvnTI/7ZrVcdt6quG/RWnm7oqvZVdN8VbwH0Mmt5e hZjjF/ZL/9BtMUWbcQ4OmeNqWcWr2sFKvm4AFtvKtL8QWVn8qG+Bhzr68xDiSsedCX2k O35g== X-Gm-Message-State: AOAM5309oXejACSQlucYiMA3bJ3yRn9Bz44MGutLAYW0FxZXpG52vCR+ TmXMVBq3dHs5YUe8G7C0aYgCcy0XijnWDQ== X-Google-Smtp-Source: ABdhPJzDWTzdHv87KGNib/IbU1aSSNTbQa6NOThRCS5wuJp7wrZGfmx3lsWkH45wEFsEscDiP9VMGA== X-Received: by 2002:a63:fd0a:: with SMTP id d10mr18615719pgh.405.1614707888602; Tue, 02 Mar 2021 09:58:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 24/27] accel/tcg: move CF_CLUSTER calculation to curr_cflags Date: Tue, 2 Mar 2021 09:57:38 -0800 Message-Id: <20210302175741.1079851-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210302175741.1079851-1-richard.henderson@linaro.org> References: <20210302175741.1079851-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Alex Benn=C3=A9e There is nothing special about this compile flag that doesn't mean we can't just compute it with curr_cflags() which we should be using when building a new set. Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210224165811.11567-3-alex.bennee@linaro.org> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 8 +++++--- include/exec/tb-lookup.h | 3 --- accel/tcg/cpu-exec.c | 9 ++++----- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 6 +++--- softmmu/physmem.c | 2 +- 6 files changed, 14 insertions(+), 16 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b7b3c0ef12..1a69c07add 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -519,10 +519,12 @@ static inline uint32_t tb_cflags(const TranslationBlo= ck *tb) } =20 /* current cflags for hashing/comparison */ -static inline uint32_t curr_cflags(void) +static inline uint32_t curr_cflags(CPUState *cpu) { - return (parallel_cpus ? CF_PARALLEL : 0) - | (icount_enabled() ? CF_USE_ICOUNT : 0); + uint32_t cflags =3D deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_ind= ex); + cflags |=3D parallel_cpus ? CF_PARALLEL : 0; + cflags |=3D icount_enabled() ? CF_USE_ICOUNT : 0; + return cflags; } =20 /* TranslationBlock invalidate API */ diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 62a509535d..b2247d458b 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -27,9 +27,6 @@ static inline TranslationBlock * tb_lookup(CPUState *cpu, hash =3D tb_jmp_cache_hash_func(pc); tb =3D qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); =20 - cf_mask &=3D ~CF_CLUSTER_MASK; - cf_mask |=3D cpu->cluster_index << CF_CLUSTER_SHIFT; - if (likely(tb && tb->pc =3D=3D pc && tb->cs_base =3D=3D cs_base && diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ef96b312a1..45286dc4b3 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -249,8 +249,7 @@ void cpu_exec_step_atomic(CPUState *cpu) TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - uint32_t cflags =3D 1; - uint32_t cf_mask =3D cflags & CF_HASH_MASK; + uint32_t cflags =3D (curr_cflags(cpu) & ~CF_PARALLEL) | 1; int tb_exit; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { @@ -260,7 +259,7 @@ void cpu_exec_step_atomic(CPUState *cpu) cpu->running =3D true; =20 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb =3D tb_lookup(cpu, pc, cs_base, flags, cf_mask); + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); =20 if (tb =3D=3D NULL) { mmap_lock(); @@ -497,7 +496,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) if (replay_has_exception() && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra =3D= =3D 0) { /* Execute just one insn to trigger exception pending in the l= og */ - cpu->cflags_next_tb =3D (curr_cflags() & ~CF_USE_ICOUNT) | 1; + cpu->cflags_next_tb =3D (curr_cflags(cpu) & ~CF_USE_ICOUNT) | = 1; } #endif return false; @@ -794,7 +793,7 @@ int cpu_exec(CPUState *cpu) have CF_INVALID set, -1 is a convenient invalid value that does not require tcg headers for cpu_common_reset. */ if (cflags =3D=3D -1) { - cflags =3D curr_cflags(); + cflags =3D curr_cflags(cpu); } else { cpu->cflags_next_tb =3D -1; } diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 05e3d52c2f..99403e3eb3 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -154,7 +154,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) =20 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, curr_cflags()); + tb =3D tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu)); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bbd919a393..f29b47f090 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2194,7 +2194,7 @@ tb_invalidate_phys_page_range__locked(struct page_col= lection *pages, if (current_tb_modified) { page_collection_unlock(pages); /* Force execution of one insn next time. */ - cpu->cflags_next_tb =3D 1 | curr_cflags(); + cpu->cflags_next_tb =3D 1 | curr_cflags(cpu); mmap_unlock(); cpu_loop_exit_noexc(cpu); } @@ -2362,7 +2362,7 @@ static bool tb_invalidate_phys_page(tb_page_addr_t ad= dr, uintptr_t pc) #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_modified) { /* Force execution of one insn next time. */ - cpu->cflags_next_tb =3D 1 | curr_cflags(); + cpu->cflags_next_tb =3D 1 | curr_cflags(cpu); return true; } #endif @@ -2438,7 +2438,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) * operations only (which execute after completion) so we don't * double instrument the instruction. */ - cpu->cflags_next_tb =3D curr_cflags() | CF_MEMI_ONLY | CF_LAST_IO | n; + cpu->cflags_next_tb =3D curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO |= n; =20 qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, "cpu_io_recompile: rewound execution of TB to " diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 19e0aa9836..7e8b0fab89 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -937,7 +937,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, cpu_loop_exit_restore(cpu, ra); } else { /* Force execution of one insn next time. */ - cpu->cflags_next_tb =3D 1 | curr_cflags(); + cpu->cflags_next_tb =3D 1 | curr_cflags(cpu); mmap_unlock(); if (ra) { cpu_restore_state(cpu, ra, true); --=20 2.25.1