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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id g3sm17897079ejz.91.2021.03.02.06.59.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 06:59:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dgsnoJxYfQ+EnbpTe4VgFeqBOMAHdGvYFMjn+ks1sAo=; b=t2Ht/JVC4b+oFbnxZ+UFN+JXDuobfX1vFNi97VSjC9Rzk3N/ovJK1o2MoMytJo0JMD 4EiGPsNCo5vD4+6YaI6l8dpj2UGDs6BwwJdjqa0dI1JLtsG8xaNGItXpP9Ryopy7Lnha qlobvG6Tg0JOueYPS/vvtsgsiRwUhelIJTMptdO5pQO82ka54MUFvbGQqSrBzvtNz3u9 0XgrILJUmoTiIUTusd/Cef96+7hs29gRZxFBUrSICJCSYDhxpolaf+sb3q1OkxHvKXV2 rtMQEqmw+yMHO3EcHVB6plaYtsxWH1VbeWVA8oL5xKixc75J1EhXa5Mfav4I8KUOsZ6/ R7ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dgsnoJxYfQ+EnbpTe4VgFeqBOMAHdGvYFMjn+ks1sAo=; b=Mq4i6z+IvXoFZmBWagI0ie9oYJ+GOE/WFHTKKN7NvjRK/WDe2zzd4sWn8Ypt8IrUyU Q465d7gnFakr/+qgcs7WD1wRCU6MO/4z4hHcdg/SrC+1qgBhE4kIlXS0FlajYEV33PLd lJffU9c0fkstVsOcEcUtdlbU3tQoCwlDjkqWhuCIU6QoTENm6jYFniZf11kIW4QUPpVH 3ELUkuowf7h0ilongSFRRjF+FvROwMzZrFarCZ40SqzJ62Jf1gwwfNb4m5L5Ap1e0pWk BiGDNO7uda1qpMNJ9KhF32xllST/vohgC2K5dXW6jyuUnuMXdZDt0eFgSoQ0yNfYxpBH OlCA== X-Gm-Message-State: AOAM533Z7KJy6wSOfZX+sjl2ksta+2clXPG8J+P0lml2+8s91ugtL26F TyS6Qf6/rzh51sl0kdPN6zE= X-Google-Smtp-Source: ABdhPJzpvtRvkgUpQFZK7U1FU2f6sgDQfrVGiLJC13htdoYsPNnoU8hQQXsUnvHlgwikIci/93HI7Q== X-Received: by 2002:a17:906:3a10:: with SMTP id z16mr20956132eje.483.1614697196272; Tue, 02 Mar 2021 06:59:56 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Max Filippov , David Gibson , "Edgar E. Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Guan Xuetao , Alistair Francis , Michael Rolnik , Palmer Dabbelt , Richard Henderson , Laurent Vivier , Paolo Bonzini , Greg Kurz , Stafford Horne , qemu-ppc@nongnu.org, Anthony Green , Aurelien Jarno , Jiaxun Yang , Cornelia Huck , Claudio Fontana , Sagar Karandikar , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Michael Walle , Marek Vasut , Marcel Apfelbaum , Artyom Tarasenko , Peter Maydell , Aleksandar Rikalo , Chris Wulff , David Hildenbrand , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-s390x@nongnu.org, Sarah Harris , Eduardo Habkost , Bastian Koppelmann , qemu-riscv@nongnu.org, Mark Cave-Ayland , "Michael S. Tsirkin" , Yoshinori Sato , Taylor Simpson Subject: [PATCH v3 13/27] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps Date: Tue, 2 Mar 2021 15:58:04 +0100 Message-Id: <20210302145818.1161461-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210302145818.1161461-1-f4bug@amsat.org> References: <20210302145818.1161461-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 8 -------- include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++ hw/core/cpu.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 4 +--- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 25 files changed, 38 insertions(+), 35 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6713a615916..9a86c707cf7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,11 +103,6 @@ struct AccelCPUClass; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -146,9 +141,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 3c3f211136d..0c8f616a565 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,19 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * and the associated memory transaction attributes to use for t= he + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c44229205ff..6932781425a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cc->sysemu_ops->get_phys_page_attrs_debug) { + return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); + return cc->sysemu_ops->get_phys_page_debug(cpu, addr); } =20 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 8d7a73d638e..d9a51d9f647 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps alpha_sysemu_ops =3D { + .get_phys_page_debug =3D alpha_cpu_get_phys_page_debug, .vmsd =3D &vmstate_alpha_cpu, }; #endif @@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index acaa3ab68da..6cd546213de 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps arm_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, @@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index b455a5e3434..040d3526995 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static struct SysemuCPUOps avr_sysemu_ops =3D { + .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, .vmsd =3D &vms_avr_cpu, }; =20 @@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; - cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 3ffd47c488d..77f821f4d9a 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps cris_sysemu_ops =3D { + .get_phys_page_debug =3D cris_cpu_get_phys_page_debug, .vmsd =3D &vmstate_cris_cpu, }; #endif @@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ba6401a4979..7de37aadd4d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps hppa_sysemu_ops =3D { + .get_phys_page_debug =3D hppa_cpu_get_phys_page_debug, .vmsd =3D &vmstate_hppa_cpu, }; #endif @@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 10884540610..c7a18cd8e4f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps i386_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, @@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 #ifndef CONFIG_USER_ONLY cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index bc754034c7e..c80cae9ff3b 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps lm32_sysemu_ops =3D { + .get_phys_page_debug =3D lm32_cpu_get_phys_page_debug, .vmsd =3D &vmstate_lm32_cpu, }; #endif @@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1641cf87a52..eaf5f34d22c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps m68k_sysemu_ops =3D { + .get_phys_page_debug =3D m68k_cpu_get_phys_page_debug, .vmsd =3D &vmstate_m68k_cpu, }; #endif @@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) - cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f59a1dd8576..a21f15192ae 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps mb_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug, .vmsd =3D &vmstate_mb_cpu, }; #endif @@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 50ab8f2a88c..285564b4d5b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps mips_sysemu_ops =3D { + .get_phys_page_debug =3D mips_cpu_get_phys_page_debug, .vmsd =3D &vmstate_mips_cpu, }; #endif @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 86f6665a048..47b8735bb75 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) } =20 static struct SysemuCPUOps moxie_sysemu_ops =3D { + .get_phys_page_debug =3D moxie_cpu_get_phys_page_debug, .vmsd =3D &vmstate_moxie_cpu, }; =20 @@ -124,9 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D moxie_cpu_has_work; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; -#ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; -#endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->sysemu_ops =3D &moxie_sysemu_ops; cc->tcg_ops =3D &moxie_tcg_ops; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 971c0d8a00a..e5cbf43d6ee 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -215,6 +215,7 @@ static const VMStateDescription vmstate_nios2_cpu =3D { }; =20 static struct SysemuCPUOps nios2_sysemu_ops =3D { + .get_phys_page_debug =3D nios2_cpu_get_phys_page_debug, .vmsd =3D &vmstate_nios2_cpu, }; #endif @@ -249,7 +250,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 55eb195df40..c666e86e919 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps openrisc_sysemu_ops =3D { + .get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug, .vmsd =3D &vmstate_openrisc_cpu, }; #endif @@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3e42f7265eb..eaf7c13e5a6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -582,6 +582,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps riscv_sysemu_ops =3D { + .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, /* For now, mark unmigratable: */ .vmsd =3D &vmstate_riscv_cpu, }; @@ -628,7 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index cb8718a58dc..d1a7a5f6877 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -180,6 +180,7 @@ static const VMStateDescription vmstate_rx_cpu =3D { }; =20 static struct SysemuCPUOps rx_sysemu_ops =3D { + .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, .vmsd =3D &vmstate_rx_cpu, }; #endif @@ -218,7 +219,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) #endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; - cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 92b7a66d3c3..30117fc8cd7 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps s390_sysemu_ops =3D { + .get_phys_page_debug =3D s390_cpu_get_phys_page_debug, .get_crash_info =3D s390_cpu_get_crash_info, .write_elf64_note =3D s390_cpu_write_elf64_note, .vmsd =3D &vmstate_s390_cpu, @@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 038dfa25e84..843f39de41c 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { }; =20 static struct SysemuCPUOps sh4_sysemu_ops =3D { + .get_phys_page_debug =3D superh_cpu_get_phys_page_debug, .vmsd =3D &vmstate_sh_cpu, }; #endif @@ -262,7 +263,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sh4_sysemu_ops; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 6a324c2765b..c8a115c886a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps sparc_sysemu_ops =3D { + .get_phys_page_debug =3D sparc_cpu_get_phys_page_debug, .vmsd =3D &vmstate_sparc_cpu, }; #endif @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index f1f72be8281..0c4b5021e79 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -149,6 +149,7 @@ static const VMStateDescription vmstate_tricore_cpu =3D= { }; =20 static struct SysemuCPUOps tricore_sysemu_ops =3D { + .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, .vmsd =3D &vmstate_tricore_cpu, }; =20 @@ -180,7 +181,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 50a61ac0b83..610fb5393ae 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { }; =20 static struct SysemuCPUOps uc32_sysemu_ops =3D { + .get_phys_page_debug =3D uc32_cpu_get_phys_page_debug, .vmsd =3D &vmstate_uc32_cpu, }; =20 @@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D uc32_cpu_has_work; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 7efe5b4f207..44a4524bc0a 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { }; =20 static struct SysemuCPUOps xtensa_sysemu_ops =3D { + .get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug, .vmsd =3D &vmstate_xtensa_cpu, }; #endif @@ -222,7 +223,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &xtensa_sysemu_ops; - cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; cc->tcg_ops =3D &xtensa_tcg_ops; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 068f4a4012e..d38d194fe87 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps ppc_sysemu_ops =3D { + .get_phys_page_debug =3D ppc_cpu_get_phys_page_debug, .write_elf32_note =3D ppc32_cpu_write_elf32_note, .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, @@ -10893,7 +10894,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif =20 --=20 2.26.2