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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id f17sm17965537edu.28.2021.03.02.02.27.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 02:27:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sZzqDSzbsexD9Zh3aq/wd1p0b53KS/Yn8zf4kVHZSu8=; b=C3VIutOQ4snDMas8WGz4Eq0p3PRH6FNWNO92X7rY5mbfYX477lNZZGR4VVP3Ji8btv Fu/VuNP8Ha633E687ZFIC8LSvXQI44CP3k+PPrKQtAN3YOYO+UeSMTvmpyM6+pCZk6Fi JlW+vV340tpRIX6XHxZqcBpFAeBtekvvVN62Xr4+cQ3Qomi7SSEWsjW7ecL37ydyZXXA zr7Txx9+4uuKzEIj+VfTkJNEa6Nrt8SZcKCZXcfzjTtOtVHk4gKi3hwE1zNeHahQBGDH iWKnGxrkWlvbVaocp9Mtb2NjfGK8vt5Jwn1XD2fWnNsdDqPUp6UfTS4q/H8uRPaqh9hZ Y2PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sZzqDSzbsexD9Zh3aq/wd1p0b53KS/Yn8zf4kVHZSu8=; b=a5dCVHzVYDEO/bPoadxNsaFh4/zq+jGMreT6FienMi75B2OKiPEx/dq5V5GXMzFVC7 IRZD22RC6Tt2y+kzKX3G4qNotHzRUYDjaS7cXEuSUuIPuI3GsNk9Jkvhn9/0uMrlBPmB Mk/SnNzvvDZ040o6rUWL1fnn7sKsyrMtf4pUFWq8KEnHH6zqYlQw9tdcb6kLCjyj9Wgr 1b/FOzW2YK2PNJzs6a1keAkcUCPtxwA9fUhE/WETKc/DPWe0cLQGKGaOwe5+XLSOncZP FpGyZKbkUikjOSvvE9oGw7DsLyTlLNzgdKfME+U8tfNQPRTyPbYUZieJPU34Jea2kLBa z4ag== X-Gm-Message-State: AOAM533q3NicyAWZmxYjqsAU3KlkKkUSRMTg1uzVehm80DygXOULkkBD r0vl4mvWtRx6lAD8Vf6E4xs= X-Google-Smtp-Source: ABdhPJwqnVUa07ao13D+aDsQOtvYkhHlMbnQO3QZuuRT2q1H0Wx8pFQJeCXrskLyQpBsXETTbLtZSA== X-Received: by 2002:a50:fa92:: with SMTP id w18mr18340311edr.172.1614680868034; Tue, 02 Mar 2021 02:27:48 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Chris Wulff , qemu-ppc@nongnu.org, Marcel Apfelbaum , Greg Kurz , qemu-riscv@nongnu.org, Richard Henderson , Peter Maydell , Michael Walle , Palmer Dabbelt , Sarah Harris , Anthony Green , Eduardo Habkost , Bastian Koppelmann , Laurent Vivier , "Edgar E. Iglesias" , Claudio Fontana , Artyom Tarasenko , qemu-s390x@nongnu.org, Thomas Huth , Paolo Bonzini , Cornelia Huck , Taylor Simpson , Alistair Francis , Michael Rolnik , David Hildenbrand , Aleksandar Rikalo , Stafford Horne , Jiaxun Yang , Marek Vasut , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, David Gibson , Sagar Karandikar , Guan Xuetao , Max Filippov , Aurelien Jarno Subject: [PATCH 1/7] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG Date: Tue, 2 Mar 2021 11:27:31 +0100 Message-Id: <20210302102737.1031287-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210302102737.1031287-1-f4bug@amsat.org> References: <20210302102737.1031287-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Invert the #ifdef'ry to easily restrict tcg_exec_init() declaration to CONFIG_TCG. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/sysemu/tcg.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index 00349fb18a7..fddde2b6b9a 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -8,13 +8,15 @@ #ifndef SYSEMU_TCG_H #define SYSEMU_TCG_H =20 +#ifndef CONFIG_TCG +#define tcg_enabled() 0 +#else + void tcg_exec_init(unsigned long tb_size, int splitwx); =20 -#ifdef CONFIG_TCG extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) -#else -#define tcg_enabled() 0 -#endif + +#endif /* CONFIG_TCG */ =20 #endif --=20 2.26.2 From nobody Wed Nov 19 04:32:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.51 as permitted sender) client-ip=209.85.218.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614680877; cv=none; d=zohomail.com; s=zohoarc; b=mNvhev/dtKcCDrImgqHCkznNkhKDdho2WvWRhNeOOeiS2eZw222cxZWnapa186AFl6lfj6/vA+3NyIycRhF5bkDpsDzGul4GHGfWw0fCIB+icOWOOiesaE2Dm3vHI/QTAfK8pqAB6UAOELNfKmThnj5JwklQmAvCsN4j4oRnk5M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614680877; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CGeOm0jundDRZ1ITFIsaK/vmviPguy9Zg4MX9Tcr6Ys=; b=LStnKRNOetz+nEkswwdU8+yRYmgRN/3hLk9wed06uuZfsd6sl/DNibFCUF+B7Qibgikk2zfiHyA9UiiLlYk1ao6+jTplWCFh4tzeLUmeEpLiN6FmcggCC4igwpimm0FEHcM+PmIcUQiuHCQ3DgOTHWoEAHrWmzUZSA8JSl12K7E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) by mx.zohomail.com with SMTPS id 1614680877633181.58937020957092; Tue, 2 Mar 2021 02:27:57 -0800 (PST) Received: by mail-ej1-f51.google.com with SMTP id gt32so22699508ejc.6 for ; Tue, 02 Mar 2021 02:27:56 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id l61sm19862564edl.37.2021.03.02.02.27.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 02:27:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CGeOm0jundDRZ1ITFIsaK/vmviPguy9Zg4MX9Tcr6Ys=; b=FxCLDzNz6QdYCdDoY45WVE53tN9ZvFhJ/jwMOjKC8oaESrRhF7MIdsPRyP/PtAqm45 +BZBOuCyrnW5MPhOgWZOSzYbh3paahSGCRQ+BUaZ/UmeZwaxbQHWfRjDf0fp35Qy5HzU a5e3aNUGk0z3rcrp+QAVUaIgdfatSvwNKaa6crhUO6Eun7l2V52NtDQz8pqtKIGUwUZ5 UIbY5lwY9ekZLR2GAVIaVLQqThMZlAqVGbXaJK6LQZzC03NFPWcwpCqAPA7gUflYxFGE bglfG+HwMOaZQ0gTvyITMOTpR1XZLX0vzBOgSXey+rBfV9NgonVfkwBMPHQzeJjiLxUf +WKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=CGeOm0jundDRZ1ITFIsaK/vmviPguy9Zg4MX9Tcr6Ys=; b=Bnhye3sG9F5Iqvpuwmn2ghBsgRkvv1ym+bD1cD41zYzndSVMacx4dtVQquQtwDAPnj Yb2APBBXsVrc8iZwatFNBsAFsDYlOMwGE9znnW7yHeoJ5nQFlEQE64SZZtOU5hVmOTRT 0xjyt8CBApQ0BryEOevobuLw+X02YYCXnRu2OjkNgR9bv45jk6ss8nqI1hzS/Qu19REx jXwXKLXDCvxgTbj88KB8k7DrdRYPWFNZkjaHClagnGx91qqtlukdcT9dYFMTgwsLhVqI 0VNELmGSGUe8d0ys9DcCuqG6Td08yfQg21GzKZpsF3HS9s8qpkXL+KvhHGw8azoVKDOq tlnQ== X-Gm-Message-State: AOAM5303unA2+IJvI1cQthaGfnvDqi/o8X3D/GVoGMnZeaLdiMAEhooT Cfl2gSmWeb+2OYuPJ76aeYc= X-Google-Smtp-Source: ABdhPJzO+Jhty7XbLj0/S3RSIAptV1dIz+4q3kpugmP/ye1w47tvloBRfq5MthO7lqIoxawRs1hMKg== X-Received: by 2002:a17:906:1b54:: with SMTP id p20mr14852707ejg.307.1614680874854; Tue, 02 Mar 2021 02:27:54 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Chris Wulff , qemu-ppc@nongnu.org, Marcel Apfelbaum , Greg Kurz , qemu-riscv@nongnu.org, Richard Henderson , Peter Maydell , Michael Walle , Palmer Dabbelt , Sarah Harris , Anthony Green , Eduardo Habkost , Bastian Koppelmann , Laurent Vivier , "Edgar E. Iglesias" , Claudio Fontana , Artyom Tarasenko , qemu-s390x@nongnu.org, Thomas Huth , Paolo Bonzini , Cornelia Huck , Taylor Simpson , Alistair Francis , Michael Rolnik , David Hildenbrand , Aleksandar Rikalo , Stafford Horne , Jiaxun Yang , Marek Vasut , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, David Gibson , Sagar Karandikar , Guan Xuetao , Max Filippov , Aurelien Jarno Subject: [PATCH 2/7] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG Date: Tue, 2 Mar 2021 11:27:32 +0100 Message-Id: <20210302102737.1031287-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210302102737.1031287-1-f4bug@amsat.org> References: <20210302102737.1031287-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) qemu_tcg_mttcg_enabled() shouldn't not be used outside of TCG, restrict its declaration. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 9 --------- include/sysemu/tcg.h | 9 +++++++++ accel/tcg/cpu-exec.c | 1 + tcg/tcg.c | 1 + 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c005d3dc2d8..7f57e57464b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -454,15 +454,6 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cp= u) } } =20 -/** - * qemu_tcg_mttcg_enabled: - * Check whether we are running MultiThread TCG or not. - * - * Returns: %true if we are in MTTCG mode %false otherwise. - */ -extern bool mttcg_enabled; -#define qemu_tcg_mttcg_enabled() (mttcg_enabled) - /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index fddde2b6b9a..c16c13c3c69 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -17,6 +17,15 @@ void tcg_exec_init(unsigned long tb_size, int splitwx); extern bool tcg_allowed; #define tcg_enabled() (tcg_allowed) =20 +/** + * qemu_tcg_mttcg_enabled: + * Check whether we are running MultiThread TCG or not. + * + * Returns: %true if we are in MTTCG mode %false otherwise. + */ +extern bool mttcg_enabled; +#define qemu_tcg_mttcg_enabled() (mttcg_enabled) + #endif /* CONFIG_TCG */ =20 #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 16e4fe3ccd8..7e67ade35b9 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -39,6 +39,7 @@ #include "hw/i386/apic.h" #endif #include "sysemu/cpus.h" +#include "sysemu/tcg.h" #include "exec/cpu-all.h" #include "sysemu/cpu-timers.h" #include "sysemu/replay.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 63a12b197bf..4a4dac0bb3e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -65,6 +65,7 @@ #include "elf.h" #include "exec/log.h" #include "sysemu/sysemu.h" +#include "sysemu/tcg.h" =20 /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ --=20 2.26.2 From nobody Wed Nov 19 04:32:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.49 as permitted sender) client-ip=209.85.208.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614680883; cv=none; d=zohomail.com; s=zohoarc; b=ile+SoS7Ut1RvKdy7WzDtbixanbOkw0BR8ProAQIKTdkAsA0xlQgoOvSIxI73YwokfwAYpfiDbGr3WeCOWyKe9JRa802Oi1I1edIukq1BUdCds9GkdWAO8MeZzXPDOZuz3nZh1kMCaLh5wI8m1L6XKwUUa4htnBu3XDPwI+eLVA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614680883; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DgLtxhW6TCh0Vt3N87A01jn3z88UQCjsPYLiOsnHu/I=; b=AI+nqJHsMDHxeAIh4TASMeO7XZIGJoiZT4M3rBd41PmQJzXy8pLLfs8G2Y9mDgLhakiwIRbNyofInmkDCx9sCA0tKhkWuHIUoCdukyq5yU/mqAJH0Kr19gC2r3e/1hCK7muWz7hlqIQVUcOc+QkQK0Fv1oiTwyTw45MN6A1nDf8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) by mx.zohomail.com with SMTPS id 1614680883288978.4630011052269; Tue, 2 Mar 2021 02:28:03 -0800 (PST) Received: by mail-ed1-f49.google.com with SMTP id p1so20019506edy.2 for ; Tue, 02 Mar 2021 02:28:02 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id y11sm17365132ejd.72.2021.03.02.02.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 02:28:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DgLtxhW6TCh0Vt3N87A01jn3z88UQCjsPYLiOsnHu/I=; b=YlynJAlXKis3xlvlp8b6xXHhq0ZpkGKKUsa//dsaBGpYIxs1ee/4OjZMCRqF7puPiO MAwS7tiamXTZgyTqqn62PHPhe+SAStlPIrlUQ8L9EEeObQf+c3mthlsnxKdD3ndP5JbT P9s0lyYCSH7V43/m4zpPv9w/CPbWrmcgyuxJk3cNlUoaj5QarlqBGD9FWTk2PgLCjFI4 wcMnz4FQgr8jldgJckscDY7lK4QlWVWWR0eVlEdNgt4xXJHHVjPDXaj/F5EfwZ4b+KYk MrgHJS5hkpgMscFTsK3yejPKqySFuAIca00epUiNV/nilYnhDlsw6jt7rA/Q02j+4UNh jPZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DgLtxhW6TCh0Vt3N87A01jn3z88UQCjsPYLiOsnHu/I=; b=dKLZ45IKS3SK09qqtEqRaFojb236HQn7uLi/muhpK6yLSACNc6PUmXRQHwpstho/aN 7HLIIYiqFxDeC598cjB3JOdwV5FCswyrJcQehYcy/X8q7EW2qcxu0+EqBuWi/98C0G5A PnJZNAx0H9jZ0qWnYYpIM7MmKEK1DGHZ6B+byvRPU0CWsZ/6xn+SgcPMJ7r6CgNuzJrF 5WxZwUVMZ458f1v+tX7ROIqGsSLboumCz6glPqxjTcVmt2S14cirfMpA2Nf+s90a9Ndz PQHr/D6pHiedlS9k2a9BTJJF7YTV9D6Mwym2YCMXF5ZQbsDNQdX00J0bkyzikIaTZQAr x8ug== X-Gm-Message-State: AOAM530tVKGqwC63OSpTHjfv7Tu1bMTa75Nn2v6TTZaDykJhcI4NjiDP 20GQ20rcLyo86dtkxFJKXuE= X-Google-Smtp-Source: ABdhPJxtBe1JyuD647B2YHW3dOzrYqzhDwPtmH10I8kjKvgq6yC2fTZ+sviIRfIIHi1N2BTa1Atj0Q== X-Received: by 2002:a05:6402:1d39:: with SMTP id dh25mr18074868edb.282.1614680881533; Tue, 02 Mar 2021 02:28:01 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Chris Wulff , qemu-ppc@nongnu.org, Marcel Apfelbaum , Greg Kurz , qemu-riscv@nongnu.org, Richard Henderson , Peter Maydell , Michael Walle , Palmer Dabbelt , Sarah Harris , Anthony Green , Eduardo Habkost , Bastian Koppelmann , Laurent Vivier , "Edgar E. Iglesias" , Claudio Fontana , Artyom Tarasenko , qemu-s390x@nongnu.org, Thomas Huth , Paolo Bonzini , Cornelia Huck , Taylor Simpson , Alistair Francis , Michael Rolnik , David Hildenbrand , Aleksandar Rikalo , Stafford Horne , Jiaxun Yang , Marek Vasut , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, David Gibson , Sagar Karandikar , Guan Xuetao , Max Filippov , Aurelien Jarno Subject: [PATCH 3/7] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work Date: Tue, 2 Mar 2021 11:27:33 +0100 Message-Id: <20210302102737.1031287-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210302102737.1031287-1-f4bug@amsat.org> References: <20210302102737.1031287-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) There is only one CPUClass::has_work() ARM handler: arm_cpu_has_work(). Avoid a dereference by declaring it in "internals.h" and call it directly in the WFI helper. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 1 + target/arm/cpu.c | 2 +- target/arm/op_helper.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 05cebc8597c..1930be08828 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -172,6 +172,7 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); =20 +bool arm_cpu_has_work(CPUState *cs); #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b8bc89e71fc..d03607c2684 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -76,7 +76,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, } #endif /* CONFIG_TCG */ =20 -static bool arm_cpu_has_work(CPUState *cs) +bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 65cb37d088f..a4da6f4fde8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -289,7 +289,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) CPUState *cs =3D env_cpu(env); int target_el =3D check_wfx_trap(env, false); =20 - if (cpu_has_work(cs)) { + if (arm_cpu_has_work(cs)) { /* Don't bother to go into our "low power state" if * we would just wake up immediately. */ --=20 2.26.2 From nobody Wed Nov 19 04:32:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) client-ip=209.85.208.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614680890; cv=none; d=zohomail.com; s=zohoarc; b=YrLf/mY2b5aRr0E3tyaluekrLNc/JhY7va7PCVpcneNXMTkHKq2yswf9YeNb1GNG6bXTYXOsRaIoOJXMf1HIPCjEIDTzn33GVecIBXNY1ohMGp6Dr4pl5sWfLsM6V4of3I8TeiMcc4HqoXhL/UYJ9OyNx/LgAR+t3+TI4lI/bzc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614680890; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pjMzSGB3VrIz5KxFOb+6NNQW9N2HU550cTaWwJDZ/8A=; b=UunbZNtgwcIEGyYZahEDKsf7CWCUM2rDJHQ77dEA6etsAEKRj7laupR1ODelbTR/UMPA0OMIfXPcmKvGX9gsgS2mdYuhdnJvreND+AKfKN6jnpoGBg+aPCGF2sIjRU3lRqZta2Bffw7yl9BYZN5SveAR6TXmBlZloLg8ztJHJx4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) by mx.zohomail.com with SMTPS id 1614680890253599.1811016763135; Tue, 2 Mar 2021 02:28:10 -0800 (PST) Received: by mail-ed1-f43.google.com with SMTP id b7so10978500edz.8 for ; Tue, 02 Mar 2021 02:28:09 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id br13sm4397210ejb.87.2021.03.02.02.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 02:28:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pjMzSGB3VrIz5KxFOb+6NNQW9N2HU550cTaWwJDZ/8A=; b=G5cW5AURekQmkyrJ6xeJCQv3edRRJ8ZowZ2/mHrshd3o/HOnTy8r0r1Wkrd93i0mF+ mtmII75SZLx6cturdLpzSNbUx8PdoKT9uFWuDmfad1KxrZQI/LWFwv2TPlpn9YPCweFW 8IKjAQKz+PUtSpW56WCBYuIjNm76Gm43hEVc10r4j4Ah40F8Bf2xfMvqnX9meZ02ZnTN 6q6cem4/2iK5QTzWNuKHcpzkSq5CFfAG24luNZ+kj+BeIrcLKzbi86cmK/hfLEvTHWhc PkdROXLdXdue86d7PetG3j2V0RlsS0/FmKH0fhgHn6b2bQGdyDw3eQcuA7KXp8y3DnDH 6mFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pjMzSGB3VrIz5KxFOb+6NNQW9N2HU550cTaWwJDZ/8A=; b=UxV7Sali/rYDI5LGxKgzzYmHW3p8N9NHszawLN3jYiO7SPQeDc14SWOy+AmPCMU55f WzBvNSpGOXrJ9DL7Hl2STWH+jpwGZz2Ri3GxBWCLS4AT2qwcPiGVDv9nPgrdXywV2iEo nNbr9t/prG6de8nQpB4elc00aSWZepqiroOdIX/r/LNwaUCSZ/4yW4BGAwHH1+D4z8pm g5SlMqZFYcbudSFJNynUhQXUfcy9JK2BoQJ2Mws2t3O/yV5BP0vLfUGumkGfdI9eG+nS 8K1ksxFkulILWctWMpazNYs3wxiaKVgqhqJEPEeQ0AKBf47ahSZ5rV3kIq55CxU6jc9W 4y+g== X-Gm-Message-State: AOAM532iqmVoD3+ce0RWhzTH1sXpuCestPRKdtxNifkDF18Saq3UEej0 UxJmYW7dio50mNMIWPUarV4= X-Google-Smtp-Source: ABdhPJwrIthzky9aSjMOj2l7zu1IQyoGsU4Myc6vHwfgeJPx5pGxTKIGOWsBqqphOUFcNXqMeKFGDA== X-Received: by 2002:aa7:c9c9:: with SMTP id i9mr19642808edt.160.1614680888521; Tue, 02 Mar 2021 02:28:08 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Chris Wulff , qemu-ppc@nongnu.org, Marcel Apfelbaum , Greg Kurz , qemu-riscv@nongnu.org, Richard Henderson , Peter Maydell , Michael Walle , Palmer Dabbelt , Sarah Harris , Anthony Green , Eduardo Habkost , Bastian Koppelmann , Laurent Vivier , "Edgar E. Iglesias" , Claudio Fontana , Artyom Tarasenko , qemu-s390x@nongnu.org, Thomas Huth , Paolo Bonzini , Cornelia Huck , Taylor Simpson , Alistair Francis , Michael Rolnik , David Hildenbrand , Aleksandar Rikalo , Stafford Horne , Jiaxun Yang , Marek Vasut , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, David Gibson , Sagar Karandikar , Guan Xuetao , Max Filippov , Aurelien Jarno Subject: [PATCH 4/7] target/s390x: Move s390_cpu_has_work to excp_helper.c Date: Tue, 2 Mar 2021 11:27:34 +0100 Message-Id: <20210302102737.1031287-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210302102737.1031287-1-f4bug@amsat.org> References: <20210302102737.1031287-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We will restrict the s390_cpu_has_work() function to TCG. First declare it in "internal.h" and move it to excp_helper.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth --- target/s390x/internal.h | 1 + target/s390x/cpu.c | 17 ----------------- target/s390x/excp_helper.c | 18 ++++++++++++++++++ 3 files changed, 19 insertions(+), 17 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 11515bb6173..7184e38631c 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -263,6 +263,7 @@ ObjectClass *s390_cpu_class_by_name(const char *name); =20 =20 /* excp_helper.c */ +bool s390_cpu_has_work(CPUState *cs); void s390x_cpu_debug_excp_handler(CPUState *cs); void s390_cpu_do_interrupt(CPUState *cpu); bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d35eb39a1bb..91142db1097 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -56,23 +56,6 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr =3D value; } =20 -static bool s390_cpu_has_work(CPUState *cs) -{ - S390CPU *cpu =3D S390_CPU(cs); - - /* STOPPED cpus can never wake up */ - if (s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_LOAD && - s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_OPERATING) { - return false; - } - - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { - return false; - } - - return s390_cpu_has_int(cpu); -} - #if !defined(CONFIG_USER_ONLY) /* S390CPUClass::load_normal() */ static void s390_cpu_load_normal(CPUState *s) diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index ce16af394b1..64923ffb83a 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -28,12 +28,30 @@ #include "hw/s390x/ioinst.h" #include "exec/address-spaces.h" #include "tcg_s390x.h" +#include "qapi/qapi-types-machine.h" #ifndef CONFIG_USER_ONLY #include "sysemu/sysemu.h" #include "hw/s390x/s390_flic.h" #include "hw/boards.h" #endif =20 +bool s390_cpu_has_work(CPUState *cs) +{ + S390CPU *cpu =3D S390_CPU(cs); + + /* STOPPED cpus can never wake up */ + if (s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_LOAD && + s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_OPERATING) { + return false; + } + + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + return false; + } + + return s390_cpu_has_int(cpu); +} + void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra) { --=20 2.26.2 From nobody Wed Nov 19 04:32:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.47 as permitted sender) client-ip=209.85.218.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614680896; cv=none; d=zohomail.com; s=zohoarc; b=IuppF41vgshhnjPUVY7DUiDQIrfMpYJ72MHzgm/fY8OHdXY1KZ3+zrfAAs+bDUklOAhSz7MrMtKdbz7baZ9mKIeJqDQJ3MwxLWXQ8DQPsuw98zyi2iRf7ayJoi69hzJqE/sNZqXXelu3H+V0TBP4mVhY50YSjXd3a//9gZpOWIs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614680896; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=McvAeDL2KZLDlk5j6C9DReDRrG7DxVQ7/lNaBCKmKts=; b=O+9GhVtccieP+8awgBm5PNhHfPT1xOzTfNUUa0AY37MPFfSAXanXyQ/yrQOdG8Egz+ZAvD7C0HPK4AF66/gMFbVcM+zeUh1r0weJWqFPGANtHZEQTpz6Ect0Er/Rq5MSMfuuC3wD76pwI7IVUnEjf1DfbMsMD7gQn7Kjw9d9Au4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) by mx.zohomail.com with SMTPS id 1614680896973683.7958861342528; Tue, 2 Mar 2021 02:28:16 -0800 (PST) Received: by mail-ej1-f47.google.com with SMTP id mm21so33935039ejb.12 for ; Tue, 02 Mar 2021 02:28:16 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id v8sm8806466edq.76.2021.03.02.02.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 02:28:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=McvAeDL2KZLDlk5j6C9DReDRrG7DxVQ7/lNaBCKmKts=; b=G6+H7LPveVxfZYZ4gAzuBUFPrN0eUG3vlxbvzuWjj9a5rM1GHBKzhzr7xM0a03Negb M7K7lvV84PeIbZuTo4kWojNmt50zInB7lqPRMqLKGUFlR9h5PwRFGYJvmYXSbDGXkbez 8JkR+MBODwLDJe2NGYoKuJh8jYdABi74jL5t0y+DiuRmp6kQ6YnTKWlN/d+rMzi/SPdc ZRBvTVv7yhTzlEgHn0IAjCUpicK5mYWfnFOs2OvxcajSzsXaYwf3Zr/hW8/1nOqDCreu bcrKPbr93FI215bxmZ/o4L96+mcy14rQcvP9eE7BR8sfdmnm6H8fnF6eiyY/3MD0Hsqx 1IVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=McvAeDL2KZLDlk5j6C9DReDRrG7DxVQ7/lNaBCKmKts=; b=KRww46uOA8hOaOvzOzCeN4vQh25AuEhjv1KLyvbOHbzWhgQ677JA5lwlswxpfYm+uI 8w9OqFFTmFt0b0ghvbd+HrV/5NWvokijBpl8bJdMZLRYRRZYS9jHmIgvN0x65JyB0AWI Y8cEJlGW91UALtwYXvwIe7oCtQ6O2cYzWLXUit+eDsJ5TV0xSqGtQjh2gcRw8fP9RoSa AS43JeXgVPYkbFnNsKBtv4rnTsCNJpkgO0KBeCxNLbE3+PWEGzgc8un5EXMtUg1DNV69 wc7MFskYJ73D9PympXlDICcxh4v70J/8wr4w/CcYVxYybwuyD9RKOTvQd0IwgBhoa908 SXFQ== X-Gm-Message-State: AOAM530XQGOrbzAEUDtzUm0cYcyZ8VXmUuMRWF7nJsBR1chapgLV/oUT mGfW0CPDNngozUJ/WKGrY6Y= X-Google-Smtp-Source: ABdhPJw//ziXTJz7Q/EFqJpyZ7pQZeJ1NZOZgWZypYXWr+13jH12R/7pcyIqxOe7iCzcxINofU5HJA== X-Received: by 2002:a17:906:73c2:: with SMTP id n2mr20178765ejl.224.1614680895260; Tue, 02 Mar 2021 02:28:15 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Chris Wulff , qemu-ppc@nongnu.org, Marcel Apfelbaum , Greg Kurz , qemu-riscv@nongnu.org, Richard Henderson , Peter Maydell , Michael Walle , Palmer Dabbelt , Sarah Harris , Anthony Green , Eduardo Habkost , Bastian Koppelmann , Laurent Vivier , "Edgar E. Iglesias" , Claudio Fontana , Artyom Tarasenko , qemu-s390x@nongnu.org, Thomas Huth , Paolo Bonzini , Cornelia Huck , Taylor Simpson , Alistair Francis , Michael Rolnik , David Hildenbrand , Aleksandar Rikalo , Stafford Horne , Jiaxun Yang , Marek Vasut , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, David Gibson , Sagar Karandikar , Guan Xuetao , Max Filippov , Aurelien Jarno Subject: [RFC PATCH 5/7] cpu: Declare cpu_has_work() in 'sysemu/tcg.h' Date: Tue, 2 Mar 2021 11:27:35 +0100 Message-Id: <20210302102737.1031287-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210302102737.1031287-1-f4bug@amsat.org> References: <20210302102737.1031287-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We can only check if a vCPU has work with TCG. Move the cpu_has_work() prototype to "sysemu/tcg.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- RFC: could another accelerator do that? can we rename this tcg_vcpu_has_work()? --- include/hw/core/cpu.h | 16 ---------------- include/sysemu/tcg.h | 11 +++++++++++ accel/tcg/cpu-exec.c | 7 +++++++ softmmu/cpus.c | 1 + 4 files changed, 19 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 7f57e57464b..ed23ed9f5fb 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -670,22 +670,6 @@ CPUState *cpu_create(const char *typename); */ const char *parse_cpu_option(const char *cpu_option); =20 -/** - * cpu_has_work: - * @cpu: The vCPU to check. - * - * Checks whether the CPU has work to do. - * - * Returns: %true if the CPU has work, %false otherwise. - */ -static inline bool cpu_has_work(CPUState *cpu) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - g_assert(cc->has_work); - return cc->has_work(cpu); -} - /** * qemu_cpu_is_self: * @cpu: The vCPU to check against. diff --git a/include/sysemu/tcg.h b/include/sysemu/tcg.h index c16c13c3c69..3d46b0a7a93 100644 --- a/include/sysemu/tcg.h +++ b/include/sysemu/tcg.h @@ -10,6 +10,7 @@ =20 #ifndef CONFIG_TCG #define tcg_enabled() 0 +#define cpu_has_work(cpu) false #else =20 void tcg_exec_init(unsigned long tb_size, int splitwx); @@ -26,6 +27,16 @@ extern bool tcg_allowed; extern bool mttcg_enabled; #define qemu_tcg_mttcg_enabled() (mttcg_enabled) =20 +/** + * cpu_has_work: + * @cpu: The vCPU to check. + * + * Checks whether the CPU has work to do. + * + * Returns: %true if the CPU has work, %false otherwise. + */ +bool cpu_has_work(CPUState *cpu); + #endif /* CONFIG_TCG */ =20 #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 7e67ade35b9..b9ce36e59e2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -447,6 +447,13 @@ static inline TranslationBlock *tb_find(CPUState *cpu, return tb; } =20 +bool cpu_has_work(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + return cc->has_work(cpu); +} + static inline bool cpu_handle_halt(CPUState *cpu) { if (cpu->halted) { diff --git a/softmmu/cpus.c b/softmmu/cpus.c index a7ee431187a..548ab9236f1 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -42,6 +42,7 @@ #include "sysemu/runstate.h" #include "sysemu/cpu-timers.h" #include "sysemu/whpx.h" +#include "sysemu/tcg.h" #include "hw/boards.h" #include "hw/hw.h" =20 --=20 2.26.2 From nobody Wed Nov 19 04:32:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.47 as permitted sender) client-ip=209.85.218.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614680904; cv=none; d=zohomail.com; s=zohoarc; b=gv03klirKWLj00HIxXkEGBv3b6a5rUD+pPi0y0zH5k1DHNsPquI5SR1WCOj6eDiz+RmyVA5N6u7GIVHaw4ufoXiCDSyGlAdgN2lBOjoQBYoP9aVDDc3f5eVSsLH5LN66cLdFduZ46ZH64HhvWJC7SqBrTSsCW6QqOtAeWs+jNDA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614680904; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vaKqMBvLu80pId+FLJUff7aDT6x+WJI57IlfMPY7/Ho=; b=XyfSh9w/JtjRYPVVhkYBLHIMoFrR969YMkUJ8ZTQIYsR+tdz8Fvk6D1HN3sdo0U6yf9aMy1fR9iZgpJA36DEXf99QuGUqaGGiTHXk+pdnyilcPkq2ZvOdgjtoHNvteqrH2/IgxbwAlPYWC6xT2A3aIp7bj1TMvtNuprBMeXc28M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) by mx.zohomail.com with SMTPS id 1614680904134371.5031119838443; Tue, 2 Mar 2021 02:28:24 -0800 (PST) Received: by mail-ej1-f47.google.com with SMTP id hs11so34253386ejc.1 for ; Tue, 02 Mar 2021 02:28:23 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id w18sm15755455ejn.23.2021.03.02.02.28.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 02:28:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vaKqMBvLu80pId+FLJUff7aDT6x+WJI57IlfMPY7/Ho=; b=fKX2acxyv1a5qhtMn86Eqy7EjUE0QSPM4uJXOFO+MvqFcJ2a56U6zrqBcQy/LZRAIz gu4334iLpSyTsz2WDIgXN0POLMza0CvS8gTWb8Uk8TG9jixBMfXnmlwqEsIz2/tpXV0T /3vrhx7+gPbQOHTXy07PYXG3vZ+FoMVAntXm0F9VpFeb5UOUteHGIteYRhh1NmPNEQMS PkWLWvVogStxMtVVxm2H5ZgzKINdkEZPXcs9CiNbOHGl7BcLBtrruRzAU1ixxMJnNosl 2+jpvnrzjEYGkwab7I6K7ic5HAGRELJ2qYAR6EpS3zCQFiUUeWENleFOm7ZlK0qPtCZl ZytA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vaKqMBvLu80pId+FLJUff7aDT6x+WJI57IlfMPY7/Ho=; b=IrO1Xu+airSqCjvr3hsl2n5qKSpqnzttLKMeh6NRXz8BJy7K219hzk4Z6VilartC86 JsfdrkLEHwW/zYnozn+vOexiNqdVi3fZhhFSBtNAaaaGmvKpl531y2UpH/WwiFzuKcuM qj/CsUSYEHFppu6K9YSIcGLL7EvgignK9wCq4tKJF1Ge+zbiRFgJ2vT+fHfmvo4JhEHs YGUJFqziotz/pAyxBIxAvHVwYdXiEUVD5++1QmVcrEmnKbs+iFVPPFcNApV7A7ygXYcH qCOvjuHR7snDUguFj9+NM0iMY2H4cwd8UOBWWSPOmZiVxXS2GE75/l3Vo7EledvRJXxm QQeQ== X-Gm-Message-State: AOAM531qrF6lWdULl23bkVt5D+Ete6/rQqTPpLPvBrGqu//FeEq8r4De wE6bIvCjSL1EtWSWDae+P20= X-Google-Smtp-Source: ABdhPJynDT6wQbQ2D5RJ/zfvYR4ZTU8jtA7T3hrNi4qPOmq02BIY8R5H6zdS7tUkRxC4qWdHAjQXaA== X-Received: by 2002:a17:906:7754:: with SMTP id o20mr385068ejn.209.1614680902151; Tue, 02 Mar 2021 02:28:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Chris Wulff , qemu-ppc@nongnu.org, Marcel Apfelbaum , Greg Kurz , qemu-riscv@nongnu.org, Richard Henderson , Peter Maydell , Michael Walle , Palmer Dabbelt , Sarah Harris , Anthony Green , Eduardo Habkost , Bastian Koppelmann , Laurent Vivier , "Edgar E. Iglesias" , Claudio Fontana , Artyom Tarasenko , qemu-s390x@nongnu.org, Thomas Huth , Paolo Bonzini , Cornelia Huck , Taylor Simpson , Alistair Francis , Michael Rolnik , David Hildenbrand , Aleksandar Rikalo , Stafford Horne , Jiaxun Yang , Marek Vasut , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, David Gibson , Sagar Karandikar , Guan Xuetao , Max Filippov , Aurelien Jarno Subject: [RFC PATCH 6/7] cpu: Move CPUClass::has_work() to TCGCPUOps Date: Tue, 2 Mar 2021 11:27:36 +0100 Message-Id: <20210302102737.1031287-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210302102737.1031287-1-f4bug@amsat.org> References: <20210302102737.1031287-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We can only check if a vCPU has work with TCG. Restrict the has_work() handler to TCG by moving it to the TCGCPUOps structure, and adapt all the targets. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Taylor Simpson --- RFC: PPC target incomplete --- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 4 ++++ accel/tcg/cpu-exec.c | 2 +- hw/core/cpu.c | 6 ------ target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 3 ++- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 7 +------ target/i386/tcg/tcg-cpu.c | 6 ++++++ target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 29 files changed, 36 insertions(+), 38 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ed23ed9f5fb..cfbc581c40e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -86,7 +86,6 @@ struct AccelCPUClass; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @has_work: Callback for checking if there is work to do. * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. Non-configurab= le * CPUs can use the default implementation of this method. This method sho= uld @@ -149,7 +148,6 @@ struct CPUClass { void (*parse_features)(const char *typename, char *str, Error **errp); =20 int reset_dump_flags; - bool (*has_work)(CPUState *cpu); bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 72d791438c2..f5d44ba59f3 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -19,6 +19,10 @@ struct TCGCPUOps { * Called when the first CPU is realized. */ void (*initialize)(void); + /** + * @has_work: Callback for checking if there is work to do + */ + bool (*has_work)(CPUState *cpu); /** * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b9ce36e59e2..1ea39b3b029 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -451,7 +451,7 @@ bool cpu_has_work(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - return cc->has_work(cpu); + return cc->tcg_ops->has_work(cpu); } =20 static inline bool cpu_handle_halt(CPUState *cpu) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..3110867c3a3 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -261,11 +261,6 @@ static void cpu_common_reset(DeviceState *dev) } } =20 -static bool cpu_common_has_work(CPUState *cs) -{ - return false; -} - ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) { CPUClass *cc =3D CPU_CLASS(object_class_by_name(typename)); @@ -397,7 +392,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) =20 k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; - k->has_work =3D cpu_common_has_work; k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->write_elf32_qemunote =3D cpu_common_write_elf32_qemunote; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27192b62e22..06728b7c182 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -210,6 +210,7 @@ static void alpha_cpu_initfn(Object *obj) =20 static struct TCGCPUOps alpha_tcg_ops =3D { .initialize =3D alpha_translate_init, + .has_work =3D alpha_cpu_has_work, .cpu_exec_interrupt =3D alpha_cpu_exec_interrupt, .tlb_fill =3D alpha_cpu_tlb_fill, =20 @@ -230,7 +231,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) &acc->parent_realize); =20 cc->class_by_name =3D alpha_cpu_class_by_name; - cc->has_work =3D alpha_cpu_has_work; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d03607c2684..09dea233af9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2263,6 +2263,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) #ifdef CONFIG_TCG static struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, + .has_work =3D arm_cpu_has_work, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, @@ -2291,7 +2292,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); =20 cc->class_by_name =3D arm_cpu_class_by_name; - cc->has_work =3D arm_cpu_has_work; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; cc->gdb_read_register =3D arm_cpu_gdb_read_register; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f4596932ba..d3fe26ea94d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -188,6 +188,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) =20 static struct TCGCPUOps avr_tcg_ops =3D { .initialize =3D avr_cpu_tcg_init, + .has_work =3D avr_cpu_has_work, .synchronize_from_tb =3D avr_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, .tlb_fill =3D avr_cpu_tlb_fill, @@ -208,7 +209,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) =20 cc->class_by_name =3D avr_cpu_class_by_name; =20 - cc->has_work =3D avr_cpu_has_work; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed983380fca..1f074c835a5 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -197,6 +197,7 @@ static void cris_cpu_initfn(Object *obj) =20 static struct TCGCPUOps crisv10_tcg_ops =3D { .initialize =3D cris_initialize_crisv10_tcg, + .has_work =3D cris_cpu_has_work, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .tlb_fill =3D cris_cpu_tlb_fill, =20 @@ -207,6 +208,7 @@ static struct TCGCPUOps crisv10_tcg_ops =3D { =20 static struct TCGCPUOps crisv32_tcg_ops =3D { .initialize =3D cris_initialize_tcg, + .has_work =3D cris_cpu_has_work, .cpu_exec_interrupt =3D cris_cpu_exec_interrupt, .tlb_fill =3D cris_cpu_tlb_fill, =20 @@ -286,7 +288,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); =20 cc->class_by_name =3D cris_cpu_class_by_name; - cc->has_work =3D cris_cpu_has_work; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b0b3040dd13..d597fe12cdf 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -268,6 +268,7 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr addres= s, int size, =20 static struct TCGCPUOps hexagon_tcg_ops =3D { .initialize =3D hexagon_translate_init, + .has_work =3D hexagon_cpu_has_work, .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, .tlb_fill =3D hexagon_tlb_fill, }; @@ -284,7 +285,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void= *data) device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_rese= t); =20 cc->class_by_name =3D hexagon_cpu_class_by_name; - cc->has_work =3D hexagon_cpu_has_work; cc->dump_state =3D hexagon_dump_state; cc->set_pc =3D hexagon_cpu_set_pc; cc->gdb_read_register =3D hexagon_gdb_read_register; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d8fad52d1fe..60769da0d2d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -135,6 +135,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 static struct TCGCPUOps hppa_tcg_ops =3D { .initialize =3D hppa_translate_init, + .has_work =3D hppa_cpu_has_work, .synchronize_from_tb =3D hppa_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D hppa_cpu_exec_interrupt, .tlb_fill =3D hppa_cpu_tlb_fill, @@ -155,7 +156,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) &acc->parent_realize); =20 cc->class_by_name =3D hppa_cpu_class_by_name; - cc->has_work =3D hppa_cpu_has_work; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6a53446e6a5..d6f757a6251 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7171,6 +7171,7 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip =3D value; } =20 +/* FIXME TCG only? */ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -7213,11 +7214,6 @@ int x86_cpu_pending_interrupt(CPUState *cs, int inte= rrupt_request) return 0; } =20 -static bool x86_cpu_has_work(CPUState *cs) -{ - return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; -} - static void x86_disas_set_info(CPUState *cs, disassemble_info *info) { X86CPU *cpu =3D X86_CPU(cs); @@ -7404,7 +7400,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; - cc->has_work =3D x86_cpu_has_work; =20 #ifdef CONFIG_TCG tcg_cpu_common_class_init(cc); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 1e125d2175a..007a05c8e57 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -57,10 +57,16 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, cpu->env.eip =3D tb->pc - tb->cs_base; } =20 +static bool x86_cpu_has_work(CPUState *cs) +{ + return x86_cpu_pending_interrupt(cs, cs->interrupt_request) !=3D 0; +} + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps x86_tcg_ops =3D { .initialize =3D tcg_x86_init, + .has_work =3D x86_cpu_has_work, .synchronize_from_tb =3D x86_cpu_synchronize_from_tb, .cpu_exec_enter =3D x86_cpu_exec_enter, .cpu_exec_exit =3D x86_cpu_exec_exit, diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c23d72874c0..a7eded771f0 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -214,6 +214,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 static struct TCGCPUOps lm32_tcg_ops =3D { .initialize =3D lm32_translate_init, + .has_work =3D lm32_cpu_has_work, .cpu_exec_interrupt =3D lm32_cpu_exec_interrupt, .tlb_fill =3D lm32_cpu_tlb_fill, .debug_excp_handler =3D lm32_debug_excp_handler, @@ -234,7 +235,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset); =20 cc->class_by_name =3D lm32_cpu_class_by_name; - cc->has_work =3D lm32_cpu_has_work; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; cc->gdb_read_register =3D lm32_cpu_gdb_read_register; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 37d2ed9dc79..a023e763b29 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -506,6 +506,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 static struct TCGCPUOps m68k_tcg_ops =3D { .initialize =3D m68k_tcg_init, + .has_work =3D m68k_cpu_has_work, .cpu_exec_interrupt =3D m68k_cpu_exec_interrupt, .tlb_fill =3D m68k_cpu_tlb_fill, =20 @@ -526,7 +527,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D m68k_cpu_class_by_name; - cc->has_work =3D m68k_cpu_has_work; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 433ba202037..471a50c3d14 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -356,6 +356,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 static struct TCGCPUOps mb_tcg_ops =3D { .initialize =3D mb_tcg_init, + .has_work =3D mb_cpu_has_work, .synchronize_from_tb =3D mb_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .tlb_fill =3D mb_cpu_tlb_fill, @@ -378,7 +379,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D mb_cpu_class_by_name; - cc->has_work =3D mb_cpu_has_work; =20 cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bf70c77295f..e654ce7d6bb 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -688,6 +688,7 @@ static Property mips_cpu_properties[] =3D { */ static struct TCGCPUOps mips_tcg_ops =3D { .initialize =3D mips_tcg_init, + .has_work =3D mips_cpu_has_work, .synchronize_from_tb =3D mips_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .tlb_fill =3D mips_cpu_tlb_fill, @@ -713,7 +714,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) device_class_set_props(dc, mips_cpu_properties); =20 cc->class_by_name =3D mips_cpu_class_by_name; - cc->has_work =3D mips_cpu_has_work; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->gdb_read_register =3D mips_cpu_gdb_read_register; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 83bec34d36c..0b14ded0b70 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -98,6 +98,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) =20 static struct TCGCPUOps moxie_tcg_ops =3D { .initialize =3D moxie_translate_init, + .has_work =3D moxie_cpu_has_work, .tlb_fill =3D moxie_cpu_tlb_fill, =20 #ifndef CONFIG_USER_ONLY @@ -117,7 +118,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D moxie_cpu_class_by_name; =20 - cc->has_work =3D moxie_cpu_has_work; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a389..d536a75e51e 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -211,6 +211,7 @@ static Property nios2_properties[] =3D { =20 static struct TCGCPUOps nios2_tcg_ops =3D { .initialize =3D nios2_tcg_init, + .has_work =3D nios2_cpu_has_work, .cpu_exec_interrupt =3D nios2_cpu_exec_interrupt, .tlb_fill =3D nios2_cpu_tlb_fill, =20 @@ -232,7 +233,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); =20 cc->class_by_name =3D nios2_cpu_class_by_name; - cc->has_work =3D nios2_cpu_has_work; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46b..61932d83515 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -178,6 +178,7 @@ static void openrisc_any_initfn(Object *obj) =20 static struct TCGCPUOps openrisc_tcg_ops =3D { .initialize =3D openrisc_translate_init, + .has_work =3D openrisc_cpu_has_work, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .tlb_fill =3D openrisc_cpu_tlb_fill, =20 @@ -197,7 +198,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_res= et); =20 cc->class_by_name =3D openrisc_cpu_class_by_name; - cc->has_work =3D openrisc_cpu_has_work; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16f1a342388..d1cb933e35b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -584,6 +584,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 static struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, + .has_work =3D riscv_cpu_has_work, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .tlb_fill =3D riscv_cpu_tlb_fill, @@ -607,7 +608,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D riscv_cpu_class_by_name; - cc->has_work =3D riscv_cpu_has_work; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26b..caeed1bb50e 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -177,6 +177,7 @@ static void rx_cpu_init(Object *obj) =20 static struct TCGCPUOps rx_tcg_ops =3D { .initialize =3D rx_translate_init, + .has_work =3D rx_cpu_has_work, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, .tlb_fill =3D rx_cpu_tlb_fill, @@ -198,7 +199,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) &rcc->parent_reset); =20 cc->class_by_name =3D rx_cpu_class_by_name; - cc->has_work =3D rx_cpu_has_work; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 91142db1097..bf760cb423d 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -465,6 +465,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 static struct TCGCPUOps s390_tcg_ops =3D { .initialize =3D s390x_translate_init, + .has_work =3D s390_cpu_has_work, .tlb_fill =3D s390_cpu_tlb_fill, =20 #if !defined(CONFIG_USER_ONLY) @@ -493,7 +494,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) #endif scc->reset =3D s390_cpu_reset; cc->class_by_name =3D s390_cpu_class_by_name, - cc->has_work =3D s390_cpu_has_work; cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; cc->gdb_read_register =3D s390_cpu_gdb_read_register; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ac65c88f1f8..2f62003d691 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -227,6 +227,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { =20 static struct TCGCPUOps superh_tcg_ops =3D { .initialize =3D sh4_translate_init, + .has_work =3D superh_cpu_has_work, .synchronize_from_tb =3D superh_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .tlb_fill =3D superh_cpu_tlb_fill, @@ -250,7 +251,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset= ); =20 cc->class_by_name =3D superh_cpu_class_by_name; - cc->has_work =3D superh_cpu_has_work; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; cc->gdb_read_register =3D superh_cpu_gdb_read_register; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index aece2c7dc83..849a88432d0 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -853,6 +853,7 @@ static Property sparc_cpu_properties[] =3D { =20 static struct TCGCPUOps sparc_tcg_ops =3D { .initialize =3D sparc_tcg_init, + .has_work =3D sparc_cpu_has_work, .synchronize_from_tb =3D sparc_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .tlb_fill =3D sparc_cpu_tlb_fill, @@ -879,7 +880,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; - cc->has_work =3D sparc_cpu_has_work; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index d969c2f1331..3f762912276 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -138,6 +138,7 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int= interrupt_request) =20 static struct TCGCPUOps tilegx_tcg_ops =3D { .initialize =3D tilegx_tcg_init, + .has_work =3D tilegx_cpu_has_work, .cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt, .tlb_fill =3D tilegx_cpu_tlb_fill, =20 @@ -158,7 +159,6 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset= ); =20 cc->class_by_name =3D tilegx_cpu_class_by_name; - cc->has_work =3D tilegx_cpu_has_work; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; cc->gdb_num_core_regs =3D 0; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcba..f5cc637d342 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -146,6 +146,7 @@ static void tc27x_initfn(Object *obj) =20 static struct TCGCPUOps tricore_tcg_ops =3D { .initialize =3D tricore_tcg_init, + .has_work =3D tricore_cpu_has_work, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .tlb_fill =3D tricore_cpu_tlb_fill, }; @@ -161,7 +162,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_rese= t); cc->class_by_name =3D tricore_cpu_class_by_name; - cc->has_work =3D tricore_cpu_has_work; =20 cc->gdb_read_register =3D tricore_cpu_gdb_read_register; cc->gdb_write_register =3D tricore_cpu_gdb_write_register; diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 0258884f845..7220ecf5b60 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -124,6 +124,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { =20 static struct TCGCPUOps uc32_tcg_ops =3D { .initialize =3D uc32_translate_init, + .has_work =3D uc32_cpu_has_work, .cpu_exec_interrupt =3D uc32_cpu_exec_interrupt, .tlb_fill =3D uc32_cpu_tlb_fill, =20 @@ -142,7 +143,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) &ucc->parent_realize); =20 cc->class_by_name =3D uc32_cpu_class_by_name; - cc->has_work =3D uc32_cpu_has_work; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e2b2c7a71c1..7c30ec3578b 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -185,6 +185,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { =20 static struct TCGCPUOps xtensa_tcg_ops =3D { .initialize =3D xtensa_translate_init, + .has_work =3D xtensa_cpu_has_work, .cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt, .tlb_fill =3D xtensa_cpu_tlb_fill, .debug_excp_handler =3D xtensa_breakpoint_handler, @@ -208,7 +209,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset= ); =20 cc->class_by_name =3D xtensa_cpu_class_by_name; - cc->has_work =3D xtensa_cpu_has_work; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index e7324e85cdb..f790daefa65 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10848,6 +10848,7 @@ static Property ppc_cpu_properties[] =3D { =20 static struct TCGCPUOps ppc_tcg_ops =3D { .initialize =3D ppc_translate_init, + .has_work =3D ppc_cpu_has_work, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .tlb_fill =3D ppc_cpu_tlb_fill, =20 @@ -10877,7 +10878,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); =20 cc->class_by_name =3D ppc_cpu_class_by_name; - cc->has_work =3D ppc_cpu_has_work; cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; cc->set_pc =3D ppc_cpu_set_pc; --=20 2.26.2 From nobody Wed Nov 19 04:32:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.54 as permitted sender) client-ip=209.85.208.54; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id n5sm18749468edw.7.2021.03.02.02.28.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 02:28:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L7WVeo3JeR2z3AVtoQK/XR045Ce4Y6oo2FncIeho75k=; b=PM9Lz9wDcwQWHcyx7h3aFKV73QDzAg2Km6FE13Cp4h/HL3Oy+Zt64BcozCUyhdmpiP s61v76fYKsD/ooPiY5BSLje8+vQge/ONQ9Z+/x3rtVHdmv2s8JnyHkPEi9T6zqSdIwPq 1aNpvmmtLqahcUi+bB2tQrr5kZEpPnxRZdeUhMSTmp/6b/IbOmFsKuZoXdnpttsZqkSd 6kc01SeZKffU0so3uZhpLKnsqJxgyuxgUkQmg7iKeHAPWo8QCDmsY/g9avbIfTQn4TN2 avZvDa0XjnEl7aAmGEdnGHZcOkjT1fv+LFlLEWyTg0lDtNbsYeT5u+pqGxAq4zwW9bfg YddA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=L7WVeo3JeR2z3AVtoQK/XR045Ce4Y6oo2FncIeho75k=; b=G5ExYOa1m2Rh1DNL6wB4eqGoWaAoAgGWDfFOUGNBrDd+FZ3EhV/fWQPYFqHCv7DhVv 2RWJp8DPT8bgNyXXa3eRJ7VhbRJn6d2DfPJ+GeYh5Q/KeGBCfmrlZRQIIr7DANRHB8ds G52MNthAHpMPidMelLP9Xfk1sLloqZ8xYT7HMiE27u1QcuwVuDKU6iDTo8LxkZQPxnWv 0LVQZHJaRfN3HMGIOPqVhCmjk0gHl1IoIFyeeNmzwae2u0nbhj7c3bHRxJqF1Qy1tShA pupDL8Px8pRKmwl6Cit1sl8c9eK5nZPb4gpNwnm9/EzS1FWF7nBmK4k/kEw0elFDsUc5 B2zA== X-Gm-Message-State: AOAM532dNCszT+SGQrnLVYhL1bSKN6Ngh0QKMDTD+XHHp/DhSReJ2IaK YXbfAjEjoYAiu3PXpBVdW60= X-Google-Smtp-Source: ABdhPJyGscw33yFx55I9b4J7hvm2PunNL+y6O3v/yS01cO/4cphsBbkP4hk3zNUmiP3gcsqTPvWaWw== X-Received: by 2002:aa7:c609:: with SMTP id h9mr20457329edq.256.1614680908765; Tue, 02 Mar 2021 02:28:28 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , Chris Wulff , qemu-ppc@nongnu.org, Marcel Apfelbaum , Greg Kurz , qemu-riscv@nongnu.org, Richard Henderson , Peter Maydell , Michael Walle , Palmer Dabbelt , Sarah Harris , Anthony Green , Eduardo Habkost , Bastian Koppelmann , Laurent Vivier , "Edgar E. Iglesias" , Claudio Fontana , Artyom Tarasenko , qemu-s390x@nongnu.org, Thomas Huth , Paolo Bonzini , Cornelia Huck , Taylor Simpson , Alistair Francis , Michael Rolnik , David Hildenbrand , Aleksandar Rikalo , Stafford Horne , Jiaxun Yang , Marek Vasut , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, David Gibson , Sagar Karandikar , Guan Xuetao , Max Filippov , Aurelien Jarno Subject: [PATCH 7/7] target/arm: Restrict arm_cpu_has_work() to TCG Date: Tue, 2 Mar 2021 11:27:37 +0100 Message-Id: <20210302102737.1031287-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210302102737.1031287-1-f4bug@amsat.org> References: <20210302102737.1031287-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) arm_cpu_has_work() is only used from TCG. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 2 +- target/arm/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1930be08828..db81db9bf57 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -172,8 +172,8 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); =20 -bool arm_cpu_has_work(CPUState *cs); #ifdef CONFIG_TCG +bool arm_cpu_has_work(CPUState *cs); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 09dea233af9..0b4727bd7e9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -74,7 +74,6 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, env->regs[15] =3D tb->pc; } } -#endif /* CONFIG_TCG */ =20 bool arm_cpu_has_work(CPUState *cs) { @@ -86,6 +85,7 @@ bool arm_cpu_has_work(CPUState *cs) | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_EXITTB); } +#endif /* CONFIG_TCG */ =20 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque) --=20 2.26.2