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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id f9sm3826592eds.41.2021.03.01.13.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:51:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nOq5iyMcYnp2lkKz6qC+70BZoqGGdKahRqfZnxYC4Rc=; b=t0pGzOKnf5ZpOvCm5Y28TWHGQpYkmR/sdTOpQHUs5O4GMP7ySv6AzuyQ24ZR+f2mTQ disBbPz6o0XYwBpg//74hQCCoWYXrbauE5Kr65Z5cu2xGjdSHLgl67OcgWa3XUibhB5N +3bIk7zRjbFrhVFgjas7cTK+JKf8bsqGTzUL+ESJTmomp0EQ5GkcnsZzAGxcbWLBzRiZ tj9tmebrkwSY3Sjw9FwRKpiQo3K8xAKvUjy0oDROaKddgVW5TDh8F9tO6U7ymuuMExbd oVrpZK5uZsLJQNbUojsfG5SFX55PddMwqCfIdEvPwnWoFhX+YLag4BL6Z0I2UsN36X0i +acw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nOq5iyMcYnp2lkKz6qC+70BZoqGGdKahRqfZnxYC4Rc=; b=Rma+3OaErCm/Ih81uu6RS2DwfKaX3ASNbxt9QO/E337PERPW8EU2Xb8Id5wDa+3YdL GbvTo0aY6SnFXbE6Soh+ncVV9FmZGUbqXV9CO1yRplXvEJiWK18X2btOBit2JQqOXaAu VG/vxy+DPY7RzkRLqRYpWRAJCSB/SWjL4T0+R7PvNUPEE7Z8DiUBencNvWJJgbK56vOz rP7wOkHbBT4NjhJympS/tXr9fDEIlTdg15Xc5CkAJw3AL6BEQgA3i1dovdSg2go9+3sd YDqLPad8XqId5EQHX3gsxxUGKKEwLpVONZqQ/ShVJcRPZ/5gaxflJa0sx/9qLJVl6Xrj a+Tw== X-Gm-Message-State: AOAM531NccxDUrTSW4tRKG5mymNqU5XNZMaETb5DbDLZe+9g7ik9hVjD Hq+cR+XfIaY6TLJnP5gLW9o= X-Google-Smtp-Source: ABdhPJyWMay7P0ghWikCHhjxO86ac7zkkAoemeVHWX8eBYuV9qNHmH8SkdUTGRiN1Qj0l4BPY+uE6A== X-Received: by 2002:a17:906:d554:: with SMTP id cr20mr1386495ejc.61.1614635481843; Mon, 01 Mar 2021 13:51:21 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 01/17] target: Set CPUClass::vmsd instead of DeviceClass::vmsd Date: Mon, 1 Mar 2021 22:50:54 +0100 Message-Id: <20210301215110.772346-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The cpu model is the single device available in user-mode. Since we want to restrict some fields to user-mode emulation, we prefer to set the vmsd field of CPUClass, rather than the DeviceClass one. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27192b62e22..faabffe0796 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -237,7 +237,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_alpha_cpu; + cc->vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed983380fca..29a865b75d2 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -293,7 +293,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_cris_cpu; + cc->vmsd =3D &vmstate_cris_cpu; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d8fad52d1fe..4f142de6e45 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -162,7 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_hppa_cpu; + cc->vmsd =3D &vmstate_hppa_cpu; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 37d2ed9dc79..c98fb1e33be 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -533,7 +533,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_m68k_cpu; + cc->vmsd =3D &vmstate_m68k_cpu; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 433ba202037..335dfdc734e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -387,7 +387,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; - dc->vmsd =3D &vmstate_mb_cpu; + cc->vmsd =3D &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46b..79d246d1930 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -204,7 +204,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_openrisc_cpu; + cc->vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ac65c88f1f8..bd44de53729 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,7 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->gdb_num_core_regs =3D 59; =20 - dc->vmsd =3D &vmstate_sh_cpu; + cc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 0258884f845..12894ffac6a 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -146,7 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_uc32_cpu; + cc->vmsd =3D &vmstate_uc32_cpu; cc->tcg_ops =3D &uc32_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e2b2c7a71c1..6bedd5b97b8 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -218,7 +218,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - dc->vmsd =3D &vmstate_xtensa_cpu; + cc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.45 as permitted sender) client-ip=209.85.208.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614635490; cv=none; d=zohomail.com; s=zohoarc; b=XBxbjRkycST74BEdNH6nQn7mp2XVZJyJbD6MGx1sglJMa+2UO9e0VixcCQlxsbE42a1Q0YoKR80ZFqUH2HS1AZL9BNPXvxtKNP6Bxc9DkNjRZ5AOPuzuF94zpShHMDzZ4akApVoPTeKHAf9ciyp6v3+hadZ2iGlUSoz0e89Slrg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635490; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id r5sm15654002ejx.96.2021.03.01.13.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:51:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UQM81mur+9UHjxbQN0Zv4wGjBmPMsrfz+L5iL9ZySpM=; b=Wo4ume9LDIcgU8ptj0tmTuZ1U0ZnXKTTeu/5Ft+lKmR/ayBUFv+3pEWMqJZRvDg2Zm czZtwCmx0tHfOEv/e+GAX5+Zr0Xi4xc82V1X8TQfsDdkeo+1408WH+tKLQbVi+SEpesm yQtkH5M5M9UCVF6ofWcrSK6MDgXzU92hAmXqDD37twrfOtdgNtB1whLwP6l1Al0NqCw6 J5qHcigcACuIwTZi226qJWjD9Wpr440Mh48s+76OhMAkj8kTS41IcbWTuyav5uozvmjM QBVgHF9gwGmzFF7PVbOx5hyk5ueMNdSdZtsPhuUVMT/DOETzjDFm3emzp7N8AZTo8GtM x70A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UQM81mur+9UHjxbQN0Zv4wGjBmPMsrfz+L5iL9ZySpM=; b=NyFrzKNMYT0KKcmefUhUpWlGAGzT+B9885gKg4HZNfEO5UwZ+x3cCO1quhZB6bipIx f2aseiApjj07ez/lLC8WwDK+tkDmeWa3f6GjDdPomEvAfAHDxfIKIFJTe20BC68v1leC KkUU8dCSo4XQ8yZkXyhhk+i9HfSCgyHn36zTTpU6QBXf7mtPir5G+KteQSRAyOJ8r1rW ZpNUdAk5eRS33qdxAXDHEFBqg493GuEu9o7qd5STB/k5eErL9q6uFKsa/1PS1VR7PL1E emNVgHHsWA8OOHZGE3DDjIIp9Rlu8yJ6R2JYatIbGUxcwWtajB/Yeiqzs49sBr2N4bAK cFgg== X-Gm-Message-State: AOAM530PwFyjIa+RK+J2V9bXYfT9vwVZEyt4dIOIvRrS5lHWYgQttMSL byXt7rsUYcOld3eRtvMb4yk= X-Google-Smtp-Source: ABdhPJwbz8n7/Q3kHjb981vHL7Yl0IqsokynKKftRO8GNia2iNJGWe0PGzFH+gDO7LKDE4TTG4JkHA== X-Received: by 2002:aa7:db91:: with SMTP id u17mr18050122edt.71.1614635488763; Mon, 01 Mar 2021 13:51:28 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 02/17] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Date: Mon, 1 Mar 2021 22:50:55 +0100 Message-Id: <20210301215110.772346-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 33 ++++----------------------------- hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c005d3dc2d8..2d43f78819f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -578,18 +578,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags); * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr ad= dr, - MemTxAttrs *attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); - } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); -} +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); =20 /** * cpu_get_phys_page_debug: @@ -601,12 +591,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPU= State *cpu, vaddr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) -{ - MemTxAttrs attrs =3D {}; - - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); -} +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 /** cpu_asidx_from_attrs: * @cpu: CPU @@ -615,17 +600,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState = *cpu, vaddr addr) * Returns the address space index specifying the CPU AddressSpace * to use for a memory access with the given transaction attributes. */ -static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - int ret =3D 0; - - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); - assert(ret < cpu->num_ases && ret >=3D 0); - } - return ret; -} +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 #endif /* CONFIG_USER_ONLY */ =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..4dce35f832f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu, error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_phys_page_attrs_debug) { + return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + } + /* Fallback for CPUs which don't implement the _attrs_ hook */ + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return cc->get_phys_page_debug(cpu, addr); +} + +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +{ + MemTxAttrs attrs =3D {}; + + return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); +} + +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + int ret =3D 0; + + if (cc->asidx_from_attrs) { + ret =3D cc->asidx_from_attrs(cpu, attrs); + assert(ret < cpu->num_ases && ret >=3D 0); + } + return ret; +} + /* Resetting the IRQ comes from across the code base so we take the * BQL here if we need to. cpu_interrupt assumes it is held.*/ void cpu_reset_interrupt(CPUState *cpu, int mask) --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) client-ip=209.85.208.43; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id z16sm15101159ejd.102.2021.03.01.13.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:51:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=alNnX6GeE8sTwFbIWBvN2VrnGh2+v4nR5yjKLFDEoAw=; b=N356hqnOS53JeEI9N4ogQ9eqEmQUvctHKDSka4SwT5jqJexytNWOdfuRkdjn5RZ/4f D9Yn3Qi5nGMd+xXN4DYkNybIOo0Njqfg2Qx8Wch53Xu7ADntj9ZMSUHCtarUI84otPW5 0QRcltdYTQLEzYkCIMFViitJ6l9dOdpx6fQQQbqEIwoDkqRHxF+Ri2tBZu6blkcc/yod +9PxMGHdFoGpp47QmJSORTnH/CdJ1YzIWzjmtFoqQBUBwZK2WzOP+LHoMi3z5cj0T8Yb qAaSVJrYSMuPYZXNFrEAd9ZV2nHwDnIA4I2Z7heOvyfTKD2f2KSrrSS9YpsBtrdx6dDM Dqlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=alNnX6GeE8sTwFbIWBvN2VrnGh2+v4nR5yjKLFDEoAw=; b=m1CFo+auODgGBVMANA0Ik89Xy63aAh2yvtIAzmdAacOD/Z9CGd/zx5hhm3MOSBdD6k 8oXrlwCLTLNkzX7sKIeO7l14nSYe2/GhkyszDztcF9DCKj1N6L9+gZaH2FpSojZSx3QI R3E1oPFCOPhjffSAprSbB+tubTPcUq76mhvWjHXnl5Broz//y+Pmvn+wRSSseINRJ6e6 rkXbsw8AuYrNHLjfP3xFotHpFx0/mFIJSFzSbJh0//jm+85CYndA71VbGKcqJ1px2rLr QRWU9MCPvJPoWz1B8e39ZQOPLeKpPtCM6FJMUguJDqaB1rvZt2pQrZckyvCcvJozHDp6 MqLw== X-Gm-Message-State: AOAM5336LEe9jZhWmgOnGZNxyXV7OsAUnRolEovk/ks8j059I7R0ihzo XhYWo0+rGA2lCw/iS1lWZGE= X-Google-Smtp-Source: ABdhPJwY2cJ6XXv/YhOMEkg/67Wc+6Z5YexVWqUoNJklbVwwjS6kByITbIU4xaCl23BOtYptCRAENw== X-Received: by 2002:a05:6402:51cd:: with SMTP id r13mr17712407edd.214.1614635495810; Mon, 01 Mar 2021 13:51:35 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 03/17] cpu: Introduce cpu_virtio_is_big_endian() Date: Mon, 1 Mar 2021 22:50:56 +0100 Message-Id: <20210301215110.772346-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the cpu_virtio_is_big_endian() generic helper to avoid calling CPUClass internal virtio_is_big_endian() one. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 9 +++++++++ hw/core/cpu.c | 8 ++++++-- hw/virtio/virtio.c | 4 +--- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2d43f78819f..b12028c3c03 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr ad= dr); */ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 +/** + * cpu_virtio_is_big_endian: + * @cpu: CPU + + * Returns %true if a CPU which supports runtime configurable endianness + * is currently big-endian. + */ +bool cpu_virtio_is_big_endian(CPUState *cpu); + #endif /* CONFIG_USER_ONLY */ =20 /** diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 4dce35f832f..daaff56a79e 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu= , uint8_t *buf, int reg) return 0; } =20 -static bool cpu_common_virtio_is_big_endian(CPUState *cpu) +bool cpu_virtio_is_big_endian(CPUState *cpu) { + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->virtio_is_big_endian) { + return cc->virtio_is_big_endian(cpu); + } return target_words_bigendian(); } =20 @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; - k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 1fd1917ca0f..fe6a4be99e4 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endia= n(void) =20 static enum virtio_device_endian virtio_current_cpu_endian(void) { - CPUClass *cc =3D CPU_GET_CLASS(current_cpu); - - if (cc->virtio_is_big_endian(current_cpu)) { + if (cpu_virtio_is_big_endian(current_cpu)) { return VIRTIO_DEVICE_ENDIAN_BIG; } else { return VIRTIO_DEVICE_ENDIAN_LITTLE; --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) client-ip=209.85.208.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614635504; cv=none; d=zohomail.com; s=zohoarc; b=IBpCUPf0i4J+mO5HWIYKxsrVjlsr4qSZ8ThLyDDoR4PPVHKm+tB5PP8E5bkGIJLMR1l+HL1xnxOUnEuoLXSpo5eYeLn7pOel6wS1nRrwWLLfXzgYA/4usOkuX53VCmSi0NI/p1ziHK6sftcwMp3BmYzljlf5TAdf3ghTXvw8uGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635504; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VJm0iGgu/pocJ2Vudv8ibS2Ot9Xd+ih0+p5aBEZz7PY=; b=XKKZFrNB8tKhTMKBOMWsaRf5y3Tm8Xp5x6xqtIq7w9ya7INTAmwsQMIoGl2YljNXqovKDyH1mZTQqv8cFMVR0yxfKg+leG6olN/bYYoxT4MW1OMYN5d47nCLxn64RO50ixdeOW0eBUL4Appn6+GwS+32RSrgiaWwFMQU1GZTlac= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) by mx.zohomail.com with SMTPS id 1614635504620371.3454243589689; Mon, 1 Mar 2021 13:51:44 -0800 (PST) Received: by mail-ed1-f43.google.com with SMTP id bd6so9514469edb.10 for ; Mon, 01 Mar 2021 13:51:44 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id l6sm17005597edn.82.2021.03.01.13.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:51:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VJm0iGgu/pocJ2Vudv8ibS2Ot9Xd+ih0+p5aBEZz7PY=; b=vfqyCfg/M0KAHUUysrP0H26KOKDyubdiVj6/XijCoK22bEANmWo0ijiO44yMB/I78u e/5LGiBJpDorWkZfxurVm5Wz6+PD6SQWdJtZe1vnMbI5SRKll0f5BhvEPIaxaY/xqVy5 hLI2WMpeKBysUHUTy9bb+TIsC6/3UEdU53Zszqv4lkKRG1gT1WHO7mQJlG0PZ5jCcx2k g16Xr8DB+lfTGeF9UF1NXnxMf8RgOJG8eW6vmpfgexq6HHKbk/vQmAzginKook7ScpES NDJekS+fFlluU3frY+jtJI1Xb2SteWazn5ckDhXS5xedd2n1CcDtIGtaDlrUu7/kYbLK ISMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VJm0iGgu/pocJ2Vudv8ibS2Ot9Xd+ih0+p5aBEZz7PY=; b=Jz3IRZIwKwy9xwjFj1YAYndjKiiGG9G1fnVGgF+/2mYplXf6OtkKCnv/aOJMkvC/mH 49zMSGjk4JtUp5ayNI3fv9F5zSVaDwGaRxI9qiqfL+Sed9hujEYq+Ap4igcp3XAFGM8u oyyb49xIB+p6tfC223HujAp/uqAkQQ1A54dWOl9CXR0Jiqp0h8j+ymthDJ70KZ1jsX3G UTMEw2rhIBbvL6f2+Ik3NzB3JEEVG8m6T5joYISK44UcHaAb4+xXB+7/Jx7JoWJaDasa ztRMl87kjvgqXf9apeyzdpF86ycJnTtznfhkK6MdUz5yT/jMLOpmuC5Pxot+XPsuT8F8 aBzw== X-Gm-Message-State: AOAM5322lIfhNQdE9o2OwA+GQX5sQ4gSVhLU6R+h0CTADonXkxEXi6CS Pv3wEGCt4UDNOXPIguOOxLA= X-Google-Smtp-Source: ABdhPJwXek5koJx5nUhvVToIiBTv2UFcA/Re7Ng5ulYwmbnUJVETdZOLNVBNieirJFx40U0FiHqxeQ== X-Received: by 2002:a05:6402:6cb:: with SMTP id n11mr4541013edy.198.1614635502892; Mon, 01 Mar 2021 13:51:42 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 04/17] cpu: Directly use cpu_write_elf*() fallback handlers in place Date: Mon, 1 Mar 2021 22:50:57 +0100 Message-Id: <20210301215110.772346-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code directly accesses CPUClass::write_elf*() handlers out of hw/core/cpu.c (the rest are assignation in target/ code): $ git grep -F -- '->write_elf' hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque); hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque); hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:440: k->write_elf32_qemunote =3D cpu_common_write_elf32_= qemunote; hw/core/cpu.c:441: k->write_elf32_note =3D cpu_common_write_elf32_note; hw/core/cpu.c:442: k->write_elf64_qemunote =3D cpu_common_write_elf64_= qemunote; hw/core/cpu.c:443: k->write_elf64_note =3D cpu_common_write_elf64_note; target/arm/cpu.c:2304: cc->write_elf64_note =3D arm_cpu_write_elf64_no= te; target/arm/cpu.c:2305: cc->write_elf32_note =3D arm_cpu_write_elf32_no= te; target/i386/cpu.c:7425: cc->write_elf64_note =3D x86_cpu_write_elf64_n= ote; target/i386/cpu.c:7426: cc->write_elf64_qemunote =3D x86_cpu_write_elf= 64_qemunote; target/i386/cpu.c:7427: cc->write_elf32_note =3D x86_cpu_write_elf32_n= ote; target/i386/cpu.c:7428: cc->write_elf32_qemunote =3D x86_cpu_write_elf= 32_qemunote; target/ppc/translate_init.c.inc:10891: cc->write_elf64_note =3D ppc64_= cpu_write_elf64_note; target/ppc/translate_init.c.inc:10892: cc->write_elf32_note =3D ppc32_= cpu_write_elf32_note; target/s390x/cpu.c:522: cc->write_elf64_note =3D s390_cpu_write_elf64_= note; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 43 ++++++++++++------------------------------- 1 file changed, 12 insertions(+), 31 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index daaff56a79e..a9ee2c74ec5 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_qemunote) { + return 0; + } return (*cc->write_elf32_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_note) { + return -1; + } return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_qemunote) { + return 0; + } return (*cc->write_elf64_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_note) { + return -1; + } return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - - static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) { return 0; @@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *d= ata) k->has_work =3D cpu_common_has_work; k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; - k->write_elf32_qemunote =3D cpu_common_write_elf32_qemunote; - k->write_elf32_note =3D cpu_common_write_elf32_note; - k->write_elf64_qemunote =3D cpu_common_write_elf64_qemunote; - k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.43 as permitted sender) client-ip=209.85.218.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614635511; cv=none; d=zohomail.com; s=zohoarc; b=HKjUFU8kTshafkSTIiEpKen6f4NcQLaEQmyC1JL6aI7M+1gICfN5/owHfk7DRCWj0Kj3xTQ0Syau3761qqgB7QIdRrJCCTHK+A2GceV/4UNl/qeeoubUSfW+9tEEcXZhXZwJKD02JFRS+PxcUkCjdwh3nnKCDjUKVxgxLmBEDNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635511; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yI5v3ChjpgUoMVznW3/vQVCaXLpm+f+cFTMRG3SQklk=; b=ElH0SWhVTrKPdtgCN9nyoRhUoZ8b1G2Ob6wLEo0fZjP6Xiv1AQ7AB+aOUvoZCSKXC73Ht9/u6MngvymnBnc2bsyhfOxu7DrQXEOoXywOuNnvTgj+7e+V2uv7o8M2lVg6PAP6vfAM181SgfgOps0c9bJgmAGSrKCu9ntImFpKDls= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) by mx.zohomail.com with SMTPS id 1614635511389266.3757592589443; Mon, 1 Mar 2021 13:51:51 -0800 (PST) Received: by mail-ej1-f43.google.com with SMTP id bm21so12329139ejb.4 for ; Mon, 01 Mar 2021 13:51:50 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id g3sm15119250ejz.91.2021.03.01.13.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:51:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yI5v3ChjpgUoMVznW3/vQVCaXLpm+f+cFTMRG3SQklk=; b=mJ/K/lwXOVWoit73y1TYSSHLaOMllfDz24/alFPlQU1Fv3CZQn+qrprvLdxaNmhbCm dSB0Tz3d5h78JZ2znwY7NsHURe3BQ9mYMwnrlI4RSBOX7lYa9WchKNRQoBnrWCmzRtYX P3fe6I732CdelMEsxp+coxJBugkqOkGmknj0h7iJGrfjdKJtqpLBCa6zEb86yLqDcBN6 aB88VKvPKgVxswFWPqTRwB0ho1O/b7rDZAb4FUwdttxG8DXe7RS5PcM4UxYixyINmWgN cgshLC40AvaqFM9PtuQgSY0PKAaW+glWBlzoNdLDJ8b+8EBzxijGfQWajaUtJqHm1TKn uk6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yI5v3ChjpgUoMVznW3/vQVCaXLpm+f+cFTMRG3SQklk=; b=JJybNsZUQGLzlYMnFy/XZkWp2wM7QLDbdJAskj9pXtkVuxMIEoveJM8NsK3Qh4Czhj wJGcrOEgFO7c5Z7Ttz3PEekLPfWXzQLh+DF+73ezXkb7vsov8AzerKW1nlLBejtPm+CB V7fgMTXB5RDyNk6/vgu0UOjhcaqf++UX4/6Q8RVo9jqi7r59+LdbvCigdTBVn6tybGGK ubgk24uv2MYK/37EUDTzCXRyxgsaHbEztPJgRHKVh5/O99HznXXcdS9f/v8hduDT4yp6 wTv4W1kDCLGCAFbBUBcGzJtm7h8vP50i/t/0CAeHpxe2M996c39HdjndhB7dLFz34H/0 zlgA== X-Gm-Message-State: AOAM530rWluz2i9gGGfCicBPrYrIldjPY6J1CdVykEzHQouO0MqOa+j1 zHaVAKWoDOWlJAb/mJziv4I= X-Google-Smtp-Source: ABdhPJwuzUg9H3JStF7Mt7P2sEH9OQ6CbSCzzDlovpAnzBeLxmRv7x1mMaGsrs4knxta3MmziPiudQ== X-Received: by 2002:a17:906:b001:: with SMTP id v1mr17826274ejy.217.1614635509703; Mon, 01 Mar 2021 13:51:49 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 05/17] cpu: Directly use get_paging_enabled() fallback handlers in place Date: Mon, 1 Mar 2021 22:50:58 +0100 Message-Id: <20210301215110.772346-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c: $ git grep -F -- '->get_paging_enabled' hw/core/cpu.c:74: return cc->get_paging_enabled(cpu); hw/core/cpu.c:438: k->get_paging_enabled =3D cpu_common_get_paging_ena= bled; target/i386/cpu.c:7418: cc->get_paging_enabled =3D x86_cpu_get_paging_= enabled; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index a9ee2c74ec5..1de00bbb474 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - return cc->get_paging_enabled(cpu); -} + if (cc->get_paging_enabled) { + return cc->get_paging_enabled(cpu); + } =20 -static bool cpu_common_get_paging_enabled(const CPUState *cpu) -{ return false; } =20 @@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.48 as permitted sender) client-ip=209.85.218.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614635518; cv=none; d=zohomail.com; s=zohoarc; b=myytByjKWKY1TUl8AwbxyOux+GGpPZC2KCxq5TOytiud47T3UxBrfzLyeWOLK9/1Hfs2ic/VEYNkHoxZr6bEDo4uctCJeympqE6DiYKz3LoPdq4PnjBNZqPblAyyGKyq/Wophn9Jf174URUB4XpOGO8/6/EaOL42rZPerQX+Q2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635518; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iDkHmNWDJUjsisDNEA+tDXF79jqbgWv+Yeaa+F2Cdm4=; b=AsA4WI0j0lEy7PUb0i/9Zx0GygcaGeAaXIdKNfXwjphQH6MnQrNa20+b65vaJ1ECtYh+4iL2vaZB3G26n0BHpeHvQeTmQKQE7J9aHv6sFzFPr72uaT1g4g9+2MPO0AnTb+QMcE1XbA4ZBex7feX07C6yz76esx6ytAxWuBAubTc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) by mx.zohomail.com with SMTPS id 16146355185649.888530590094206; Mon, 1 Mar 2021 13:51:58 -0800 (PST) Received: by mail-ej1-f48.google.com with SMTP id mm21so30864947ejb.12 for ; Mon, 01 Mar 2021 13:51:57 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id k22sm16117927edv.33.2021.03.01.13.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:51:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iDkHmNWDJUjsisDNEA+tDXF79jqbgWv+Yeaa+F2Cdm4=; b=qKbMpv8R6uGKaW+uF2TJniKppsrNgGG8wOsfeSa8V1qx0PoHJAGlfGGLA5R+WHb0fA /TVZ3p3JWNmsfeRoSLinNoSa9Q4QzdUMgVOiGt62dn0mErZVAgpEPxQLoHKaUNDdg5J4 a15/5NwKl9JsVGvL8+TiIUSft7nY+gP5CCPWdcOsvBPlZY8nzuI8GR0CbxQ+gobLheql yP9edRwWF41VhFuHjKjsuMuZ54h3GLNQBjoAM7re+X0+P3ztQF2mFr3dyfp2Xeg1p7vP LIYIZd00wkKzgSK6bO1a+XbuJVwhTnxccj2HOta6itnVQAmdXMyaXSsduWP2pUMgNmnI 5qbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iDkHmNWDJUjsisDNEA+tDXF79jqbgWv+Yeaa+F2Cdm4=; b=m6GVKbOuKvLU32AAxx1AFOF9lazJydqkSCRA0u7hH8aNmxmCnrx2zUdPB4Xfyx9Idx JGMNbNLl6bckzTv4Sc8jiDEc2TTUCqH9gnK/sPq8ghJC8xHQSBpMNkCeYWlX6gBgWkjr G6RoWFP71RJvKzHv27hHxhEe7dVHIBya8Ogddt7tsT/O8q+2P98nzIZclqu79QJ3RCRC 1VhjgEKMjpZi8/yj12yczw0sH9/ay5a3HbOUuVyD0Pv6ee+r6UAjCbdSn8XJrmu7BtHA sdPEaQN7RaY8lntnQObRSEwKwqRLl+D1QZaqypkf4WIvifd06BMCyOI3QikXBljXKPKa y+zA== X-Gm-Message-State: AOAM5308ibed/3PIU+v0iPvK3mEzw1PjFfFM5OPxEeQw/rs+17BP2YhE vWqz/4MUK7cpKVHiIzTG0Vc= X-Google-Smtp-Source: ABdhPJw94wwLPTSrVmDa5ZJSx4v6K75gqF320i50dk/ACFSxUOLBbuaPMoMpLry5l7fTFqx1V/FU1w== X-Received: by 2002:a17:906:5016:: with SMTP id s22mr17940611ejj.550.1614635516679; Mon, 01 Mar 2021 13:51:56 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 06/17] cpu: Directly use get_memory_mapping() fallback handlers in place Date: Mon, 1 Mar 2021 22:50:59 +0100 Message-Id: <20210301215110.772346-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c: $ git grep -F -- '->get_memory_mapping' hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp); hw/core/cpu.c:439: k->get_memory_mapping =3D cpu_common_get_memory_map= ping; target/i386/cpu.c:7422: cc->get_memory_mapping =3D x86_cpu_get_memory_= mapping; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 1de00bbb474..5abf8bed2e4 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappin= gList *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->get_memory_mapping(cpu, list, errp); -} + if (cc->get_memory_mapping) { + cc->get_memory_mapping(cpu, list, errp); + return; + } =20 -static void cpu_common_get_memory_mapping(CPUState *cpu, - MemoryMappingList *list, - Error **errp) -{ error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 @@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.44 as permitted sender) client-ip=209.85.208.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614635526; cv=none; d=zohomail.com; s=zohoarc; b=dwK+0bPI6N132JP2Bn0GLIZfU2xqUJnuq5lS1BnmqxbiXLJXkNm/3twG0YktKg8UfqpCRIYrhXJMBRdF7GJjcE32dnbCZ+VMeqJMc7OY8ljdJhBgCvqsjLgqJZlHL/sjw2ugcNWn0yWhkxqx/koqnhJq6+PHznBg38ex9rv+O6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635526; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=X120oQI07eFl+Ysl6eq3iFfdrvQzs+b+T4SMXWlM8P0=; b=fdXNd8vvnuBLqK2aunHvstH7bpD8+1q2W5ixOoCTMJ7IzTuZ3Cn135YTrEo+WVwZ6wGHfHdWO3R71LAqMSAtPj1H3j67e2Gf1uIfhCftxZQgcU+q7YbWIf8+IpiyMwXo7HqAHK4XBfJOB9yPRoLt+8riSSEwi8iBDs7jb8onohY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) by mx.zohomail.com with SMTPS id 1614635526515377.84501735594984; Mon, 1 Mar 2021 13:52:06 -0800 (PST) Received: by mail-ed1-f44.google.com with SMTP id g3so22706324edb.11 for ; Mon, 01 Mar 2021 13:52:05 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id b6sm15129585ejb.8.2021.03.01.13.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:52:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X120oQI07eFl+Ysl6eq3iFfdrvQzs+b+T4SMXWlM8P0=; b=FFWdFnjV9kAaXTetaWV4cYn/IEBr10Cp/HZxWpapsDOZ5BcCSgSVj1RLUNs+1QRhl+ El1VWa12iYQqeBpnv/uxitNfCxuqaGKrdZnhbZr0c2Bc879rQUv+XUQ+F8AEwKWXwbdK 5ZdFOhkM/NDV610RMb1eRsluYJINyCEPoA1HLvNaTHXEdrMxaW54f9DZ/Pw+t7/Chsgg FsYz6LSPFwtEhAO1fJeYNotASRFojvxPSCK4IPXCGSkZdBz3Fog4OQZzqbBvXOkxaM33 8UhWtTOW8KZJRpGtnYUpjrIFWHoUslqe3VtuW4fKTqYIcU75ONFV70N+P9SNBDyuQTs+ fYsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=X120oQI07eFl+Ysl6eq3iFfdrvQzs+b+T4SMXWlM8P0=; b=kmdnVYjtcL450NLgZte6yw4CckuJLvvMKR8LCm6Vk0H1tmNmPDMugcVGXZY1fGN0C2 e2zsa1BR3maM0H7UowBStgder6UTDwujpoWiSor99dR/nRB+mYoXA2SHLgBhKYhqTsr7 vPm4piHyYum49dG58dLiqbte1za34vfJrwbRbTJvzSOSDDD7wLa+BLd8dYGWhgQo6fpU V08lIAVrHwF+nzF370f4HKJDVSiEZ4SgmrGfir57Gl4AXnS020YCwbJIwykeLVEg4yMH NQMqIshhb64vZZiLbNEC6W+VTP3KCUx2ODtheqkCgpFDmF1Pkt+RJN9eD5H/l7Tn7WxG UseA== X-Gm-Message-State: AOAM533cl3Qmv7WrXryHxLCRhAcvXD/hIr0HV48ITLg1AUsIbxLS1x3Q 0cOzZAyLg9RVE0O5MD4WIes= X-Google-Smtp-Source: ABdhPJzsdhRBLzeY0zF4p1GIPgchBxGvNRlJckLVkhXEthxoC/UDES220OCzWIN+tyQBqw1PmoAjYw== X-Received: by 2002:a05:6402:3553:: with SMTP id f19mr18445845edd.271.1614635524422; Mon, 01 Mar 2021 13:52:04 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 07/17] cpu: Introduce SysemuCPUOps structure Date: Mon, 1 Mar 2021 22:51:00 +0100 Message-Id: <20210301215110.772346-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 +++++ include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++ target/alpha/cpu.c | 6 ++++++ target/arm/cpu.c | 6 ++++++ target/avr/cpu.c | 4 ++++ target/cris/cpu.c | 6 ++++++ target/hppa/cpu.c | 6 ++++++ target/i386/cpu.c | 6 ++++++ target/lm32/cpu.c | 6 ++++++ target/m68k/cpu.c | 6 ++++++ target/microblaze/cpu.c | 6 ++++++ target/mips/cpu.c | 6 ++++++ target/moxie/cpu.c | 4 ++++ target/nios2/cpu.c | 6 ++++++ target/openrisc/cpu.c | 6 ++++++ target/riscv/cpu.c | 6 ++++++ target/rx/cpu.c | 8 ++++++++ target/s390x/cpu.c | 6 ++++++ target/sh4/cpu.c | 6 ++++++ target/sparc/cpu.c | 6 ++++++ target/tricore/cpu.c | 4 ++++ target/unicore32/cpu.c | 4 ++++ target/xtensa/cpu.c | 6 ++++++ target/ppc/translate_init.c.inc | 6 ++++++ 24 files changed, 152 insertions(+) create mode 100644 include/hw/core/sysemu-cpu-ops.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b12028c3c03..3c26471d0fa 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,6 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 +#include "hw/core/sysemu-cpu-ops.h" + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -190,6 +192,9 @@ struct CPUClass { bool gdb_stop_before_watchpoint; struct AccelCPUClass *accel_cpu; =20 + /* when system emulation is not available, this pointer is NULL */ + const struct SysemuCPUOps *sysemu_ops; + /* when TCG is not available, this pointer is NULL */ struct TCGCPUOps *tcg_ops; }; diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h new file mode 100644 index 00000000000..e54a08ea25e --- /dev/null +++ b/include/hw/core/sysemu-cpu-ops.h @@ -0,0 +1,21 @@ +/* + * CPU operations specific to system emulation + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef SYSEMU_CPU_OPS_H +#define SYSEMU_CPU_OPS_H + +#include "hw/core/cpu.h" + +/* + * struct SysemuCPUOps: System operations specific to a CPU class + */ +typedef struct SysemuCPUOps { +} SysemuCPUOps; + +#endif /* SYSEMU_CPU_OPS_H */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index faabffe0796..b9b431102f2 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps alpha_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps alpha_tcg_ops =3D { @@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_alpha_cpu; + cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b8bc89e71fc..994e7b344d4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2260,6 +2260,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs) return g_strdup("arm"); } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps arm_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG static struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, @@ -2303,6 +2308,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; + cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f4596932ba..84f7ad4167e 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) qemu_fprintf(f, "\n"); } =20 +static struct SysemuCPUOps avr_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps avr_tcg_ops =3D { @@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; cc->vmsd =3D &vms_avr_cpu; + cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 29a865b75d2..a97ad7c9c65 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps cris_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps crisv10_tcg_ops =3D { @@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_cris_cpu; + cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4f142de6e45..48946cf6669 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char = *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps hppa_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps hppa_tcg_ops =3D { @@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_hppa_cpu; + cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6a53446e6a5..fa517555e73 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7386,6 +7386,11 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps i386_sysemu_ops =3D { +}; +#endif + static void x86_cpu_common_class_init(ObjectClass *oc, void *data) { X86CPUClass *xcc =3D X86_CPU_CLASS(oc); @@ -7427,6 +7432,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->vmsd =3D &vmstate_x86_cpu; + cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c23d72874c0..2d8d16d5535 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char = *cpu_model) return oc; } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps lm32_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps lm32_tcg_ops =3D { @@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_lm32_cpu; + cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c98fb1e33be..5c43981c35d 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -502,6 +502,11 @@ static const VMStateDescription vmstate_m68k_cpu =3D { }; #endif =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps m68k_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps m68k_tcg_ops =3D { @@ -534,6 +539,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_m68k_cpu; + cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 335dfdc734e..34a60edd1cc 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *c= pu_model) return object_class_by_name(TYPE_MICROBLAZE_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps mb_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps mb_tcg_ops =3D { @@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; cc->vmsd =3D &vmstate_mb_cpu; + cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bf70c77295f..ea9259896f2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -680,6 +680,11 @@ static Property mips_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps mips_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_mips_cpu; + cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; cc->gdb_num_core_regs =3D 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 83bec34d36c..dbc9e022b61 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) return oc; } =20 +static struct SysemuCPUOps moxie_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps moxie_tcg_ops =3D { @@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; + cc->sysemu_ops =3D &moxie_sysemu_ops; cc->tcg_ops =3D &moxie_tcg_ops; } =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a389..57023e38cb8 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -207,6 +207,11 @@ static Property nios2_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps nios2_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps nios2_tcg_ops =3D { @@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 79d246d1930..e00678ae038 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj) | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps openrisc_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps openrisc_tcg_ops =3D { @@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_openrisc_cpu; + cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16f1a342388..fd85e6fc6af 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -580,6 +580,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState = *cs, const char *xmlname) return NULL; } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps riscv_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps riscv_tcg_ops =3D { @@ -624,6 +629,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->vmsd =3D &vmstate_riscv_cpu; + cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26b..812cf718732 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps rx_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps rx_tcg_ops =3D { @@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; =20 +#ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &rx_sysemu_ops; +#endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d35eb39a1bb..0efb1381647 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev) return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); } =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps s390_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; + cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index bd44de53729..41f1c7c0507 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -223,6 +223,11 @@ static const VMStateDescription vmstate_sh_cpu =3D { .unmigratable =3D 1, }; =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps sh4_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps superh_tcg_ops =3D { @@ -257,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &sh4_sysemu_ops; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index aece2c7dc83..377378ca1f2 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps sparc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_sparc_cpu; + cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcba..75f8a2d8014 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +static struct SysemuCPUOps tricore_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps tricore_tcg_ops =3D { @@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 12894ffac6a..37e57178657 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu =3D { .unmigratable =3D 1, }; =20 +static struct SysemuCPUOps uc32_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps uc32_tcg_ops =3D { @@ -147,6 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_uc32_cpu; + cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6bedd5b97b8..7b925468203 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,6 +181,11 @@ static const VMStateDescription vmstate_xtensa_cpu =3D= { .unmigratable =3D 1, }; =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps xtensa_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps xtensa_tcg_ops =3D { @@ -215,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &xtensa_sysemu_ops; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index e7324e85cdb..a835bd86214 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10843,6 +10843,11 @@ static Property ppc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static struct SysemuCPUOps ppc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -10886,6 +10891,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_ppc_cpu; + cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.44 as permitted sender) client-ip=209.85.208.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614635533; cv=none; d=zohomail.com; s=zohoarc; b=T2oKuVKXFB9NuqFC7x72vW3+a3L+cEXLromiHdJ6Sa6unSeM4KVf5tAAdp/Fg/dBGjR05/hN4rwY3PfbzHKEL2woT1lR0/MTLVDFLoh60wHeVtljBV4NJmKRj2RghoQ91z8WLmcMsKDMmsR8kUPqn+6BhcSFviv7TbJKuleq2b0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635533; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id lu5sm5727409ejb.97.2021.03.01.13.52.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:52:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jZ9LzGr+2KjxpCj3ls57BgL9kGnnOtUuV1kbA258rRM=; b=ZasCNX7ubURnS/5CT9+SzIq4Qvh/fXj1c2sP5JsHYu9H83OTcof+GQ6/tERvNNQY2T dmIz/kV19MlDlABLTZBNZCQomG0BLR29pzJ/BrOJAU64W94tZ9fJTpFwLZUF4zcl02sK Qd41kDhBQMPt2XjSdLMn8JYvKgT1plLCObSL+XY13YanKdGtCTKc63rM9yZLK0z1SBAd DsKoU0tj9EUyDGiFT4vtJP6y1OK0uGJha94xG8T+Cwy6n8TMUieA47RcdrcnwuY4PbOj t3953npS3+N3zrRaf7+J6g8oNiPzqWr+Bo38e2itMiFHqmitl8+plfhldgqRkUZpDUsf YF6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jZ9LzGr+2KjxpCj3ls57BgL9kGnnOtUuV1kbA258rRM=; b=h3fKZIvr3TnddDf777jZpNY5zIzzBvuZnsKOI/u9z7JgruI8CTfMvK4kcegWlG/hKd cGICMAilJxzHJbhoUKT95A2N2XzJxVesQwpuV+sTwSz4BEn/UgB+WVPR/XdApxvkUZc3 /jCBiNk5PRfE7pfzlkDkRrCmgnO2v5a5jpko1NC4whhj59O466Zp0cuUE1gE+0PYMgDP SruzB2SEG8eQOqpQzu0v0Fx8OPxNFi9/Ox6i7ef8xoDdTnJ+eiKvyJfD+WM7VRZnSwps Md6BsKPmixrBJ9nz0/tQfQkMzlAVNyPWPJQjUw+i6ZZMfFl7R34S2Ym6b13EaZOYOAPg rvZA== X-Gm-Message-State: AOAM530MwoLXWZnmKhu9mXvKtV5sM6mhuwVicaBcYx9VeQ1SpSdZ9Bye nfBS5EY9crdmqsAyppMcAUk= X-Google-Smtp-Source: ABdhPJz5d4TC87WwKY2OAcvvWDDsW16vT+TFE1fNEfemUdfwS0JIw3d9yOepcVOX+QBznDRf2yCnQQ== X-Received: by 2002:a05:6402:13ce:: with SMTP id a14mr18295516edx.365.1614635531906; Mon, 01 Mar 2021 13:52:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 08/17] cpu: Move CPUClass::vmsd to SysemuCPUOps Date: Mon, 1 Mar 2021 22:51:01 +0100 Message-Id: <20210301215110.772346-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Migration is specific to system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 2 -- include/hw/core/sysemu-cpu-ops.h | 4 ++++ cpu.c | 18 ++++++++---------- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 7 +++++++ target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 4 ++-- target/rx/cpu.c | 6 ++++++ target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 7 +++++++ target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 4 ++-- target/ppc/translate_init.c.inc | 2 +- 25 files changed, 54 insertions(+), 34 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3c26471d0fa..471c99d9f04 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -124,7 +124,6 @@ struct AccelCPUClass; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @vmsd: State description for migration. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -179,7 +178,6 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); =20 - const VMStateDescription *vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index e54a08ea25e..05f19b22070 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,10 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @vmsd: State description for migration. + */ + const VMStateDescription *vmsd; } SysemuCPUOps; =20 #endif /* SYSEMU_CPU_OPS_H */ diff --git a/cpu.c b/cpu.c index bfbe5a66f95..64e17537e21 100644 --- a/cpu.c +++ b/cpu.c @@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common =3D { =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); +#endif =20 cpu_list_add(cpu); =20 @@ -137,27 +139,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) } #endif /* CONFIG_TCG */ =20 -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else +#ifndef CONFIG_USER_ONLY if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + if (cc->sysemu_ops->vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } =20 void cpu_exec_unrealizefn(CPUState *cpu) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else - if (cc->vmsd !=3D NULL) { - vmstate_unregister(NULL, cc->vmsd, cpu); + if (cc->sysemu_ops->vmsd !=3D NULL) { + vmstate_unregister(NULL, cc->sysemu_ops->vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b9b431102f2..8d7a73d638e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps alpha_sysemu_ops =3D { + .vmsd =3D &vmstate_alpha_cpu, }; #endif =20 @@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_alpha_cpu; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 994e7b344d4..e03977e4c3c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps arm_sysemu_ops =3D { + .vmsd =3D &vmstate_arm_cpu, }; #endif =20 @@ -2304,7 +2305,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->vmsd =3D &vmstate_arm_cpu; cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 84f7ad4167e..b455a5e3434 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static struct SysemuCPUOps avr_sysemu_ops =3D { + .vmsd =3D &vms_avr_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->vmsd =3D &vms_avr_cpu; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index a97ad7c9c65..3ffd47c488d 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps cris_sysemu_ops =3D { + .vmsd =3D &vmstate_cris_cpu, }; #endif =20 @@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_cris_cpu; cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 48946cf6669..ba6401a4979 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps hppa_sysemu_ops =3D { + .vmsd =3D &vmstate_hppa_cpu, }; #endif =20 @@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_hppa_cpu; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fa517555e73..2d1e61da8ea 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps i386_sysemu_ops =3D { + .vmsd =3D &vmstate_x86_cpu, }; #endif =20 @@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; - cc->vmsd =3D &vmstate_x86_cpu; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 2d8d16d5535..bc754034c7e 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps lm32_sysemu_ops =3D { + .vmsd =3D &vmstate_lm32_cpu, }; #endif =20 @@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_lm32_cpu; cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5c43981c35d..1641cf87a52 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps m68k_sysemu_ops =3D { + .vmsd =3D &vmstate_m68k_cpu, }; #endif =20 @@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_m68k_cpu; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 34a60edd1cc..f59a1dd8576 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps mb_sysemu_ops =3D { + .vmsd =3D &vmstate_mb_cpu, }; #endif =20 @@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; - cc->vmsd =3D &vmstate_mb_cpu; cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index ea9259896f2..50ab8f2a88c 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps mips_sysemu_ops =3D { + .vmsd =3D &vmstate_mips_cpu, }; #endif =20 @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_mips_cpu; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index dbc9e022b61..86f6665a048 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) } =20 static struct SysemuCPUOps moxie_sysemu_ops =3D { + .vmsd =3D &vmstate_moxie_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -125,7 +126,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->sysemu_ops =3D &moxie_sysemu_ops; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 57023e38cb8..971c0d8a00a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -25,6 +25,7 @@ #include "exec/log.h" #include "exec/gdbstub.h" #include "hw/qdev-properties.h" +#include "migration/vmstate.h" =20 static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { @@ -208,7 +209,13 @@ static Property nios2_properties[] =3D { }; =20 #ifndef CONFIG_USER_ONLY +static const VMStateDescription vmstate_nios2_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static struct SysemuCPUOps nios2_sysemu_ops =3D { + .vmsd =3D &vmstate_nios2_cpu, }; #endif =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e00678ae038..55eb195df40 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps openrisc_sysemu_ops =3D { + .vmsd =3D &vmstate_openrisc_cpu, }; #endif =20 @@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_openrisc_cpu; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fd85e6fc6af..3e42f7265eb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -582,6 +582,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps riscv_sysemu_ops =3D { + /* For now, mark unmigratable: */ + .vmsd =3D &vmstate_riscv_cpu, }; #endif =20 @@ -627,8 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; - /* For now, mark unmigratable: */ - cc->vmsd =3D &vmstate_riscv_cpu; cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 812cf718732..cb8718a58dc 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -174,7 +174,13 @@ static void rx_cpu_init(Object *obj) } =20 #ifndef CONFIG_USER_ONLY +static const VMStateDescription vmstate_rx_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static struct SysemuCPUOps rx_sysemu_ops =3D { + .vmsd =3D &vmstate_rx_cpu, }; #endif =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 0efb1381647..a480f4abbaf 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps s390_sysemu_ops =3D { + .vmsd =3D &vmstate_s390_cpu, }; #endif =20 @@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 41f1c7c0507..038dfa25e84 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -218,13 +218,14 @@ static void superh_cpu_initfn(Object *obj) env->movcal_backup_tail =3D &(env->movcal_backup); } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_sh_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; =20 -#ifndef CONFIG_USER_ONLY static struct SysemuCPUOps sh4_sysemu_ops =3D { + .vmsd =3D &vmstate_sh_cpu, }; #endif =20 @@ -268,7 +269,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->gdb_num_core_regs =3D 59; =20 - cc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 377378ca1f2..6a324c2765b 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps sparc_sysemu_ops =3D { + .vmsd =3D &vmstate_sparc_cpu, }; #endif =20 @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_sparc_cpu; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 75f8a2d8014..f1f72be8281 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "qemu/error-report.h" +#include "migration/vmstate.h" =20 static inline void set_feature(CPUTriCoreState *env, int feature) { @@ -142,7 +143,13 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +static const VMStateDescription vmstate_tricore_cpu =3D { + .name =3D "cpu", + .unmigratable =3D 1, +}; + static struct SysemuCPUOps tricore_sysemu_ops =3D { + .vmsd =3D &vmstate_tricore_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 37e57178657..50a61ac0b83 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { }; =20 static struct SysemuCPUOps uc32_sysemu_ops =3D { + .vmsd =3D &vmstate_uc32_cpu, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_uc32_cpu; cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 7b925468203..7efe5b4f207 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -176,13 +176,14 @@ static void xtensa_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_xtensa_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; =20 -#ifndef CONFIG_USER_ONLY static struct SysemuCPUOps xtensa_sysemu_ops =3D { + .vmsd =3D &vmstate_xtensa_cpu, }; #endif =20 @@ -224,7 +225,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - cc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index a835bd86214..b5ed1dbfd26 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps ppc_sysemu_ops =3D { + .vmsd =3D &vmstate_ppc_cpu, }; #endif =20 @@ -10890,7 +10891,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_ppc_cpu; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.50 as permitted sender) client-ip=209.85.218.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614635540; cv=none; d=zohomail.com; s=zohoarc; b=N45ruAEvTsbzLgTxPz4hCmp4QVUkdenEAvsW8j/r7fQubpw9xg+97BQbg03FPWAQYqH//PnQHhovgkvsalbD2rLehIfvtCC3Tx+hwhDNtjNiYYAUeXlZYF1eK4+/53pVOCEqPTOyf3K+qGALS19d/vei/OU0XtyoV2hzGIW09ys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635540; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id z13sm16422668edc.73.2021.03.01.13.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:52:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WaQE95EZW9w0jtG86ZuVDK+2I8kDeUh8Unqfgkk9oi8=; b=dJQ4UANzR76b3eYWMyKZ+He1nEuDTPwS4OZNkrIHDXleHTj1Hux1ASLPymQAFMJSRb 2+DKOrVNXenpXyVJDNHdzsJdJKDuUWAj3kLOhmB25ecCaR9ZN6SABD2G43yRtV89cyaF +5ltmjdUxUmzkEQhL3frqVYbA/uyqO5SklhXQV8PR9j2+SbsO8M1wG5RowwIVXYb22RG B2N+65359kzj2XsyxC2AnTYTdKDrQ3JGunj5UvB2MJu2FBVAySmQVjkRHflpe3687HKV lf7Hx60vVu7XwMa3mhO/Qur9cIa0GF069048V1Nvmc6VT+QcyEl6YP4OrPA/YGyhAzpN E1Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=WaQE95EZW9w0jtG86ZuVDK+2I8kDeUh8Unqfgkk9oi8=; b=fHm2fkPgsWVYjSTdIpD0RrnVYDMV4Y/gRXLKDT5FvCZkc5AcWJWYGvN0U9Y1f1Y6Ha 0UIEcZuvXmcar89kTg4OgjVgEPjTpqsdgYCdLFTTid5iapdiV6o+a1L2t7S9f/TTztBX cYWeiRhVrcK4e7s8e7lRANEWXnII88jJqexYupmOyI+5ASCmRPksGSyuA/Xs/TlDnMVe mlO/p9Dsx29O94ic5AofkFy8/xn3gSv+FIIpuRemdD98FYVn839wdrUSxDZUaD72MGD8 S1xrWjIN04l5ZAAWBiBKJszTP+qMGemcVM6dHTK3i2i/7nXJkyljzf5HwUPXXzxY8BD3 HFHQ== X-Gm-Message-State: AOAM532U35gTmJtdJ1y5f9NPrUhmEnzdH4gMnUZsSuUVMtfyUTBzztbH CxNucr17UO+/hdtCtYcW89w= X-Google-Smtp-Source: ABdhPJx8YbyP/ysJIvbY6PD3CrlpttS9YDA8LjWAoN8qLWT6/WeDXT0T11P1nTCvwGIc16HQw24QwQ== X-Received: by 2002:a17:906:f10c:: with SMTP id gv12mr3059434ejb.53.1614635539084; Mon, 01 Mar 2021 13:52:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 09/17] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps Date: Mon, 1 Mar 2021 22:51:02 +0100 Message-Id: <20210301215110.772346-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) VirtIO devices are only meaningful with system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 ----- include/hw/core/sysemu-cpu-ops.h | 8 ++++++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/ppc/translate_init.c.inc | 4 +--- 5 files changed, 12 insertions(+), 11 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 471c99d9f04..dfb50b60128 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,10 +89,6 @@ struct AccelCPUClass; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @virtio_is_big_endian: Callback to return %true if a CPU which supports - * runtime configurable endianness is currently big-endian. Non-configurab= le - * CPUs can use the default implementation of this method. This method sho= uld - * not be used by any callers other than the pre-1.0 virtio devices. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. @@ -151,7 +147,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 05f19b22070..9c3ac4f2280 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,14 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts + * runtime configurable endianness is currently big-endian. + * Non-configurable CPUs can use the default implementation of this me= thod. + * This method should not be used by any callers other than the pre-1.0 + * virtio devices. + */ + bool (*virtio_is_big_endian)(CPUState *cpu); /** * @vmsd: State description for migration. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 5abf8bed2e4..09eaa3fa49f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->virtio_is_big_endian) { - return cc->virtio_is_big_endian(cpu); + if (cc->sysemu_ops->virtio_is_big_endian) { + return cc->sysemu_ops->virtio_is_big_endian(cpu); } return target_words_bigendian(); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e03977e4c3c..2bad6307cce 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps arm_sysemu_ops =3D { + .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .vmsd =3D &vmstate_arm_cpu, }; #endif @@ -2305,7 +2306,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index b5ed1dbfd26..2dd4f47adbb 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps ppc_sysemu_ops =3D { + .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .vmsd =3D &vmstate_ppc_cpu, }; #endif @@ -10913,9 +10914,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_core_xml_file =3D "power64-core.xml"; #else cc->gdb_core_xml_file =3D "power-core.xml"; -#endif -#ifndef CONFIG_USER_ONLY - cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif cc->disas_set_info =3D ppc_disas_set_info; =20 --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.47 as permitted sender) client-ip=209.85.208.47; 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Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 10/17] cpu: Move CPUClass::get_crash_info to SysemuCPUOps Date: Mon, 1 Mar 2021 22:51:03 +0100 Message-Id: <20210301215110.772346-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) cpu_get_crash_info() is called on GUEST_PANICKED events, which only occur in system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 1 - include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- target/s390x/cpu.c | 2 +- 5 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index dfb50b60128..781cd8fc42b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -150,7 +150,6 @@ struct CPUClass { int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); - GuestPanicInformation* (*get_crash_info)(CPUState *cpu); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 9c3ac4f2280..b9ffca07665 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_crash_info: Callback for reporting guest crash information in + * GUEST_PANICKED events. + */ + GuestPanicInformation* (*get_crash_info)(CPUState *cpu); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 09eaa3fa49f..0aebc18c41f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) CPUClass *cc =3D CPU_GET_CLASS(cpu); GuestPanicInformation *res =3D NULL; =20 - if (cc->get_crash_info) { - res =3D cc->get_crash_info(cpu); + if (cc->sysemu_ops->get_crash_info) { + res =3D cc->sysemu_ops->get_crash_info(cpu); } return res; } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2d1e61da8ea..b7672a7accc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps i386_sysemu_ops =3D { + .get_crash_info =3D x86_cpu_get_crash_info, .vmsd =3D &vmstate_x86_cpu, }; #endif @@ -7427,7 +7428,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->get_crash_info =3D x86_cpu_get_crash_info; cc->write_elf64_note =3D x86_cpu_write_elf64_note; cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index a480f4abbaf..04c14fcd9da 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps s390_sysemu_ops =3D { + .get_crash_info =3D s390_cpu_get_crash_info, .vmsd =3D &vmstate_s390_cpu, }; #endif @@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id cf6sm13288712edb.92.2021.03.01.13.52.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:52:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6w8yuNP2zUEwKLIo3lOsMB+G9xmXkg7KWNf3q3iE2oc=; b=t2iJIBFCVAKQEcBIcZipQNpz8ubr5Q9nRLeMJ6GslySjKtLZsvHRh8EV8Zp7G+IlJO SjZ2fjbTL7UbSpBoJqgDp0+DIhZA010VZFaR7jw6a0a+AfiJyAcIRpKouT9AyVnxXu1u 8qQpCypKtM+tp9DAMgQ5E9mi9TJoKcBdno8hJ1qa9VVJtdmBLz1ujXs3fFnUKcdLaR3d vaxmppc3ySbOs07SXHeuloKw69jA60MomOZXGmg1CLT6EGBwkoFh+Jasi3fYyvHzVMQA vv8Za7OFyL2Pj84KJ9SeDTZYAuIuZNPeWTd7q3VylIEdVMtGEY7T6K2BCyXgZguve7dR Y9Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6w8yuNP2zUEwKLIo3lOsMB+G9xmXkg7KWNf3q3iE2oc=; b=Kd0sqNkueSdSWYUTUNA4UI5+inUY08RVnAaOE1VkCy9kv6sx35EOT6Q/bV+p1kLnLX pj6OyPbqjT3Z3sP+gJd86qVtCGXt7G+qy5rMtR5aDP47+0Eo+WE90gSGlMHjhVpSTjA0 WUhwEq8kiaDSezhjo9LxBEedK+rzawgYoPfiFgT7gpoOdwJJz2Hz0SKPCMkmu2ug1sR0 vO9pp7WgEU++dI8u2bTV3V9DPi3rGA9HuuTyL+UpY8Bx4ANLz9ZGRiMd5S7QtzgGcEca zV7VWqwdvuxhXPb/lSTXboSeqWBWX5SBQ2X8YiA/AvKSrZgOohHvAYe3PaKSGeSWmBWH ESYA== X-Gm-Message-State: AOAM531aw+0poQlwPAC3gES6j5gT2sbP09EgIpTu/TlsQwzG4dfOnHFV sX4CnpIgwGRe/aWGnuwW2Jo= X-Google-Smtp-Source: ABdhPJyzg0Ru0qUvpGzWPMv50ICHMdqxS3+ztJRegmPICCkgZcWGXcia4d3njEnUkXiP0dxUh4bSvg== X-Received: by 2002:aa7:d44a:: with SMTP id q10mr10097384edr.278.1614635553279; Mon, 01 Mar 2021 13:52:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 11/17] cpu: Move CPUClass::write_elf* to SysemuCPUOps Date: Mon, 1 Mar 2021 22:51:04 +0100 Message-Id: <20210301215110.772346-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The write_elf*() handlers are used to dump vmcore images. This feature is only meaningful for system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 17 ----------------- include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++ hw/core/cpu.c | 16 ++++++++-------- target/arm/cpu.c | 4 ++-- target/i386/cpu.c | 8 ++++---- target/s390x/cpu.c | 2 +- target/ppc/translate_init.c.inc | 6 ++---- 7 files changed, 41 insertions(+), 36 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 781cd8fc42b..0a2c29c3735 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -112,14 +112,6 @@ struct AccelCPUClass; * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. - * @write_elf64_note: Callback for writing a CPU-specific ELF note to a - * 64-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. - * @write_elf32_note: Callback for writing a CPU-specific ELF note to a - * 32-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -163,15 +155,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 - int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index b9ffca07665..60c667801ef 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,30 @@ typedef struct SysemuCPUOps { * GUEST_PANICKED events. */ GuestPanicInformation* (*get_crash_info)(CPUState *cpu); + /** + * @write_elf32_note: Callback for writing a CPU-specific ELF note to a + * 32-bit VM coredump. + */ + int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf64_note: Callback for writing a CPU-specific ELF note to a + * 64-bit VM coredump. + */ + int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 32-bit VM coredump. + */ + int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + /** + * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 64-bit VM coredump. + */ + int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 0aebc18c41f..c74390aafbf 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_qemunote) { + if (!cc->sysemu_ops->write_elf32_qemunote) { return 0; } - return (*cc->write_elf32_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_note) { + if (!cc->sysemu_ops->write_elf32_note) { return -1; } - return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque); } =20 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, @@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_qemunote) { + if (!cc->sysemu_ops->write_elf64_qemunote) { return 0; } - return (*cc->write_elf64_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_note) { + if (!cc->sysemu_ops->write_elf64_note) { return -1; } - return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); } =20 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2bad6307cce..7dc6956f2cc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps arm_sysemu_ops =3D { + .write_elf32_note =3D arm_cpu_write_elf32_note, + .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .vmsd =3D &vmstate_arm_cpu, }; @@ -2306,8 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->write_elf64_note =3D arm_cpu_write_elf64_note; - cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b7672a7accc..b26905b22a3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7389,6 +7389,10 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps i386_sysemu_ops =3D { .get_crash_info =3D x86_cpu_get_crash_info, + .write_elf32_note =3D x86_cpu_write_elf32_note, + .write_elf64_note =3D x86_cpu_write_elf64_note, + .write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote, + .write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote, .vmsd =3D &vmstate_x86_cpu, }; #endif @@ -7428,10 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->write_elf64_note =3D x86_cpu_write_elf64_note; - cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; - cc->write_elf32_note =3D x86_cpu_write_elf32_note; - cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 04c14fcd9da..92b7a66d3c3 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps s390_sysemu_ops =3D { .get_crash_info =3D s390_cpu_get_crash_info, + .write_elf64_note =3D s390_cpu_write_elf64_note, .vmsd =3D &vmstate_s390_cpu, }; #endif @@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 2dd4f47adbb..068f4a4012e 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,6 +10845,8 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps ppc_sysemu_ops =3D { + .write_elf32_note =3D ppc32_cpu_write_elf32_note, + .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .vmsd =3D &vmstate_ppc_cpu, }; @@ -10894,10 +10896,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif -#if defined(CONFIG_SOFTMMU) - cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; - cc->write_elf32_note =3D ppc32_cpu_write_elf32_note; -#endif =20 cc->gdb_num_core_regs =3D 71; #ifndef CONFIG_USER_ONLY --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.47 as permitted sender) client-ip=209.85.208.47; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id e18sm14991555eji.111.2021.03.01.13.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:52:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GB8inY6UkxSK7b05oz5LFm6GUiIud2UztI6zOEllLW8=; b=LtIjyOZgMv531D8H1UJnIR+kYlAWbgfATlcWyiQeDJijrcZ8ogwa+y9isXg38wOaeN ajgfzgrtU4EfBl3DL/FcWJ/jaaGhv+EcMUqOzEHDgMCN+QfAU0gAyBs+L9f6BqE5R5Ul ItDcQMOZKnBcOovAttPYahqxYPiGiQ1AwH2aI+n0rzoa4BWVa00alO0sCf6bnLilFC1m SfCvewhFkr8TA/1eDR/N/vi5DVn//uBry5fp/qbvm2g1+ZKEDtajm1ecwDiMxHaEhZjb 6IsZL/EM7yX9Z8rdS4sVmbBknofJ49H0PCbDig1COFs202lDrkQBGoKMK3kxmPCwWq01 4VEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GB8inY6UkxSK7b05oz5LFm6GUiIud2UztI6zOEllLW8=; b=RA/DO/8ufpwo+5bnWw1OHSmW798LNgqCaYrk1Xo89Si9s7XmshKYH3IQ5Zqu57te8h oMMBVMLNjXHFCfljsDoyPpOlVEpa3iwQNmDrW5akk2huNNu/chOa5lUFhaARe/j0YwYc 6pjPSHfWdjzKj7DesfrIctp3pEl5oIqWpujBWrxSrd+K6Z/1/fShzAyUhHmiGm0k2nwR GKj+z+vmCEGdLyqHk6jbMQMYM59GFjipve6NZwUjBA3ULlrdcZqLVGpDy/Luo6H1Dexy 3VS9sq10Xn2LrvtxHK68XU/UTJv/0l29s6NiVruAe75fev/ggGIK88rCEafl/y6xb3bG 41oA== X-Gm-Message-State: AOAM531IQ5N8iUyvpfW2drdkyKXAInZAU8pDEIoD4bND7t87XfTfuVLz 6TGDItEQPA0jmeP/eammX3g= X-Google-Smtp-Source: ABdhPJyffC80a2OCvMEOq5yWR/Hs0q0IJZ5yuVpvoR5nsPSEjPtLvpZezlQoxmEb4jtjtirjdGznGw== X-Received: by 2002:aa7:c983:: with SMTP id c3mr11114617edt.185.1614635560323; Mon, 01 Mar 2021 13:52:40 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 12/17] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps Date: Mon, 1 Mar 2021 22:51:05 +0100 Message-Id: <20210301215110.772346-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 0a2c29c3735..6713a615916 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -108,8 +108,6 @@ struct AccelCPUClass; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -151,7 +149,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 60c667801ef..3c3f211136d 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or + * a memory access with the specified memory transaction attribu= tes. + */ + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); /** * @get_crash_info: Callback for reporting guest crash information in * GUEST_PANICKED events. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c74390aafbf..c44229205ff 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attr= s) CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); + if (cc->sysemu_ops->asidx_from_attrs) { + ret =3D cc->sysemu_ops->asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7dc6956f2cc..acaa3ab68da 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps arm_sysemu_ops =3D { + .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, @@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; - cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b26905b22a3..10884540610 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps i386_sysemu_ops =3D { + .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, .write_elf64_note =3D x86_cpu_write_elf64_note, @@ -7429,7 +7430,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.45 as permitted sender) client-ip=209.85.208.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614635569; cv=none; d=zohomail.com; s=zohoarc; b=PVlKuoDgakMJAZPJKxWI7IeauAD6+Ber3H14tEaor8LWYCLGwq3/QZo5xauagzXDlCTwhHVATOEpGSPHkbDHLjl5T2V+Y72gHbYBIODFG/p5hp6G8BgJpcmhUbhVOqh+wBaxS1gpkVj+sHK2TdLP1Vwr8gdxpfTHUUaVxrUVWxI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635569; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id i17sm17293385ejo.25.2021.03.01.13.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:52:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dgsnoJxYfQ+EnbpTe4VgFeqBOMAHdGvYFMjn+ks1sAo=; b=XI6zPdS9eJ1aBK9gmQYmBkS7YZvV3tECkqHz0msMNg3evk4rzS7Dl2ZDKb2Hy+VPTc FU1sWew1bEjktH7BNz6SRJrMeV+JF8ysoyv5W5avy9FClxpmFUlP7P3Gr+27WhLbTPVa CjgJ0SIgyjY6Nk/h/noWl7hoqPMYmnBuoLSJqggLw+LgQHSo/EwAucOqxYd0sJz6BbX/ Lxf3M4uA7NBaY0zdt5zcz4H4B6OIhlku2HB4KujPGj/j6xXwsDRA3YnqV0A9gY98f7FU Uj7a/6sXLHuHZF00cB154zTWNvd1j7wunlrayQqNOm2EpdzzTN5PbBM6kcwW0TTTkthM HCJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dgsnoJxYfQ+EnbpTe4VgFeqBOMAHdGvYFMjn+ks1sAo=; b=AQaT3E451rWNS0VRoNBRpM/MUL7zOI8z6dHmUWJ1ig7CYPrJhvBF2XIZ0qUYwc9q5R dF3tpt6x877Iaur12luePLHZbPvkvJJEQDFh9dd7WiyBuPnsdheBG7IzL0d5h7e2oAzJ 0UxgMRqu0syG7piwmOT0SBpPtTnXz5nbMclItVMH+fu89yCTE1PpDilWfH9pSExOKiVx mlP/LPoE3zlQEAw9bOxa0L7lV1tcqVFU4/1b+zW20FJRe6LEyJ5DhPQsCfQ3LRI4ic+E 8/5Q5UAosE3EoL+EWnjKQ7aqL2h0owSwbvgcf4S3uY/xiPZaLUkCLPDIGRfGIc7RYHjx opgA== X-Gm-Message-State: AOAM530nFSbSr5rDyR4E28aSi/GPEtkp0di2/6YdfdOTA2uQNK0ogEB5 Jl9T7huV0SzPo63EV6eiuVd1QLdI2mo= X-Google-Smtp-Source: ABdhPJySCNOFM1vDkKKWFKbW7N65o9FyAc11F/NrjK31ZiIRNhaQb5FsY/54Jo8FVLFAPAgV0rXTqA== X-Received: by 2002:a05:6402:9:: with SMTP id d9mr12058645edu.67.1614635567624; Mon, 01 Mar 2021 13:52:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 13/17] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps Date: Mon, 1 Mar 2021 22:51:06 +0100 Message-Id: <20210301215110.772346-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 8 -------- include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++ hw/core/cpu.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 4 +--- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 25 files changed, 38 insertions(+), 35 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6713a615916..9a86c707cf7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,11 +103,6 @@ struct AccelCPUClass; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -146,9 +141,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 3c3f211136d..0c8f616a565 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,19 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * and the associated memory transaction attributes to use for t= he + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index c44229205ff..6932781425a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cc->sysemu_ops->get_phys_page_attrs_debug) { + return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); + return cc->sysemu_ops->get_phys_page_debug(cpu, addr); } =20 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 8d7a73d638e..d9a51d9f647 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps alpha_sysemu_ops =3D { + .get_phys_page_debug =3D alpha_cpu_get_phys_page_debug, .vmsd =3D &vmstate_alpha_cpu, }; #endif @@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index acaa3ab68da..6cd546213de 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps arm_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, @@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index b455a5e3434..040d3526995 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static struct SysemuCPUOps avr_sysemu_ops =3D { + .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, .vmsd =3D &vms_avr_cpu, }; =20 @@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; - cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 3ffd47c488d..77f821f4d9a 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps cris_sysemu_ops =3D { + .get_phys_page_debug =3D cris_cpu_get_phys_page_debug, .vmsd =3D &vmstate_cris_cpu, }; #endif @@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ba6401a4979..7de37aadd4d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps hppa_sysemu_ops =3D { + .get_phys_page_debug =3D hppa_cpu_get_phys_page_debug, .vmsd =3D &vmstate_hppa_cpu, }; #endif @@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 10884540610..c7a18cd8e4f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps i386_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, @@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 #ifndef CONFIG_USER_ONLY cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index bc754034c7e..c80cae9ff3b 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps lm32_sysemu_ops =3D { + .get_phys_page_debug =3D lm32_cpu_get_phys_page_debug, .vmsd =3D &vmstate_lm32_cpu, }; #endif @@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->sysemu_ops =3D &lm32_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1641cf87a52..eaf5f34d22c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps m68k_sysemu_ops =3D { + .get_phys_page_debug =3D m68k_cpu_get_phys_page_debug, .vmsd =3D &vmstate_m68k_cpu, }; #endif @@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) - cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f59a1dd8576..a21f15192ae 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps mb_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug, .vmsd =3D &vmstate_mb_cpu, }; #endif @@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 50ab8f2a88c..285564b4d5b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -682,6 +682,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps mips_sysemu_ops =3D { + .get_phys_page_debug =3D mips_cpu_get_phys_page_debug, .vmsd =3D &vmstate_mips_cpu, }; #endif @@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 86f6665a048..47b8735bb75 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *c= pu_model) } =20 static struct SysemuCPUOps moxie_sysemu_ops =3D { + .get_phys_page_debug =3D moxie_cpu_get_phys_page_debug, .vmsd =3D &vmstate_moxie_cpu, }; =20 @@ -124,9 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->has_work =3D moxie_cpu_has_work; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; -#ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; -#endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->sysemu_ops =3D &moxie_sysemu_ops; cc->tcg_ops =3D &moxie_tcg_ops; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 971c0d8a00a..e5cbf43d6ee 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -215,6 +215,7 @@ static const VMStateDescription vmstate_nios2_cpu =3D { }; =20 static struct SysemuCPUOps nios2_sysemu_ops =3D { + .get_phys_page_debug =3D nios2_cpu_get_phys_page_debug, .vmsd =3D &vmstate_nios2_cpu, }; #endif @@ -249,7 +250,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 55eb195df40..c666e86e919 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps openrisc_sysemu_ops =3D { + .get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug, .vmsd =3D &vmstate_openrisc_cpu, }; #endif @@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3e42f7265eb..eaf7c13e5a6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -582,6 +582,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps riscv_sysemu_ops =3D { + .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, /* For now, mark unmigratable: */ .vmsd =3D &vmstate_riscv_cpu, }; @@ -628,7 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index cb8718a58dc..d1a7a5f6877 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -180,6 +180,7 @@ static const VMStateDescription vmstate_rx_cpu =3D { }; =20 static struct SysemuCPUOps rx_sysemu_ops =3D { + .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, .vmsd =3D &vmstate_rx_cpu, }; #endif @@ -218,7 +219,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) #endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; - cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 92b7a66d3c3..30117fc8cd7 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps s390_sysemu_ops =3D { + .get_phys_page_debug =3D s390_cpu_get_phys_page_debug, .get_crash_info =3D s390_cpu_get_crash_info, .write_elf64_note =3D s390_cpu_write_elf64_note, .vmsd =3D &vmstate_s390_cpu, @@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 038dfa25e84..843f39de41c 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { }; =20 static struct SysemuCPUOps sh4_sysemu_ops =3D { + .get_phys_page_debug =3D superh_cpu_get_phys_page_debug, .vmsd =3D &vmstate_sh_cpu, }; #endif @@ -262,7 +263,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sh4_sysemu_ops; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 6a324c2765b..c8a115c886a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps sparc_sysemu_ops =3D { + .get_phys_page_debug =3D sparc_cpu_get_phys_page_debug, .vmsd =3D &vmstate_sparc_cpu, }; #endif @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index f1f72be8281..0c4b5021e79 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -149,6 +149,7 @@ static const VMStateDescription vmstate_tricore_cpu =3D= { }; =20 static struct SysemuCPUOps tricore_sysemu_ops =3D { + .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, .vmsd =3D &vmstate_tricore_cpu, }; =20 @@ -180,7 +181,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 50a61ac0b83..610fb5393ae 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu =3D { }; =20 static struct SysemuCPUOps uc32_sysemu_ops =3D { + .get_phys_page_debug =3D uc32_cpu_get_phys_page_debug, .vmsd =3D &vmstate_uc32_cpu, }; =20 @@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D uc32_cpu_has_work; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->sysemu_ops =3D &uc32_sysemu_ops; cc->tcg_ops =3D &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 7efe5b4f207..44a4524bc0a 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { }; =20 static struct SysemuCPUOps xtensa_sysemu_ops =3D { + .get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug, .vmsd =3D &vmstate_xtensa_cpu, }; #endif @@ -222,7 +223,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &xtensa_sysemu_ops; - cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; cc->tcg_ops =3D &xtensa_tcg_ops; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 068f4a4012e..d38d194fe87 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps ppc_sysemu_ops =3D { + .get_phys_page_debug =3D ppc_cpu_get_phys_page_debug, .write_elf32_note =3D ppc32_cpu_write_elf32_note, .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, @@ -10893,7 +10894,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id n2sm15596030ejl.1.2021.03.01.13.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:52:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=80i+luS2gU1nZWsoBAiYbRUL/K5YnYdp7E5uXZjJBL4=; b=gPfj5PeGZg2x+XNFTJcwXjcE1X/xtVf//5uzWDW4Au2WoljQRlWs+7BQTvGRTb3TqA SSK760ZD+iNVI/cCpoMvsR7UzU/FAR16G49PY7z1LzzOra6wnIXqvv/8+Y0mG7OC27jv M5WUf0nc08szLLWSb/ralvgpdr7CbgvNAKa1PjC7SNbY4bqNTppg3rVeshlV2XpjqfC+ rHVNUrwQBuRcKRpxQ9Fu3KG0vPt7zOGRUxfmQ7E+MavAYUUWzIu58eFIB+ObuO6XqOen WAwE3qcKO3H4jy9D99yOVbFRpOW674cQyAKyAhuiHStyXjN4C3gRzlpJwUl4v6Wb+dhE 7Otg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=80i+luS2gU1nZWsoBAiYbRUL/K5YnYdp7E5uXZjJBL4=; b=umf2d1oHWLyBZvuMQk3FxBXeJ8/+mQMst1trAYoTqM4cICy1JO45yfV+JohtmZfiv2 SDC1RQMVm5AzWgfAwfN+qdxbVngj/+n+FRFwFaBHkWhHcjczLPeRhS4r+rlUUhdsgN7K NHkEdKp9arAtUSZCa4JErePc0URna1YxmY7hQ5U23ZhfUaAEMh0DWGIMXn1CZqczajfu ylD2qTraVv9Ork33wQMD0cTU0Qe2ZqqDcF0OTFy2IC8irfDerhrrDpRH2zlWlh8iQIiD XvhjB5fSQtvmYQuFcQ954moGxHaJayG7gO5KBUyF66iYsTcwxxgJI1lWMSdqvS0v+6nR i2WQ== X-Gm-Message-State: AOAM531LtGpuGpyQDFX0bg9sjP8xHTcNa+IWSSaO0My53aFPfQomjEPu x6hw9cnGvMbUYwho5FqgvMs= X-Google-Smtp-Source: ABdhPJwIP2JIQA5wI0AQpMRVb9QayOV7PdiRN6lfNAG3+Ll75D9ZBZ1t+KmAn4WpidlUEygmumXREA== X-Received: by 2002:a17:906:f88a:: with SMTP id lg10mr18075135ejb.39.1614635574975; Mon, 01 Mar 2021 13:52:54 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 14/17] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps Date: Mon, 1 Mar 2021 22:51:07 +0100 Message-Id: <20210301215110.772346-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 9a86c707cf7..8af78cdde23 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -94,7 +94,6 @@ struct AccelCPUClass; * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled. - * @get_memory_mapping: Callback for obtaining the memory mappings. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -138,8 +137,6 @@ struct CPUClass { void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); - void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, - Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 0c8f616a565..460e7d63b0c 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_memory_mapping: Callback for obtaining the memory mappings. + */ + void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, + Error **errp); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 6932781425a..339bdfadd7a 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingL= ist *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_memory_mapping) { - cc->get_memory_mapping(cpu, list, errp); + if (cc->sysemu_ops->get_memory_mapping) { + cc->sysemu_ops->get_memory_mapping(cpu, list, errp); return; } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c7a18cd8e4f..d33ee9f831e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps i386_sysemu_ops =3D { + .get_memory_mapping =3D x86_cpu_get_memory_mapping, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.46 as permitted sender) client-ip=209.85.208.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614635583; cv=none; d=zohomail.com; s=zohoarc; b=KuW1KGGYRBci4YfpUh51n11PV4b6TtQABQ/wsBr51xzkyBBvTvaVmy/5b5mtkX+PtNIsi+s5S1HI+xaoSflrGebKUTU/DQFXFq3oiPug3sHK/hRM944xszbkyDck1xTWaJr+hjE25nsvUZkfKW51Il7dWXtIxOaNDgUgG3U6QJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635583; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MXkQdWgohB9uSSp9OtT22O1oCJ949jTBzJW7O9qsdTc=; b=X5i7Ra4Z05MgPCuzvuDhPl3P1HlziD7095BVS64N4BuqhYwaz0QrzcZIXY1rmd6cfSjWVjA/QvuwH36W/KV+0nzibIpsquTwyFbemqyxMXvuY0SQSNTL3VzaV+EDO+az01a40qk7Je0AunLXnHsroFKd7+P8+3ZdxnFNrFP0Nno= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) by mx.zohomail.com with SMTPS id 1614635583681547.8405414340981; Mon, 1 Mar 2021 13:53:03 -0800 (PST) Received: by mail-ed1-f46.google.com with SMTP id d13so17721548edp.4 for ; Mon, 01 Mar 2021 13:53:03 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id y8sm10716968eju.31.2021.03.01.13.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:53:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MXkQdWgohB9uSSp9OtT22O1oCJ949jTBzJW7O9qsdTc=; b=hNZjpVdrVI63phJbFYUzDIPLoonxJsaqtraOR5sYfaAoSgzWe7io18UVu0L6m7RhH4 bebZKBGTfRRLxU6MTxQX4UltQ7Smz38CS4M/cEI5pYD1dNlLhequCNf+vWDETmDo+Onn t/WipwsglUfsAUmVlJ+abKHbUhazMEvHJTmOxqYKUIYZvs3BqBuJYyeF5CC5n4vdYDS3 ZqAZV9zwDoHgK+LaBvifxtvxJmBxCg5CP0surZ2LI8zceyYSu5iiqK9HlY4Dw09AUUWB 7gevru6kx7Z4Ju8EX7X6p7zbhTT6MIpuQz0qEQ96pP/IcaSjzp4yqsdLKQ+iScPEJa1x wE4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=MXkQdWgohB9uSSp9OtT22O1oCJ949jTBzJW7O9qsdTc=; b=G4qWSs0VGAyQm4JyxMJBuqKrZodu7kTPOvEF+xvENjlBitpyOT+O4cIkxGKckmfyoJ om2MyBE1e6nF6mJZEK+nIRp6NLH58I9zMnKFNOoktJAe/su/phu3An8FSSL+eo7HzzZS z0PqfiNE0BEjOlYPAb/CcdmI3sKL9sK/fvcgG7YkbZZGqw6Hs8qkLMBan4GhpR54FI3T O4F6eCCWMG/GUUwFZjKplTzvpAzfSomRMLkVlNo9A0HQrEE1ntWT9XV3WK9OwRQFjhHD Zm+kBxcDI2cCrPmHXK0FQXUc7Ev9BWqzIXHuvA2OYsyZwYX6eTpbeP22yl8+O/tavx8Q IXaw== X-Gm-Message-State: AOAM5311KMGU8COF+YbVd08XGxmFDXrwhRK7otlw9v1uhvSVVCtUacgw qlICtikKwFrPzS8v3VCkyxY= X-Google-Smtp-Source: ABdhPJypEelAe2MQJO+QsAlt6vhlOKERbfLpxu5hJmk9ARnOY43j4ecWuvtrsDfZSyTh/d4Ud0/o6Q== X-Received: by 2002:a05:6402:31b7:: with SMTP id dj23mr18452684edb.245.1614635581892; Mon, 01 Mar 2021 13:53:01 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 15/17] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps Date: Mon, 1 Mar 2021 22:51:08 +0100 Message-Id: <20210301215110.772346-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 2 -- include/hw/core/sysemu-cpu-ops.h | 4 ++++ hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 4 +++- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8af78cdde23..960846d2b64 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -93,7 +93,6 @@ struct AccelCPUClass; * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. - * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -136,7 +135,6 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); - bool (*get_paging_enabled)(const CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 460e7d63b0c..3f9a5199dd1 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,10 @@ typedef struct SysemuCPUOps { */ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); + /** + * @get_paging_enabled: Callback for inquiring whether paging is enabl= ed. + */ + bool (*get_paging_enabled)(const CPUState *cpu); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 339bdfadd7a..7a8487d468f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_paging_enabled) { - return cc->get_paging_enabled(cpu); + if (cc->sysemu_ops->get_paging_enabled) { + return cc->sysemu_ops->get_paging_enabled(cpu); } =20 return false; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d33ee9f831e..3519cef8fba 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7157,12 +7157,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs) return cpu->apic_id; } =20 +#if !defined(CONFIG_USER_ONLY) static bool x86_cpu_get_paging_enabled(const CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 return cpu->env.cr[0] & CR0_PG_MASK; } +#endif /* !CONFIG_USER_ONLY */ =20 static void x86_cpu_set_pc(CPUState *cs, vaddr value) { @@ -7389,6 +7391,7 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static struct SysemuCPUOps i386_sysemu_ops =3D { .get_memory_mapping =3D x86_cpu_get_memory_mapping, + .get_paging_enabled =3D x86_cpu_get_paging_enabled, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -7429,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; - cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.45 as permitted sender) client-ip=209.85.218.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614635590; cv=none; d=zohomail.com; s=zohoarc; b=UiUifSMovs5gBEpH0VpGN8cTvJWq30u0GRapLbltpP14r4TeVP6Bh8+7R//8YYFKRHKdf1U3r67JSed7BgmGQh0vUNJnOGUuGDKLtCqlIyEW+DtHv+KrsdlX5tkC6JIyNUxocnPtVqYv7x5mGuzsfcNW1eTNDBsMpDmeQ4GXjX0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635590; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2UJf+T8AbVyetglv75P3vpefSV1VtMBl6vQz8AR9Gio=; b=eKoA5Fi8d1Ropapdmx63HN68n8jyZL5Gh+wKNFszWU2UHcz9Nz7+vWHn/B4uP4wYbPqvOwbRbPzXDrkHnvkoo8Nuv/kSEVLJlLF35mLmaIZWmenxP8SdTGK8X+cwboe3f1WPZTkNviutTAV2ftRzmuhLu/4gg8I3OX5JWA3fnL0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) by mx.zohomail.com with SMTPS id 1614635590543690.06966662061; Mon, 1 Mar 2021 13:53:10 -0800 (PST) Received: by mail-ej1-f45.google.com with SMTP id do6so31205994ejc.3 for ; Mon, 01 Mar 2021 13:53:09 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. 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Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [PATCH v2 16/17] cpu: Restrict cpu_paging_enabled / cpu_get_memory_mapping to sysemu Date: Mon, 1 Mar 2021 22:51:09 +0100 Message-Id: <20210301215110.772346-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 960846d2b64..d99d3c830dc 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -427,6 +427,8 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) extern bool mttcg_enabled; #define qemu_tcg_mttcg_enabled() (mttcg_enabled) =20 +#if !defined(CONFIG_USER_ONLY) + /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. @@ -444,8 +446,6 @@ bool cpu_paging_enabled(const CPUState *cpu); void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, Error **errp); =20 -#if !defined(CONFIG_USER_ONLY) - /** * cpu_write_elf64_note: * @f: pointer to a function that writes memory to a file --=20 2.26.2 From nobody Mon May 20 21:02:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.48 as permitted sender) client-ip=209.85.218.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614635598; cv=none; d=zohomail.com; s=zohoarc; b=ZrH+WjmeJEOIoiLUwp/lDnr3cgmx7ralkZxxFUB0s4RYWU4nNArJXwi3JrRxAZTVUZy3c8bOny2ae6NMwCe5Ua7Hd+rkEZQdJfLxOSHEAuBv/b0Yr7lTZeqIJfEN/7nmZ/+IjI4EbcSSG6sbKIMrhHCiNBB1mNKTrS9oGxXWzC0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614635598; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Pw9WC6vACp5fmsq1o7bIBFCUdYDUl5sYsIdhjFrN0KY=; b=eNgr+upGslku0FhmOezCYqvBFY9UrAlGCV/nPST7dQm5y169rigk1RY/pThUVyL8x3P97WZrYr8tmGQqjcBEDtWlNtUgHMkpYDETG3T2NKbt75SiZFOvcc2bxsL6bwOdn6hVKPYSrs180YZJCaZuka03yPksTSDqKA+Kg/JIFsg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) by mx.zohomail.com with SMTPS id 1614635597995967.415419771463; Mon, 1 Mar 2021 13:53:17 -0800 (PST) Received: by mail-ej1-f48.google.com with SMTP id hs11so31190336ejc.1 for ; Mon, 01 Mar 2021 13:53:17 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id d6sm15594748eje.20.2021.03.01.13.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 13:53:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Pw9WC6vACp5fmsq1o7bIBFCUdYDUl5sYsIdhjFrN0KY=; b=MGxFe2L36N+hppLecyhnAZ0T+o7raU+kemtTVvU5lLqmMNBspsPxpTQK9orkEX4eWE O5Q3Mo2mJydcaKT4Nm084bDstKf3+GaHyRH50eMbF2n9VptnxqFLQq3vtIX0BUneKOQQ qwwfwCmOpqZqIFTKI1ExBXIXvpbp87c4J8a5rH9Ahjew+ilLKR+mpRoDRRbiKB64ECA/ E5Nm8tsMEzB+b24jh7qs1yS9CwR6enC5BTUszF9MHuZXt1RWBIBjgBqCmu8jJP1oLKMC fm7FwW72VBb6tqLzFdbZglXvuO8Wp3m7rwRFjed7WQ4irGi78Vp4lrhD8BHDFbmb4opo mZ7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Pw9WC6vACp5fmsq1o7bIBFCUdYDUl5sYsIdhjFrN0KY=; b=NxHSfMt8dtvTQFJu9v8OJ67l8W9d4JWK+tw1Qoer99s2HPSFYl+sE5mz9xqu2GOOAN PrXQ3Qymxyih1xlwqzfg40xxJ+JAcYruOkSAMZZK/uh1HM+lEN25ztka+Ck+rsM7EFVz 4kcDIoLLE5HQetuX+D/PKxwpalDeLPvfw24DScQrVW0rxUKwI1jzeWO+0B3PhfieEG5E L4xNQ3zuFaqogOd5wubFoejz8yr5z9nhNuBjy4HpHDyrEJhZ92F+9CK3OhEtfpewQx7s ZNzLaJgBi/pr030QCzvNiqXFb738ZZ+fLk9Sthit3jdJ3CoEZVAYFTKEMd4KdH/pku+D lkTg== X-Gm-Message-State: AOAM53279B7WIgBQgR3SpGU3TEHyehFvXwqw2ZMbk5ZG4zxAwsZWl41w dQV4+U7/9hw4MkiZ9elau7M= X-Google-Smtp-Source: ABdhPJzWwl3yvTIxpsoEa72kFgGUoyEOZXVTtimWN96EyKE+ic0eqAt5tXNvPRAoPeHxcPdcl3w2Cg== X-Received: by 2002:a17:907:3e06:: with SMTP id hp6mr17900073ejc.254.1614635596186; Mon, 01 Mar 2021 13:53:16 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Michael Rolnik , Anthony Green , Jiaxun Yang , Peter Maydell , qemu-arm@nongnu.org, Marek Vasut , Paolo Bonzini , Stafford Horne , Palmer Dabbelt , Aleksandar Rikalo , qemu-s390x@nongnu.org, Chris Wulff , Marcel Apfelbaum , Yoshinori Sato , Aurelien Jarno , David Gibson , Sarah Harris , David Hildenbrand , Cornelia Huck , Richard Henderson , Sagar Karandikar , qemu-riscv@nongnu.org, Alistair Francis , qemu-ppc@nongnu.org, Laurent Vivier , Claudio Fontana , Michael Walle , Guan Xuetao , "Edgar E. Iglesias" , Artyom Tarasenko , Thomas Huth , "Michael S. Tsirkin" , Eduardo Habkost , Greg Kurz , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Max Filippov Subject: [RFC PATCH v2 17/17] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c Date: Mon, 1 Mar 2021 22:51:10 +0100 Message-Id: <20210301215110.772346-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210301215110.772346-1-f4bug@amsat.org> References: <20210301215110.772346-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"): We cannot in principle make the SysEmu Operations field definitions conditional on CONFIG_SOFTMMU in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the SysEmu fields to system emulation builds, is to move all sysemu operations into a separate header file, which is only included by system-specific code. This leaves just a NULL pointer in the cpu.h for the user-mode builds. Inspired-by: Claudio Fontana Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- RFC: improve commit description? include/hw/core/cpu.h | 3 ++- cpu.c | 1 + hw/core/cpu.c | 1 + target/alpha/cpu.c | 1 + target/arm/cpu.c | 1 + target/avr/cpu.c | 1 + target/cris/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/moxie/cpu.c | 1 + target/nios2/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/riscv/cpu.c | 1 + target/rx/cpu.c | 1 + target/s390x/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + target/ppc/translate_init.c.inc | 1 + 23 files changed, 24 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d99d3c830dc..398696f0f2d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,7 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 -#include "hw/core/sysemu-cpu-ops.h" +/* see sysemu-cpu-ops.h */ +struct SysemuCPUOps; =20 /** * CPUClass: diff --git a/cpu.c b/cpu.c index 64e17537e21..29dafee581f 100644 --- a/cpu.c +++ b/cpu.c @@ -29,6 +29,7 @@ #ifdef CONFIG_USER_ONLY #include "qemu.h" #else +#include "hw/core/sysemu-cpu-ops.h" #include "exec/address-spaces.h" #endif #include "sysemu/tcg.h" diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 7a8487d468f..da7543be514 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -35,6 +35,7 @@ #include "trace/trace-root.h" #include "qemu/plugin.h" #include "sysemu/hw_accel.h" +#include "hw/core/sysemu-cpu-ops.h" =20 CPUState *cpu_by_arch_id(int64_t id) { diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index d9a51d9f647..f6b4bb14cc5 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -24,6 +24,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "hw/core/sysemu-cpu-ops.h" =20 =20 static void alpha_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6cd546213de..7fa22a6beba 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -35,6 +35,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #include "hw/boards.h" +#include "hw/core/sysemu-cpu-ops.h" #endif #include "sysemu/sysemu.h" #include "sysemu/tcg.h" diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 040d3526995..89de301fc2b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "cpu.h" #include "disas/dis-asm.h" +#include "hw/core/sysemu-cpu-ops.h" =20 static void avr_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 77f821f4d9a..ed944094cf3 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -26,6 +26,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "mmu.h" +#include "hw/core/sysemu-cpu-ops.h" =20 =20 static void cris_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 7de37aadd4d..304a975eddf 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -25,6 +25,7 @@ #include "qemu/module.h" #include "exec/exec-all.h" #include "fpu/softfloat.h" +#include "hw/core/sysemu-cpu-ops.h" =20 =20 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3519cef8fba..1e8ee015bfc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -60,6 +60,7 @@ #include "exec/address-spaces.h" #include "hw/i386/apic_internal.h" #include "hw/boards.h" +#include "hw/core/sysemu-cpu-ops.h" #endif =20 #include "disas/capstone.h" diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index eaf5f34d22c..96fe37e84f1 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "fpu/softfloat.h" +#include "hw/core/sysemu-cpu-ops.h" =20 static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index a21f15192ae..ad3996cd90e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "exec/exec-all.h" #include "fpu/softfloat-helpers.h" +#include "hw/core/sysemu-cpu-ops.h" =20 static const struct { const char *name; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 285564b4d5b..ab3b6a76b1a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -34,6 +34,7 @@ #include "hw/semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" +#include "hw/core/sysemu-cpu-ops.h" =20 #if !defined(CONFIG_USER_ONLY) =20 diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 47b8735bb75..9c450fc9a61 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "migration/vmstate.h" #include "machine.h" +#include "hw/core/sysemu-cpu-ops.h" =20 static void moxie_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e5cbf43d6ee..6e89d3a7abd 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -26,6 +26,7 @@ #include "exec/gdbstub.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" +#include "hw/core/sysemu-cpu-ops.h" =20 static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index c666e86e919..fceacf97203 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -21,6 +21,7 @@ #include "qapi/error.h" #include "qemu/qemu-print.h" #include "cpu.h" +#include "hw/core/sysemu-cpu-ops.h" =20 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eaf7c13e5a6..f24b033426d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -29,6 +29,7 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" +#include "hw/core/sysemu-cpu-ops.h" =20 /* RISC-V CPU definitions */ =20 diff --git a/target/rx/cpu.c b/target/rx/cpu.c index d1a7a5f6877..458553b8fba 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "hw/loader.h" #include "fpu/softfloat.h" +#include "hw/core/sysemu-cpu-ops.h" =20 static void rx_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 30117fc8cd7..511e9b2aa6f 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -42,6 +42,7 @@ #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" #include "sysemu/tcg.h" +#include "hw/core/sysemu-cpu-ops.h" #endif #include "fpu/softfloat-helpers.h" #include "disas/capstone.h" diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 843f39de41c..273bf3fbe8e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -26,6 +26,7 @@ #include "migration/vmstate.h" #include "exec/exec-all.h" #include "fpu/softfloat-helpers.h" +#include "hw/core/sysemu-cpu-ops.h" =20 static void superh_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index c8a115c886a..ce9cc6469a9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "hw/qdev-properties.h" #include "qapi/visitor.h" +#include "hw/core/sysemu-cpu-ops.h" =20 //#define DEBUG_FEATURES =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0c4b5021e79..4709854a0aa 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "qemu/error-report.h" #include "migration/vmstate.h" +#include "hw/core/sysemu-cpu-ops.h" =20 static inline void set_feature(CPUTriCoreState *env, int feature) { diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 44a4524bc0a..7e24cb3269f 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -34,6 +34,7 @@ #include "fpu/softfloat.h" #include "qemu/module.h" #include "migration/vmstate.h" +#include "hw/core/sysemu-cpu-ops.h" =20 =20 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index d38d194fe87..591fae52410 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -42,6 +42,7 @@ #include "disas/capstone.h" #include "fpu/softfloat.h" #include "qapi/qapi-commands-machine-target.h" +#include "hw/core/sysemu-cpu-ops.h" =20 /* #define PPC_DUMP_CPU */ /* #define PPC_DEBUG_SPR */ --=20 2.26.2