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[174.21.84.25]) by smtp.gmail.com with ESMTPSA id d24sm16257400pfn.54.2021.02.28.15.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Feb 2021 15:23:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5sMrPCvBvZcRNI0f+4NGvi10dnGYsatk73CQtS7iOqk=; b=XviND/LmawhHzDOwdpfeeRqtWUdkMKvIRPzJqSSovblGu50Vzhz4TCToSwuLGapPmj hazn1ycqqVY/3+WluzsgajCZKQuZLdIyXwXgNMiKR/mLZBWGngmEk58tp1iT5IXq4o/9 p3UPrpYkfZSmy2z8AUwWqpQkwWX1qBSdaG4gdQSImhIiqTTCC98zhx14cuLhO5W+F0jc 8lfLsWBzXFAsH/k7oyc866++pGl2/suRmkQ2dXItVyG4WNX9LeLw1OpIYScfdrZBlGGn 74scrtcPglEWHdUAFactSfw9+qVc2s4F188hxwf3jfcMUV2FdgqbzyBCB5Pv1XYzdjy2 6JDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5sMrPCvBvZcRNI0f+4NGvi10dnGYsatk73CQtS7iOqk=; b=baCzIsBxmVWJQUvxsW8nnz61W8v8b8vNyUT/Y4eDgVzuCUNZKKebvlADw3hysvWqKh shB6eB6Im3An3BBQiDFFSal3+EFm0ugNuOfgbbfPA0ofgKeiANeyvMnbUgB8AJmWax8V aUFqZyg3kpafCzi21DRNcFiqc05EcVsbYeBycvzo3Tci2Mx6QcIhG322I+KspWHvbw7F gpKMJ2U87KLKQm1W8Ba/rmx+/9MoMRPxolgCm6UeA6tPNye8gt830GfPH/Cq4+Tl81eO c7VSmajTAyl4TUGCwadu66L2gB4KLWNCDMj/gkj61BQZEfCTC65S9ZPZdCSSGWjhl8L9 kaUA== X-Gm-Message-State: AOAM532hRoAXA03BhThiX5WEjHBKvSc78BxVakynN5QYsfEG7PGYywOy z6uJoSKs44Gp/Xdbn1ek18W7fnCh5cnYrg== X-Google-Smtp-Source: ABdhPJyOFyVK+r2ER6kRssMHJT7b549YyQPrQd2qKlv4Mnau93dVnbZOnbOFJ70uPaSarCF/63dWJA== X-Received: by 2002:a17:903:248f:b029:de:c703:9839 with SMTP id p15-20020a170903248fb02900dec7039839mr13020757plw.42.1614554618432; Sun, 28 Feb 2021 15:23:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 17/50] target/i386: Move rex_r into DisasContext Date: Sun, 28 Feb 2021 15:22:48 -0800 Message-Id: <20210228232321.322053-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210228232321.322053-1-richard.henderson@linaro.org> References: <20210228232321.322053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cfontana@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Treat this flag exactly like we treat rex_b and rex_x. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 84 ++++++++++++++++++++----------------- 1 file changed, 45 insertions(+), 39 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 605b80229a..aa10d0ba99 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -92,6 +92,7 @@ typedef struct DisasContext { #endif =20 #ifdef TARGET_X86_64 + uint8_t rex_r; uint8_t rex_x; uint8_t rex_b; #endif @@ -166,10 +167,12 @@ typedef struct DisasContext { =20 #ifdef TARGET_X86_64 #define REX_PREFIX(S) (((S)->prefix & PREFIX_REX) !=3D 0) +#define REX_R(S) ((S)->rex_r + 0) #define REX_X(S) ((S)->rex_x + 0) #define REX_B(S) ((S)->rex_b + 0) #else #define REX_PREFIX(S) false +#define REX_R(S) 0 #define REX_X(S) 0 #define REX_B(S) 0 #endif @@ -3094,7 +3097,7 @@ static const struct SSEOpHelper_eppi sse_op_table7[25= 6] =3D { }; =20 static void gen_sse(CPUX86State *env, DisasContext *s, int b, - target_ulong pc_start, int rex_r) + target_ulong pc_start) { int b1, op1_offset, op2_offset, is_xmm, val; int modrm, mod, rm, reg; @@ -3164,8 +3167,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, =20 modrm =3D x86_ldub_code(env, s); reg =3D ((modrm >> 3) & 7); - if (is_xmm) - reg |=3D rex_r; + if (is_xmm) { + reg |=3D REX_R(s); + } mod =3D (modrm >> 6) & 3; if (sse_fn_epp =3D=3D SSE_SPECIAL) { b |=3D (b1 << 8); @@ -3699,7 +3703,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, tcg_gen_ld16u_tl(s->T0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(= val))); } - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); gen_op_mov_reg_v(s, ot, reg, s->T0); break; case 0x1d6: /* movq ea, xmm */ @@ -3743,7 +3747,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, offsetof(CPUX86State, fpregs[rm].mmx)); gen_helper_pmovmskb_mmx(s->tmp2_i32, cpu_env, s->ptr0); } - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); tcg_gen_extu_i32_tl(cpu_regs[reg], s->tmp2_i32); break; =20 @@ -3755,7 +3759,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, } modrm =3D x86_ldub_code(env, s); rm =3D modrm & 7; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; if (b1 >=3D 2) { goto unknown_op; @@ -3831,7 +3835,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, /* Various integer extensions at 0f 38 f[0-f]. */ b =3D modrm | (b1 << 8); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 switch (b) { case 0x3f0: /* crc32 Gd,Eb */ @@ -4185,7 +4189,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, b =3D modrm; modrm =3D x86_ldub_code(env, s); rm =3D modrm & 7; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; if (b1 >=3D 2) { goto unknown_op; @@ -4205,7 +4209,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, rm =3D (modrm & 7) | REX_B(s); if (mod !=3D 3) gen_lea_modrm(env, s, modrm); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); val =3D x86_ldub_code(env, s); switch (b) { case 0x14: /* pextrb */ @@ -4374,7 +4378,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, /* Various integer extensions at 0f 3a f[0-f]. */ b =3D modrm | (b1 << 8); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 switch (b) { case 0x3f0: /* rorx Gy,Ey, Ib */ @@ -4548,12 +4552,13 @@ static target_ulong disas_insn(DisasContext *s, CPU= State *cpu) MemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; - int rex_w, rex_r; + int rex_w; target_ulong pc_start =3D s->base.pc_next; =20 s->pc_start =3D s->pc =3D pc_start; s->override =3D -1; #ifdef TARGET_X86_64 + s->rex_r =3D 0; s->rex_x =3D 0; s->rex_b =3D 0; #endif @@ -4567,7 +4572,6 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) =20 prefixes =3D 0; rex_w =3D -1; - rex_r =3D 0; =20 next_byte: b =3D x86_ldub_code(env, s); @@ -4612,7 +4616,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) /* REX prefix */ prefixes |=3D PREFIX_REX; rex_w =3D (b >> 3) & 1; - rex_r =3D (b & 0x4) << 1; + s->rex_r =3D (b & 0x4) << 1; s->rex_x =3D (b & 0x2) << 2; s->rex_b =3D (b & 0x1) << 3; goto next_byte; @@ -4641,7 +4645,9 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) | PREFIX_LOCK | PREFIX_DATA | PREFIX_REX)) { goto illegal_op; } - rex_r =3D (~vex2 >> 4) & 8; +#ifdef TARGET_X86_64 + s->rex_r =3D (~vex2 >> 4) & 8; +#endif if (b =3D=3D 0xc5) { /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode = byte */ vex3 =3D vex2; @@ -4731,7 +4737,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) switch(f) { case 0: /* OP Ev, Gv */ modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); if (mod !=3D 3) { @@ -4753,7 +4759,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 1: /* OP Gv, Ev */ modrm =3D x86_ldub_code(env, s); mod =3D (modrm >> 6) & 3; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); rm =3D (modrm & 7) | REX_B(s); if (mod !=3D 3) { gen_lea_modrm(env, s, modrm); @@ -5173,7 +5179,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) ot =3D mo_b_d(b, dflag); =20 modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_v_reg(s, ot, s->T1, reg); @@ -5245,7 +5251,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x6b: ot =3D dflag; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (b =3D=3D 0x69) s->rip_offset =3D insn_const_size(ot); else if (b =3D=3D 0x6b) @@ -5297,7 +5303,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x1c1: /* xadd Ev, Gv */ ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; gen_op_mov_v_reg(s, ot, s->T0, reg); if (mod =3D=3D 3) { @@ -5329,7 +5335,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) =20 ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; oldv =3D tcg_temp_new(); newv =3D tcg_temp_new(); @@ -5551,7 +5557,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x89: /* mov Gv, Ev */ ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 /* generate a generic store */ gen_ldst_modrm(env, s, modrm, ot, reg, 1); @@ -5577,7 +5583,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x8b: /* mov Ev, Gv */ ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_reg_v(s, ot, reg, s->T0); @@ -5627,7 +5633,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) s_ot =3D b & 8 ? MO_SIGN | ot : ot; =20 modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); =20 @@ -5666,7 +5672,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) mod =3D (modrm >> 6) & 3; if (mod =3D=3D 3) goto illegal_op; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); { AddressParts a =3D gen_lea_modrm_0(env, s, modrm); TCGv ea =3D gen_lea_modrm_1(s, a); @@ -5748,7 +5754,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x87: /* xchg Ev, Gv */ ot =3D mo_b_d(b, dflag); modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; if (mod =3D=3D 3) { rm =3D (modrm & 7) | REX_B(s); @@ -5785,7 +5791,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) do_lxx: ot =3D dflag !=3D MO_16 ? MO_32 : MO_16; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; if (mod =3D=3D 3) goto illegal_op; @@ -5868,7 +5874,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) modrm =3D x86_ldub_code(env, s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (mod !=3D 3) { gen_lea_modrm(env, s, modrm); opreg =3D OR_TMP0; @@ -6722,7 +6728,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) } ot =3D dflag; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); gen_cmovcc1(env, s, ot, b, modrm, reg); break; =20 @@ -6868,7 +6874,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) do_btx: ot =3D dflag; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); gen_op_mov_v_reg(s, MO_32, s->T1, reg); @@ -6973,7 +6979,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x1bd: /* bsr / lzcnt */ ot =3D dflag; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_extu(ot, s->T0); =20 @@ -7700,7 +7706,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) d_ot =3D dflag; =20 modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); mod =3D (modrm >> 6) & 3; rm =3D (modrm & 7) | REX_B(s); =20 @@ -7774,7 +7780,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) goto illegal_op; ot =3D dflag !=3D MO_16 ? MO_32 : MO_16; modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); t0 =3D tcg_temp_local_new(); gen_update_cc_op(s); @@ -7815,7 +7821,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) modrm =3D x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod =3D (modrm >> 6) & 3; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (prefixes & PREFIX_REPZ) { /* bndcl */ if (reg >=3D 4 @@ -7905,7 +7911,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) modrm =3D x86_ldub_code(env, s); if (s->flags & HF_MPX_EN_MASK) { mod =3D (modrm >> 6) & 3; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (mod !=3D 3 && (prefixes & PREFIX_REPZ)) { /* bndmk */ if (reg >=3D 4 @@ -8017,7 +8023,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) * are assumed to be 1's, regardless of actual values. */ rm =3D (modrm & 7) | REX_B(s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (CODE64(s)) ot =3D MO_64; else @@ -8070,7 +8076,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) * are assumed to be 1's, regardless of actual values. */ rm =3D (modrm & 7) | REX_B(s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); if (CODE64(s)) ot =3D MO_64; else @@ -8112,7 +8118,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) mod =3D (modrm >> 6) & 3; if (mod =3D=3D 3) goto illegal_op; - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); /* generate a generic store */ gen_ldst_modrm(env, s, modrm, ot, reg, 1); break; @@ -8344,7 +8350,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) goto illegal_op; =20 modrm =3D x86_ldub_code(env, s); - reg =3D ((modrm >> 3) & 7) | rex_r; + reg =3D ((modrm >> 3) & 7) | REX_R(s); =20 if (s->prefix & PREFIX_DATA) { ot =3D MO_16; @@ -8372,7 +8378,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x1c2: case 0x1c4 ... 0x1c6: case 0x1d0 ... 0x1fe: - gen_sse(env, s, b, pc_start, rex_r); + gen_sse(env, s, b, pc_start); break; default: goto unknown_op; --=20 2.25.1