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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id b15sm14268366wmd.41.2021.02.26.08.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:32:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UQM81mur+9UHjxbQN0Zv4wGjBmPMsrfz+L5iL9ZySpM=; b=hS9C85/oo+y2Yc3FC6Hq/wW/6MOhCok3wlDBQ4fIK52mjwH2SNfsJdL9E4jDk6uF1u myIEPX+MIlA7yhaqncVRUft7WD5a2sGTSy4m7qD9w+Ru1ghouBPLbXMUkgjLKP9A/JwC f2yyUJC0cJrgj18U/TsJnGx54V7jPmV8qThIGZrRPXwNgvJn5RNqtobZfdSV18lKrNUv xxlbIfgP8O4+byfH+OTqYKKyhCRQUa40K3PfApfYwWiCfxVkVJlkR4gv6Q7BqxNSpGS3 bF0XQKAEs3JNuYdCPFU8mSNjtKCJd2Y3b9FtSnXhfVBQz9ANK1K8pWc8MUCUunQh2p7C BfjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UQM81mur+9UHjxbQN0Zv4wGjBmPMsrfz+L5iL9ZySpM=; b=LBe8YRLaQTLMZiX+Mrox0ascv6TZQNmVF4Nh7akcAKaBAFornynAOP7y2jXJp8xG+A 7RpO2kYbDSzEKW2UqRcOcauC3YZu1iYQQHp941NSem4rXp9OtIJ8UsHTbUqteTkYrKQS h3QXgwYYFOFkrpP5szOy0DL7yAjRqLSuquyXqwW7Kf8ta6VaMZjPVza++q7YqFdKn+ws NBUkY2ZGJA1WEgV2emrA/9guHitP837YjFl6pk97JZb+FWON2OEilIj7st9EFyB/3k1m ZgynRX/QN4cka3L30ttG57q+F/idhQ9rw7G0TQNEY+T3JX430vs95ZkWo4++VkCXug2+ +ETA== X-Gm-Message-State: AOAM5301EvkHWE+r4Ug1FmvgORnaRZP37wvGJSZMs9RcyN86Fkh8uaE2 Aawn3BjP3lTaVA+pj1n9O74= X-Google-Smtp-Source: ABdhPJzImIoHGIqzmSEscH67EA8q0vm8DYLiMAdRlkpSxbxE8lkYw/NVJptyGI7VkNaymQqhD75XBw== X-Received: by 2002:adf:e60e:: with SMTP id p14mr4034695wrm.221.1614357163853; Fri, 26 Feb 2021 08:32:43 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 02/16] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Date: Fri, 26 Feb 2021 17:32:13 +0100 Message-Id: <20210226163227.4097950-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 33 ++++----------------------------- hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c005d3dc2d8..2d43f78819f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -578,18 +578,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags); * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr ad= dr, - MemTxAttrs *attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); - } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); -} +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); =20 /** * cpu_get_phys_page_debug: @@ -601,12 +591,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPU= State *cpu, vaddr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) -{ - MemTxAttrs attrs =3D {}; - - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); -} +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 /** cpu_asidx_from_attrs: * @cpu: CPU @@ -615,17 +600,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState = *cpu, vaddr addr) * Returns the address space index specifying the CPU AddressSpace * to use for a memory access with the given transaction attributes. */ -static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - int ret =3D 0; - - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); - assert(ret < cpu->num_ases && ret >=3D 0); - } - return ret; -} +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 #endif /* CONFIG_USER_ONLY */ =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..4dce35f832f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu, error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_phys_page_attrs_debug) { + return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + } + /* Fallback for CPUs which don't implement the _attrs_ hook */ + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return cc->get_phys_page_debug(cpu, addr); +} + +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +{ + MemTxAttrs attrs =3D {}; + + return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); +} + +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + int ret =3D 0; + + if (cc->asidx_from_attrs) { + ret =3D cc->asidx_from_attrs(cpu, attrs); + assert(ret < cpu->num_ases && ret >=3D 0); + } + return ret; +} + /* Resetting the IRQ comes from across the code base so we take the * BQL here if we need to. cpu_interrupt assumes it is held.*/ void cpu_reset_interrupt(CPUState *cpu, int mask) --=20 2.26.2