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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id d29sm14123456wra.51.2021.02.26.08.32.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:32:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nOq5iyMcYnp2lkKz6qC+70BZoqGGdKahRqfZnxYC4Rc=; b=MIivNJ7e9XPkANOqJbGY5lKphhSSmVnEPU8TXNAme91nhvYlV5u1pKA33EglzJuvTV lj9BQrcNXtdW/XViGNOniAlJiuwJZZPyJdbD0twF5tWYxclU134oMsjarOc2MZ7OZg7L jxeCloPB3+5n3dbOVN12nwB8yFcBTCZds9U+9LCZFw/Nj+t3lMl/VQyFng5WfMFqwBYX 3mnea/cFnniO8tHvUuY0cSnbTPzxSThKJ1DoFZMsJxdPbt2w+fkUKKo+J5VDSvm3bKei RcCiBfLXGQKpWYGPMKVizJI+Hb9DkDLTeZuMl/evTmF0I5P4HnKhh6STDCVB2nQrh24K pVlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nOq5iyMcYnp2lkKz6qC+70BZoqGGdKahRqfZnxYC4Rc=; b=cDlFye5HO7gQ6SQUBgY1suSItLuRMdneyfU90IbgcSzsPL7YL7whE3kTCXf1uezSwS FiX1v6iV5VTuPA5n8Jz4Ymk5QuztuT3r5fpGC7FGdTCkDh046aYyf3BPBtjANnAVHwU5 TBDSmz+ImCpBjGblkK/Q5JaGM9czzQMzki8dg7AQH6kiw/nAVxrhdMWdYeAiVmfeebZx Q4nIk8PAiQEMnvbzdYkBGAMLoREbZ1b6FUKPheK5pr1C6Cq51dDD4ZHkCh6HsVbDttFd HlXOSVlrBsK2aprJzdsYxWAPHpTbCxcWpmVdnTFH00DUIavLwjcP817XGaF8flqVG3T1 b5Bg== X-Gm-Message-State: AOAM532J6a5xGHTrIZFc4IIwBiZV0jZnI/Yw2wnzFx8YcvUzPVS4Xsjw r0YC+QCXfqxuqlz6VNLY828= X-Google-Smtp-Source: ABdhPJw1ssbsvOTtNWYtOVhhF1Q3Lrudc5JKlRWS1P8CFhiboT0XSXm+MjaaX+AdJ3khfagJ6zKOeA== X-Received: by 2002:a7b:c10c:: with SMTP id w12mr705868wmi.112.1614357157921; Fri, 26 Feb 2021 08:32:37 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 01/16] target: Set CPUClass::vmsd instead of DeviceClass::vmsd Date: Fri, 26 Feb 2021 17:32:12 +0100 Message-Id: <20210226163227.4097950-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The cpu model is the single device available in user-mode. Since we want to restrict some fields to user-mode emulation, we prefer to set the vmsd field of CPUClass, rather than the DeviceClass one. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27192b62e22..faabffe0796 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -237,7 +237,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_alpha_cpu; + cc->vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed983380fca..29a865b75d2 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -293,7 +293,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_cris_cpu; + cc->vmsd =3D &vmstate_cris_cpu; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d8fad52d1fe..4f142de6e45 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -162,7 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_hppa_cpu; + cc->vmsd =3D &vmstate_hppa_cpu; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 37d2ed9dc79..c98fb1e33be 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -533,7 +533,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_m68k_cpu; + cc->vmsd =3D &vmstate_m68k_cpu; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 433ba202037..335dfdc734e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -387,7 +387,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; - dc->vmsd =3D &vmstate_mb_cpu; + cc->vmsd =3D &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46b..79d246d1930 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -204,7 +204,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_openrisc_cpu; + cc->vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ac65c88f1f8..bd44de53729 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,7 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->gdb_num_core_regs =3D 59; =20 - dc->vmsd =3D &vmstate_sh_cpu; + cc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 0258884f845..12894ffac6a 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -146,7 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_uc32_cpu; + cc->vmsd =3D &vmstate_uc32_cpu; cc->tcg_ops =3D &uc32_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e2b2c7a71c1..6bedd5b97b8 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -218,7 +218,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - dc->vmsd =3D &vmstate_xtensa_cpu; + cc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 --=20 2.26.2