From nobody Wed Nov 19 04:35:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357237; cv=none; d=zohomail.com; s=zohoarc; b=JT/6TDenKEU5Zpzi56OUhJXzQIA7boG4kfvytAjCm1/pVNcGpVZKwEqHK+mW9zYIB2vJvn0R+8I0D/v2rIoWp5I9a5thiVeNWwZDCJGBljP2c3d/Ndef0pCVA7UnHjglsAMJtm2a6oGwGRkW99bJexi9OX9vlm+PG15JwbLd5mY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357237; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gQ4YHlwNbSL25AZUo/xOoa8axE7iYMW7r02UBMH2a6M=; b=O/MeABGCIGCqc2lSfp5QpChc5WnFSH6pht0WcdHi9EXusV63KVOc6DGutX9W+ZYyt9EBbZ6NFzIfuK30sfUNnp/5ivDZdNEn4R4/YNcCEea6VL9GFoEJF/3P0Dz59SlmfA5mQhmTLHe09KVSD4kpKgI3SkR2T7U0CfIusoKfOQA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1614357237889314.8508170534818; Fri, 26 Feb 2021 08:33:57 -0800 (PST) Received: by mail-wr1-f49.google.com with SMTP id r3so9147571wro.9 for ; Fri, 26 Feb 2021 08:33:56 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id a14sm15954469wrg.84.2021.02.26.08.33.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:33:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gQ4YHlwNbSL25AZUo/xOoa8axE7iYMW7r02UBMH2a6M=; b=DkI5fKT3UPEsAUYxLuKMv3jzzcXgExFTLX6nF4QIqTkXbaKOFW5+KNOfqxec7JfznW 0fwTVjOGyr/dKGHpEZiay1mHgBKHBWrU4ESfMf8SYVWsMcED9hEXdH++r29oKRYC91c/ 6PK21j6JtF6tUvG9P1HXSisnADjG7kLZEg4tSbNUSuhWuqwsgI0YrZUgVEAYSMqVN2zv bD8S5d8BnsJmxORm6SeRCdROGKxOQRi6HJ3M1KBjfGgcHm/2NyEFrqGlF8adb9Bjxa4t 9q+8JMuNrr0SmKCZ7PExWoVDftG0sAB6L0eIzcny0iUmKrR2IxzoNfd27oaO5iO7rwSI k7sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gQ4YHlwNbSL25AZUo/xOoa8axE7iYMW7r02UBMH2a6M=; b=l1QkY8L80/QsZPL5SKlfIQp+WRspjEIkzfMsSfwEkdliwkXMOHZK2clbF6ngBvhLwn F7VNCCVqf7oe6rkN84nAnivOgSySzkBZYyn7EBkVF3vz4rZ/asV7I6xJdDpIb+Yx1poD 1bSsa7BYbjEJUkWLsugooSxaBD2pBF6Y7pt3VAGH94msp6mKzOZax9MWA89X3+NcH0RY kIL93tEopCo9i8qga5S2YLOAqERF8+xRpcq8mGwMn1MJWQFipOsU9bVytxsCI6UyWxYM aw24dZfyfcsH3SBI7YOip533gne8pOd+pqCHV8KDaozK5uz4TOBn8gii6RBRbKuEFFSJ Eexw== X-Gm-Message-State: AOAM5330N3n6XT94eDrYkrzTpnY90gJT5uqCFTI+A7Qvd41FzYDXlNCj xDx8OZ8OAkZumpwKOZh2cbc= X-Google-Smtp-Source: ABdhPJx1Mzhs4AoKmJtCNTryhP1c2cJTsmBcpFJwcPJsWyebPgg0DRG2DcDjr5ApFn+jJkWWBZgJzw== X-Received: by 2002:adf:d1ce:: with SMTP id b14mr4089240wrd.126.1614357234852; Fri, 26 Feb 2021 08:33:54 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 13/16] cpu: Move CPUClass::get_phys_page_debug to CPUSystemOperations Date: Fri, 26 Feb 2021 17:32:24 +0100 Message-Id: <20210226163227.4097950-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 21 +++++++++++++-------- hw/core/cpu.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 24 files changed, 38 insertions(+), 33 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fc3c4c217b1..5bc66653c19 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -84,6 +84,19 @@ struct AccelCPUClass; * struct CPUSystemOperations: System operations specific to a CPU class */ typedef struct CPUSystemOperations { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * and the associated memory transaction attributes to use for t= he + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. @@ -153,11 +166,6 @@ typedef struct CPUSystemOperations { * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -196,9 +204,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index d38eda36bc3..f0c558c002e 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cc->system_ops.get_phys_page_attrs_debug) { + return cc->system_ops.get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); + return cc->system_ops.get_phys_page_debug(cpu, addr); } =20 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ee65971da8e..b430771b7c8 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -236,7 +236,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 86af15b0625..87a581fa47c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2297,7 +2297,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; + cc->system_ops.get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_att= rs_debug; cc->system_ops.asidx_from_attrs =3D arm_asidx_from_attrs; cc->system_ops.vmsd =3D &vmstate_arm_cpu; cc->system_ops.virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0e55d5f4838..d532a579c1b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -212,7 +212,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; - cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D avr_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c0392c7def3..6434f170387 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -292,7 +292,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D cris_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_cris_cpu; #endif =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 58c09824fff..cc72a6ea1ce 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -161,7 +161,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_hppa_cpu; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 36b34eee62f..f6f5c333b7e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7420,7 +7420,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) #ifndef CONFIG_USER_ONLY cc->system_ops.asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; + cc->system_ops.get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_att= rs_debug; cc->system_ops.get_crash_info =3D x86_cpu_get_crash_info; cc->system_ops.write_elf64_note =3D x86_cpu_write_elf64_note; cc->system_ops.write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index bc5f448584c..515728b7f5d 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -240,7 +240,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_lm32_cpu; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 30cf308633f..63c45e98e97 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -532,7 +532,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) - cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_m68k_cpu; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 17670bbfb59..73e99d2d9be 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -386,7 +386,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; + cc->system_ops.get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attr= s_debug; cc->system_ops.vmsd =3D &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 3389b879087..b95856e3137 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -719,7 +719,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_mips_cpu; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 953a440576f..8512bc50715 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -121,7 +121,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a389..615aed9729f 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -237,7 +237,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index c127bcc0680..02397842757 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -203,7 +203,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D openrisc_cpu_get_phys_page_debu= g; cc->system_ops.vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 70651c9b721..7abf7685184 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -621,7 +621,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->system_ops.vmsd =3D &vmstate_riscv_cpu; #endif diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26b..1191c686637 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,7 +204,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) =20 cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; - cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index dcfbb7832e1..11acf9b5727 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -516,7 +516,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_s390_cpu; cc->system_ops.get_crash_info =3D s390_cpu_get_crash_info; cc->system_ops.write_elf64_note =3D s390_cpu_write_elf64_note; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 706ef971c3d..533e02bd3d9 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -256,7 +256,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index f14a26c154a..46d3e0ec668 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -888,7 +888,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_sparc_cpu; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcba..c9ae4249fc1 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -170,7 +170,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->tcg_ops =3D &tricore_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 277b41194fb..eb4eec341a1 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -145,7 +145,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D uc32_cpu_has_work; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_uc32_cpu; cc->tcg_ops =3D &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 80f12ebf995..befcb004d6f 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -215,7 +215,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; cc->system_ops.vmsd =3D &vmstate_xtensa_cpu; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index b1ac3291be1..82438c5c72b 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10884,7 +10884,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_ppc_cpu; #endif #if defined(CONFIG_SOFTMMU) --=20 2.26.2