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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id d29sm14123456wra.51.2021.02.26.08.32.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:32:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nOq5iyMcYnp2lkKz6qC+70BZoqGGdKahRqfZnxYC4Rc=; b=MIivNJ7e9XPkANOqJbGY5lKphhSSmVnEPU8TXNAme91nhvYlV5u1pKA33EglzJuvTV lj9BQrcNXtdW/XViGNOniAlJiuwJZZPyJdbD0twF5tWYxclU134oMsjarOc2MZ7OZg7L jxeCloPB3+5n3dbOVN12nwB8yFcBTCZds9U+9LCZFw/Nj+t3lMl/VQyFng5WfMFqwBYX 3mnea/cFnniO8tHvUuY0cSnbTPzxSThKJ1DoFZMsJxdPbt2w+fkUKKo+J5VDSvm3bKei RcCiBfLXGQKpWYGPMKVizJI+Hb9DkDLTeZuMl/evTmF0I5P4HnKhh6STDCVB2nQrh24K pVlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nOq5iyMcYnp2lkKz6qC+70BZoqGGdKahRqfZnxYC4Rc=; b=cDlFye5HO7gQ6SQUBgY1suSItLuRMdneyfU90IbgcSzsPL7YL7whE3kTCXf1uezSwS FiX1v6iV5VTuPA5n8Jz4Ymk5QuztuT3r5fpGC7FGdTCkDh046aYyf3BPBtjANnAVHwU5 TBDSmz+ImCpBjGblkK/Q5JaGM9czzQMzki8dg7AQH6kiw/nAVxrhdMWdYeAiVmfeebZx Q4nIk8PAiQEMnvbzdYkBGAMLoREbZ1b6FUKPheK5pr1C6Cq51dDD4ZHkCh6HsVbDttFd HlXOSVlrBsK2aprJzdsYxWAPHpTbCxcWpmVdnTFH00DUIavLwjcP817XGaF8flqVG3T1 b5Bg== X-Gm-Message-State: AOAM532J6a5xGHTrIZFc4IIwBiZV0jZnI/Yw2wnzFx8YcvUzPVS4Xsjw r0YC+QCXfqxuqlz6VNLY828= X-Google-Smtp-Source: ABdhPJw1ssbsvOTtNWYtOVhhF1Q3Lrudc5JKlRWS1P8CFhiboT0XSXm+MjaaX+AdJ3khfagJ6zKOeA== X-Received: by 2002:a7b:c10c:: with SMTP id w12mr705868wmi.112.1614357157921; Fri, 26 Feb 2021 08:32:37 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 01/16] target: Set CPUClass::vmsd instead of DeviceClass::vmsd Date: Fri, 26 Feb 2021 17:32:12 +0100 Message-Id: <20210226163227.4097950-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The cpu model is the single device available in user-mode. Since we want to restrict some fields to user-mode emulation, we prefer to set the vmsd field of CPUClass, rather than the DeviceClass one. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27192b62e22..faabffe0796 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -237,7 +237,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_alpha_cpu; + cc->vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed983380fca..29a865b75d2 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -293,7 +293,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_cris_cpu; + cc->vmsd =3D &vmstate_cris_cpu; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d8fad52d1fe..4f142de6e45 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -162,7 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_hppa_cpu; + cc->vmsd =3D &vmstate_hppa_cpu; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 37d2ed9dc79..c98fb1e33be 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -533,7 +533,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_m68k_cpu; + cc->vmsd =3D &vmstate_m68k_cpu; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 433ba202037..335dfdc734e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -387,7 +387,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; - dc->vmsd =3D &vmstate_mb_cpu; + cc->vmsd =3D &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46b..79d246d1930 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -204,7 +204,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_openrisc_cpu; + cc->vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ac65c88f1f8..bd44de53729 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,7 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->gdb_num_core_regs =3D 59; =20 - dc->vmsd =3D &vmstate_sh_cpu; + cc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 0258884f845..12894ffac6a 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -146,7 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - dc->vmsd =3D &vmstate_uc32_cpu; + cc->vmsd =3D &vmstate_uc32_cpu; cc->tcg_ops =3D &uc32_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e2b2c7a71c1..6bedd5b97b8 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -218,7 +218,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - dc->vmsd =3D &vmstate_xtensa_cpu; + cc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357165; cv=none; d=zohomail.com; s=zohoarc; b=SrRUrz3wMmKNo8nvgU/B6X4nlSv0cOpYB+jweDPcmNyUVTmtl8sEZeP0WZCanBEh/LbP7d+ka0/5Tq22ZsSj3BKc4jCCCefooenojc8jv1iNRNRbB/fy4QiiXTi6AjpNQg8NWAVHVJENMt2D+mbEhuomJBLGVCeqBtlw2AuMTu8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357165; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id b15sm14268366wmd.41.2021.02.26.08.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:32:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UQM81mur+9UHjxbQN0Zv4wGjBmPMsrfz+L5iL9ZySpM=; b=hS9C85/oo+y2Yc3FC6Hq/wW/6MOhCok3wlDBQ4fIK52mjwH2SNfsJdL9E4jDk6uF1u myIEPX+MIlA7yhaqncVRUft7WD5a2sGTSy4m7qD9w+Ru1ghouBPLbXMUkgjLKP9A/JwC f2yyUJC0cJrgj18U/TsJnGx54V7jPmV8qThIGZrRPXwNgvJn5RNqtobZfdSV18lKrNUv xxlbIfgP8O4+byfH+OTqYKKyhCRQUa40K3PfApfYwWiCfxVkVJlkR4gv6Q7BqxNSpGS3 bF0XQKAEs3JNuYdCPFU8mSNjtKCJd2Y3b9FtSnXhfVBQz9ANK1K8pWc8MUCUunQh2p7C BfjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UQM81mur+9UHjxbQN0Zv4wGjBmPMsrfz+L5iL9ZySpM=; b=LBe8YRLaQTLMZiX+Mrox0ascv6TZQNmVF4Nh7akcAKaBAFornynAOP7y2jXJp8xG+A 7RpO2kYbDSzEKW2UqRcOcauC3YZu1iYQQHp941NSem4rXp9OtIJ8UsHTbUqteTkYrKQS h3QXgwYYFOFkrpP5szOy0DL7yAjRqLSuquyXqwW7Kf8ta6VaMZjPVza++q7YqFdKn+ws NBUkY2ZGJA1WEgV2emrA/9guHitP837YjFl6pk97JZb+FWON2OEilIj7st9EFyB/3k1m ZgynRX/QN4cka3L30ttG57q+F/idhQ9rw7G0TQNEY+T3JX430vs95ZkWo4++VkCXug2+ +ETA== X-Gm-Message-State: AOAM5301EvkHWE+r4Ug1FmvgORnaRZP37wvGJSZMs9RcyN86Fkh8uaE2 Aawn3BjP3lTaVA+pj1n9O74= X-Google-Smtp-Source: ABdhPJzImIoHGIqzmSEscH67EA8q0vm8DYLiMAdRlkpSxbxE8lkYw/NVJptyGI7VkNaymQqhD75XBw== X-Received: by 2002:adf:e60e:: with SMTP id p14mr4034695wrm.221.1614357163853; Fri, 26 Feb 2021 08:32:43 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 02/16] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Date: Fri, 26 Feb 2021 17:32:13 +0100 Message-Id: <20210226163227.4097950-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 33 ++++----------------------------- hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c005d3dc2d8..2d43f78819f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -578,18 +578,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags); * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr ad= dr, - MemTxAttrs *attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); - } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); -} +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); =20 /** * cpu_get_phys_page_debug: @@ -601,12 +591,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPU= State *cpu, vaddr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) -{ - MemTxAttrs attrs =3D {}; - - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); -} +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 /** cpu_asidx_from_attrs: * @cpu: CPU @@ -615,17 +600,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState = *cpu, vaddr addr) * Returns the address space index specifying the CPU AddressSpace * to use for a memory access with the given transaction attributes. */ -static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - int ret =3D 0; - - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); - assert(ret < cpu->num_ases && ret >=3D 0); - } - return ret; -} +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 #endif /* CONFIG_USER_ONLY */ =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..4dce35f832f 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu, error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_phys_page_attrs_debug) { + return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + } + /* Fallback for CPUs which don't implement the _attrs_ hook */ + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return cc->get_phys_page_debug(cpu, addr); +} + +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +{ + MemTxAttrs attrs =3D {}; + + return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); +} + +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + int ret =3D 0; + + if (cc->asidx_from_attrs) { + ret =3D cc->asidx_from_attrs(cpu, attrs); + assert(ret < cpu->num_ases && ret >=3D 0); + } + return ret; +} + /* Resetting the IRQ comes from across the code base so we take the * BQL here if we need to. cpu_interrupt assumes it is held.*/ void cpu_reset_interrupt(CPUState *cpu, int mask) --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id k15sm16661875wrn.0.2021.02.26.08.32.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:32:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=alNnX6GeE8sTwFbIWBvN2VrnGh2+v4nR5yjKLFDEoAw=; b=uyLMHlRDhmj2W3V3ce9VzgPU9r6OpFofbOSN9lX/cs7+Tmdo/xSLuzIAUfNU0EMI4I 23Ze1PKYwLOkQn7eEaZgrTKXetGQprjQrfqOu6co1hwfi1og/IyqrUDIt5QvCk9DdvKT mYhhjzPXto23Dhqs5Pukg9PsRMu4WhzkzF4hjTxLplbu2kkKYTnwOsxCjM4Rpv4NgEOy /mB+EUK2gj5Au/d/Mwuk4AsG0Lj7LlfkFMvmpBcS0eeiCMebZw5VDoDr1F6bdEbKS1Ro 4KOSfzmq2Qi9TvR563kHISpz3tA3QNMs7n0pCw1IcDTwRxE7F9aHdgkpRQt+52QKAyCU w3mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=alNnX6GeE8sTwFbIWBvN2VrnGh2+v4nR5yjKLFDEoAw=; b=G6YxcHXX2US+k4YEhtEx/nURnzzdxgjYZdVXhx1qoltjrtqIM98hsKjClii3Bvy/uh UlsnK1moQ4mPbLHEr7ttbTs03F5X7emmW4CAiJqlU7g7I8taKkm4kHv1s4WcAAeLB8CN yFH4zT3ScIPPTqDklQiVUgAAjxfNFZg+5A61HJQYGRPR55P9hTaBk/oPi1oDLF29W6Iv XeWe5AWbeWx1nHE22qvtmZkElJZsMfTRo5kTCI+qa2DuERd/23AWvqNae2PVB36eZtfu 4/UIYo9KHeJAm2RBhmHB6vGVt5ONpyzPfEYD5AelrFJTz2TAI9STVWJ7G97N0E42Gecp xIEg== X-Gm-Message-State: AOAM531UnbSOmc8iECSLpbhjGlT9xomRrKAyTgowveizCMpkpVMbeiZM +Qt94zr7MZsm+D75Yw6mnyI= X-Google-Smtp-Source: ABdhPJzDkN6tyMjmW6kiH+JF3nWHZrnzVfI10cUhsz+my/NvSxcjCUQIcnL4ukyU+tijzW/+2XMUqA== X-Received: by 2002:a5d:6ca6:: with SMTP id a6mr1465183wra.179.1614357169623; Fri, 26 Feb 2021 08:32:49 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 03/16] cpu: Introduce cpu_virtio_is_big_endian() Date: Fri, 26 Feb 2021 17:32:14 +0100 Message-Id: <20210226163227.4097950-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the cpu_virtio_is_big_endian() generic helper to avoid calling CPUClass internal virtio_is_big_endian() one. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 9 +++++++++ hw/core/cpu.c | 8 ++++++-- hw/virtio/virtio.c | 4 +--- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2d43f78819f..b12028c3c03 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr ad= dr); */ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 +/** + * cpu_virtio_is_big_endian: + * @cpu: CPU + + * Returns %true if a CPU which supports runtime configurable endianness + * is currently big-endian. + */ +bool cpu_virtio_is_big_endian(CPUState *cpu); + #endif /* CONFIG_USER_ONLY */ =20 /** diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 4dce35f832f..daaff56a79e 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu= , uint8_t *buf, int reg) return 0; } =20 -static bool cpu_common_virtio_is_big_endian(CPUState *cpu) +bool cpu_virtio_is_big_endian(CPUState *cpu) { + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->virtio_is_big_endian) { + return cc->virtio_is_big_endian(cpu); + } return target_words_bigendian(); } =20 @@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; - k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 1fd1917ca0f..fe6a4be99e4 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endia= n(void) =20 static enum virtio_device_endian virtio_current_cpu_endian(void) { - CPUClass *cc =3D CPU_GET_CLASS(current_cpu); - - if (cc->virtio_is_big_endian(current_cpu)) { + if (cpu_virtio_is_big_endian(current_cpu)) { return VIRTIO_DEVICE_ENDIAN_BIG; } else { return VIRTIO_DEVICE_ENDIAN_LITTLE; --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357177; cv=none; d=zohomail.com; s=zohoarc; b=fgfFs36r8DXRMi/W64rhhegC56Rr9IGUfRVNtvXcgwe1QDJCvxdlyKntBVyHmhNfWC3wvEk7IOjblgpjeiwf/UTa3WT9qtACfhWFVuvIXPPVXpUiJz1p+PX+9EysJjf/eN6GMy/nF2fjYMbYT+TYUc0YBBhqaTq3C5n1YFgUPFA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357177; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VJm0iGgu/pocJ2Vudv8ibS2Ot9Xd+ih0+p5aBEZz7PY=; b=aaox/yE+8XdjK0xH30KX6+s2Ri0xkaSOIN0cZoa+9NvSzrWbN0wNTghLMfKOc37Qre2Tvm0XAPBkhwVI93HpCQ/yKV4/KQAPGtIl5CTGZvHyRnOzk0HjIbhJE+NDrwciTdUWEFt7ZuE3avgmeQiDQzwzhDGz7Si0Cs5xHujJV74= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1614357177344184.09403706297348; Fri, 26 Feb 2021 08:32:57 -0800 (PST) Received: by mail-wm1-f50.google.com with SMTP id g11so4165476wmh.1 for ; Fri, 26 Feb 2021 08:32:56 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id c12sm14340059wru.71.2021.02.26.08.32.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:32:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VJm0iGgu/pocJ2Vudv8ibS2Ot9Xd+ih0+p5aBEZz7PY=; b=AvV3HzGz6b/FxsITj4P+nmJUJQc0hWFWajeyGY2576inTmfr58Uxlen0K113mri4FX 1JeATUrLlt7rlomIPZwF54l28sA5yY/kPnDRpdiSVVhRwRxPKJe5bIMLGSh8UDbTIWqw XAdg0NCQYabBASrsNCznKn16XIRBa39OwiRmnrGXJ0gzkS5BSH1Cdjnt0CGa3XG5TwRf ABNtaOmo1H6pQLT7bVepiBCitq56o8CHATraAUjItnqzibrjHNcOR/NW4U9ppMrjodlW i5wx45gaYlN3fy2IvMvDRR7DkkaM3wOOkB5PSVoxJFNcEWPyEd4mhygPjJ57IBZhzW7Q I0JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VJm0iGgu/pocJ2Vudv8ibS2Ot9Xd+ih0+p5aBEZz7PY=; b=GgUlUz5xJmRH3RswDYBAu92AdKkO8bIDeF9ycGyExdTy7Pnmu38lYc0CoDMhojIDtD ChDNExxszDyyq1NvdaDlW9iMdljbC77prdcarMZz0+PD+YBBPxGneJjVTwFMXoKVB37t sJoslJPKtQzyXrtb3w77LhELpraGcnsswgWyiM3Brb5QcwbERbRVwBw5q5ys3abKhsdk oFl9PPTpbdj1mTS8hWQ+3bsLOl1vPPhrgH6XPYy+yZ4yvhSzeelR6nMQtcLTPuH5XA7j RTvulpyJS3bGGG7gpWMLgIyW+2Me0T9n6+G9bBIsECUuvKiTzxO9uiX1jISw2speO4e6 5GZw== X-Gm-Message-State: AOAM531SMlIdM9TrPCEx3z4YiKRXZGqa10uzuVKlohhlj3JKBxDdYcfx GcYoZl6vAXGqmZGnNqumUV8= X-Google-Smtp-Source: ABdhPJy2diKC+uzbdNrnj6CbxvZ0e04xhEmDFH5D/f0q/qJQc22GX1GxaoChg+LID1dCZnOMcBehSw== X-Received: by 2002:a7b:c010:: with SMTP id c16mr3757539wmb.46.1614357175503; Fri, 26 Feb 2021 08:32:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 04/16] cpu: Directly use cpu_write_elf*() fallback handlers in place Date: Fri, 26 Feb 2021 17:32:15 +0100 Message-Id: <20210226163227.4097950-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code directly accesses CPUClass::write_elf*() handlers out of hw/core/cpu.c (the rest are assignation in target/ code): $ git grep -F -- '->write_elf' hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque); hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque); hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:440: k->write_elf32_qemunote =3D cpu_common_write_elf32_= qemunote; hw/core/cpu.c:441: k->write_elf32_note =3D cpu_common_write_elf32_note; hw/core/cpu.c:442: k->write_elf64_qemunote =3D cpu_common_write_elf64_= qemunote; hw/core/cpu.c:443: k->write_elf64_note =3D cpu_common_write_elf64_note; target/arm/cpu.c:2304: cc->write_elf64_note =3D arm_cpu_write_elf64_no= te; target/arm/cpu.c:2305: cc->write_elf32_note =3D arm_cpu_write_elf32_no= te; target/i386/cpu.c:7425: cc->write_elf64_note =3D x86_cpu_write_elf64_n= ote; target/i386/cpu.c:7426: cc->write_elf64_qemunote =3D x86_cpu_write_elf= 64_qemunote; target/i386/cpu.c:7427: cc->write_elf32_note =3D x86_cpu_write_elf32_n= ote; target/i386/cpu.c:7428: cc->write_elf32_qemunote =3D x86_cpu_write_elf= 32_qemunote; target/ppc/translate_init.c.inc:10891: cc->write_elf64_note =3D ppc64_= cpu_write_elf64_note; target/ppc/translate_init.c.inc:10892: cc->write_elf32_note =3D ppc32_= cpu_write_elf32_note; target/s390x/cpu.c:522: cc->write_elf64_note =3D s390_cpu_write_elf64_= note; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 43 ++++++++++++------------------------------- 1 file changed, 12 insertions(+), 31 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index daaff56a79e..a9ee2c74ec5 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_qemunote) { + return 0; + } return (*cc->write_elf32_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf32_note) { + return -1; + } return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_qemunote) { + return 0; + } return (*cc->write_elf64_qemunote)(f, cpu, opaque); } =20 -static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 + if (!cc->write_elf64_note) { + return -1; + } return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); } =20 -static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - - static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) { return 0; @@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *d= ata) k->has_work =3D cpu_common_has_work; k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; - k->write_elf32_qemunote =3D cpu_common_write_elf32_qemunote; - k->write_elf32_note =3D cpu_common_write_elf32_note; - k->write_elf64_qemunote =3D cpu_common_write_elf64_qemunote; - k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614357183; cv=none; d=zohomail.com; s=zohoarc; b=YfdGUyvas9sApeyxrpCYUbYssvZs5VW5v48KFLxDNe1GWvd3aXt/pMV9O5Qou0DnKJQnR2JR3xE0iAn3Wkbpt54Dd7wr405qXYZkHymnuU2xQkQKOZN9vb8NwgKfsrUrMrwFXPDPDIgDPQr5dQVPP2hM7Dzmav4Rg5VgfDb5gng= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357183; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yI5v3ChjpgUoMVznW3/vQVCaXLpm+f+cFTMRG3SQklk=; b=BNBJs0ZPnKHkhyoyTuKzowhuVpTsgLKpDL4s/FqX8qWKbP3QNuBLE7rb7SEVnHd2Qn36W8ng/TtVROc75YyN2L2k5SeLeB8PrQSbL4AnsYETjq/jaOBnF956wfMjw397NhkSC6J1ntOQGhX6hYFDCXyXubHvodgHxfZ7B06ol2E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1614357183178584.2859023745584; Fri, 26 Feb 2021 08:33:03 -0800 (PST) Received: by mail-wm1-f43.google.com with SMTP id u11so2188835wmq.5 for ; Fri, 26 Feb 2021 08:33:02 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id c128sm12749844wma.37.2021.02.26.08.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:33:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yI5v3ChjpgUoMVznW3/vQVCaXLpm+f+cFTMRG3SQklk=; b=BRX2O+8rPgMmAhoMuArR6BGQp9RPtIMCCDWft0DsYREYvSmofpcL+CWu+E2K4+ANba +i6L5uoXgpMwGS7GPuSGa4hku2StEpsEN8VWJL/8Og6ToJOkY7W3PFk9yJuSnDCSH4E0 tq2cKQc3VI1yNDxWQCJriUXuc1hXwJrhqfz+L92ql4JTkOvatwZnvpNGIGNlhV2xETp7 93eMcnE5X3/X0JmbORZETZCLIv+JRGLK9nVaeqAoFhmZqtMUdXj7t4h9NVIJuSN8+Ohd /Xuqu8hAHm2q914h2DjZvk/4ksJt7YvvCDCu9MMzebWMhWlxmC8Wbg5EZ5rLm2RZfJU1 rbGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yI5v3ChjpgUoMVznW3/vQVCaXLpm+f+cFTMRG3SQklk=; b=cfksPFrS0AAcbsgLHqphWL5rlyZsBoB2wZwQaH/IYJQNxkvy9OwCWhoaGcbu1TIyOg cealS1gKTDtKmnIjZaGDBSpKJVdUoaEjuDzcs5cagkXXDn+C+wWKeLZal+wPjv4BQ8jj imBX3NzlP3KFEqOAHUdDE1u4sOL1uF6PigE7zSz4NbtGWPpiRvWA6hXjJXUcSJxiNddW Hc/uPCF+6iiAc7kFUj7GNaoyAD0zerDRvj6R4VJ0NKxiZR5tG2568aoIXAls715w/0Hb qbOiq+8i1XQoev5B9Ocv1SUFn/7VffTttKRk9NMnFZolLEJOTRPp8KJFGi1Wbnu6asHd gEMQ== X-Gm-Message-State: AOAM530Bs0EntAOoRcJCPjXBr356R2v0V8zOwVZG7yUUTaQQe9Zfh54W Z46FdF4EKPQZJvSaHGsZP50= X-Google-Smtp-Source: ABdhPJwCBhB2ciT+Du95bx+5RDuSosOJPrCa8N0jHOr+l+XBkasB6CnQVnlRXwMsyaCwStcBFRU3Xg== X-Received: by 2002:a7b:c4d5:: with SMTP id g21mr3644774wmk.161.1614357181284; Fri, 26 Feb 2021 08:33:01 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 05/16] cpu: Directly use get_paging_enabled() fallback handlers in place Date: Fri, 26 Feb 2021 17:32:16 +0100 Message-Id: <20210226163227.4097950-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c: $ git grep -F -- '->get_paging_enabled' hw/core/cpu.c:74: return cc->get_paging_enabled(cpu); hw/core/cpu.c:438: k->get_paging_enabled =3D cpu_common_get_paging_ena= bled; target/i386/cpu.c:7418: cc->get_paging_enabled =3D x86_cpu_get_paging_= enabled; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index a9ee2c74ec5..1de00bbb474 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - return cc->get_paging_enabled(cpu); -} + if (cc->get_paging_enabled) { + return cc->get_paging_enabled(cpu); + } =20 -static bool cpu_common_get_paging_enabled(const CPUState *cpu) -{ return false; } =20 @@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357189; cv=none; d=zohomail.com; s=zohoarc; b=dIygfmbuhS/BHOtSafp4lyKGo95F9lgsTlj2dJi5YOtMog0UbMKYvZmB+lqf1gCIH3NdHs+w/AkiZhr+6ZUcRE25oDUidKswB7lJSkKTsTGFhaPHi9wdNkboQsqxnFS+8kGFd6K82hLVfJFLsc1AtXKUKZvPjVsvxaxBBTMbU0M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357189; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iDkHmNWDJUjsisDNEA+tDXF79jqbgWv+Yeaa+F2Cdm4=; b=ngSZwEg/L4yIxoTSmWWBopA7BHWJsIt7ezsyzNcyA9pAtehSVY5BrXOK3bpCLniOsaJQGTWwDm009vN12lMor6lXmRHXyy3ZrRjeqKGzbGsDBb0XlFtYoDONG7KdJJJ+boA6x/qKyOTz8uYVHNUThTVVXYmSWo2X8vTtk006lmU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1614357189004551.9940443023239; Fri, 26 Feb 2021 08:33:09 -0800 (PST) Received: by mail-wr1-f48.google.com with SMTP id n4so9179358wrx.1 for ; Fri, 26 Feb 2021 08:33:08 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id u4sm13542416wrr.37.2021.02.26.08.33.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:33:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iDkHmNWDJUjsisDNEA+tDXF79jqbgWv+Yeaa+F2Cdm4=; b=rhVyMHsN6sD4XaBIDbOSPH1f1Gxr3TD8f2RxmMFKtq7gJOLr9b9PCG7lF2RGJdV+a3 EPKU5+KwYMhmhmFfgwQ846SFNCq9yEwx90M2M4mamOpZr0rr3DuqHZyHUaX3z9qovWfY fLc+IKIokbn1R+jlLTV1aJ+ZbjWU/3ZDv3zn4RoRCAWR9uxMY6YYaK9G/381qbrMSbIl 2NfWE/eMlHxRTeiJog1gV8HCQO7afmWuqVXh1gAOqHWTwX8LkGaXz8xt6Ie5vadA6U2c WeFjXCAvr79dn/okef5E+E3lmQMd4G0ygdkqSUHgf12ErIe1czDxwREOBsGJ2/e3F0gd PPsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iDkHmNWDJUjsisDNEA+tDXF79jqbgWv+Yeaa+F2Cdm4=; b=L6JG+Oqsm8AYwnXkw0Ysb8ozs9rmR2gYqobRKaDtDqkSNfb9ZwWD73of+ZBixWvdiG BLubNpjxU4pFQNi8Pj7+IeLGtAZXDNnod47iYh2V3nx2iXedar/9H8G6F3qAs4DVrZWT KcP6CEkqJVdRkAaoK9MrzPqYbCqrCpVtOH7amb8JM5CgfMQ2S+rdiZ/HnS4jtqNxGAiu NhcfHd26f/3GcJK12LhRnrgZ3xhgvnUhKm5q8g5h0mDpryzpfK9x+ieZ/i46l80jN1Iu +/iA9xvWI0IA8WcUqNGYgbdn/7SlWemg1iuQWIw9A48fUyJSkoxHC/H6hX0MinFvrlpG koNg== X-Gm-Message-State: AOAM532kgvP9PODis7lrgUGpwaiCw3tyxj9A4pvYX6nvO+cwovdoetXu /0UTYaRuNxqHuuol5V8H394= X-Google-Smtp-Source: ABdhPJxqjSMsXYtj2QXQr+6zgeLmiV+MsnF1M83EQ0njAM80bc1w/PXXjJ1efpDeWkDlTSCXO7L4pQ== X-Received: by 2002:adf:dcd2:: with SMTP id x18mr4226702wrm.361.1614357187210; Fri, 26 Feb 2021 08:33:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 06/16] cpu: Directly use get_memory_mapping() fallback handlers in place Date: Fri, 26 Feb 2021 17:32:17 +0100 Message-Id: <20210226163227.4097950-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c: $ git grep -F -- '->get_memory_mapping' hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp); hw/core/cpu.c:439: k->get_memory_mapping =3D cpu_common_get_memory_map= ping; target/i386/cpu.c:7422: cc->get_memory_mapping =3D x86_cpu_get_memory_= mapping; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 1de00bbb474..5abf8bed2e4 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappin= gList *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->get_memory_mapping(cpu, list, errp); -} + if (cc->get_memory_mapping) { + cc->get_memory_mapping(cpu, list, errp); + return; + } =20 -static void cpu_common_get_memory_mapping(CPUState *cpu, - MemoryMappingList *list, - Error **errp) -{ error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); } =20 @@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357194; cv=none; d=zohomail.com; s=zohoarc; b=DnasAuSmcx8r9zKkb0F/P3zwdTNE1Dvg3ITxvdtFYkyNrxl7QrRLvX45BaMMRmKcqUUGGkjWWAgaUmaYmgZiFguvlLZZQY3xADWtlnll8dGL1raHFGOD+cH9BMcIFySL4Gh5KS6nW5bKhX48uVxee6pvcXIVDMIfzdGMXj2p4Bk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357194; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cqYmlwAyP4EwEP7vrTu/PZK1/0mxFb/0cmm6txRTavI=; b=ii+G2cX9QRQ40SUfRnsF+h9psV2MlfPK7vc6ulzCEMTQjC92pljIX+bxVYPiOALHB7PRXevi85P1AZS64l1IhsT8rIHsaHDTd1IF03zflTUO1IY0vFlxdM0QlrSoDEEHUKh64OYsZEjzFpxL0k1bjasCk9YPOGFUTd9UPUe8G5w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.zohomail.com with SMTPS id 16143571947001000.7819805402046; Fri, 26 Feb 2021 08:33:14 -0800 (PST) Received: by mail-wr1-f41.google.com with SMTP id d11so9156125wrj.7 for ; Fri, 26 Feb 2021 08:33:14 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 6sm14814560wra.63.2021.02.26.08.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:33:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cqYmlwAyP4EwEP7vrTu/PZK1/0mxFb/0cmm6txRTavI=; b=Q/GVwYuNkGxJ/Q9ke2SuYtBSrUx9A0eBdyi9iyh/L1/r8tBvCHUEzBfvy/KNeNNiSn Cr9TNGEdwYFcSYMMdCyOeY1i/Ba4c8agsZ1NOCvMqIbZU4KXJ2kcFOqOJpuAsO31fGSc h0OJ0ZsXfoXThyE0Sa14wpmw+MsUuHlaWW5dGVBOSDCOaZHZigJnejCy28de26GfIfDu Zhcl+lJwEuDk4cM2C5NLpB+DAjfuBIMhXccHgVE/27sLDUUqxlUkIs8RvpNvdacpnubd rB9gusji7bHn0Ai3bFKvCZlU4J/GUpdCOtvKWGy9nA32xrkBfuQJAnM0Y4+CEOMDDs37 4jIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cqYmlwAyP4EwEP7vrTu/PZK1/0mxFb/0cmm6txRTavI=; b=aQl+ynbfKgcMwZPzuotAAqrz8hjJnZ/7MAHh5QVEtel9sY32YJlb4gKBEoxKERJb5v 1oeJ1rG7KIbOjreqsysm1zAnGP/93wShkUfUYV+2FuNG808mjiFwI8KbqvGCg9CZVFz4 viAPkuxIpd6nMgnS5AuGYVC6+hscMYBatPOTMvo2loLteLows6nrVvtewjNv3vjnwE29 BGU1SjYm9YpfzyM3tBoJD1K+nEe70xAAPB1HwRjGGExkavWP/JDHiBYH9s2DQHYrG6Td RZigpz2pYVudz4l0QDoXXQGtCVVRzRAJa3chuKP0hRlyUll25FDGmHsz1BELkH+sJvsj VA/A== X-Gm-Message-State: AOAM531nzfsRK15WiYxCdR/5/P+gshFJDiBugozIAuipjOsOXPwKvxdr jTMk1UpDxmFvveK9Onhl/Fo= X-Google-Smtp-Source: ABdhPJyVKet7fLK7FFHIzc2XCusgC2/GSoYvxHG+n79W7ILnKLJBaG7CY5eh5N1nm9IzkHfSN4GVnQ== X-Received: by 2002:adf:f1c4:: with SMTP id z4mr4226490wro.404.1614357192932; Fri, 26 Feb 2021 08:33:12 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 07/16] cpu: Introduce CPUSystemOperations structure Date: Fri, 26 Feb 2021 17:32:18 +0100 Message-Id: <20210226163227.4097950-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b12028c3c03..ab89235cb45 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,6 +80,12 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 +/* + * struct CPUSystemOperations: System operations specific to a CPU class + */ +typedef struct CPUSystemOperations { +} CPUSystemOperations; + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -190,6 +196,9 @@ struct CPUClass { bool gdb_stop_before_watchpoint; struct AccelCPUClass *accel_cpu; =20 + /* when system emulation is not available, this pointer is NULL */ + struct CPUSystemOperations system_ops; + /* when TCG is not available, this pointer is NULL */ struct TCGCPUOps *tcg_ops; }; --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) client-ip=209.85.128.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357201; cv=none; d=zohomail.com; s=zohoarc; b=bkifXcdODhhv3vgLlE1Qk+RTIeUr7rP+BJdFY2cPn6MGWuXB6HpGJLttb848ikcYYsxjAIxNK34scSHXHJSRIwwiGnArpoXqL/quswp9bnwsHcmmyDMyY3tZmB89SXckJtahUodqD5bw4H+Phcu/DsmKVZz4N7SLW4STLW9mDCY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357201; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Vuc9PsSLt2QcMz7V44LFADU1+acM0s5lJbReK29D000=; b=CMBwvemCY4kdSCnP+QEOnYqpSJtT8qMw/nSWk06YJM8vcNrWzGTmOzo9gpCD06FlrVlsdrhEWlXSMxWT5uFBedL+6JdwygjCQLwzYT29uNIszTfMqsve5gSQXY42dmmWT1IggMnbJSKcFOMQSz2k+bzSvonYjc8m6A6jP8wlS+0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.zohomail.com with SMTPS id 1614357201163487.7633354100742; Fri, 26 Feb 2021 08:33:21 -0800 (PST) Received: by mail-wm1-f50.google.com with SMTP id x16so7890745wmk.3 for ; Fri, 26 Feb 2021 08:33:20 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id f2sm10929721wrq.34.2021.02.26.08.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:33:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vuc9PsSLt2QcMz7V44LFADU1+acM0s5lJbReK29D000=; b=Bfi19QPGpQFQ3L5Iqi+WyuiNpxkTNf4P8xxDYMle/dTLWa+0XAxhG2ERuZEfItnFGg GeELWChCYC79YyddyOATVRgUstihC+kGEWhApztxLfHBk8M/h+CXrxovwUSEp1dsipxj n4E+wh0kJVhJAfVXp7EgsIU5+2fowHNTl4x/P99wJB1UfE206Zmh3PbQYbNSeKfPjU08 p5k4IdCULqrNCRKoqkTaYER70ZDB2mweOxJ6Z1UiWnkiQJc808WOhltnkLL3LxKB0MYl f9/dXvAHbTZAWyttCUDcAv/Dg2VGDZhVvMoOzQQ2MthYAFB0Hwt3c/D6J55kV8CXfFg/ wVIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Vuc9PsSLt2QcMz7V44LFADU1+acM0s5lJbReK29D000=; b=M4Wf/N8+fpYE+diMhQJaI0bQrYQ1D+dpbyFm7GmT1c2GYbcVX5LV8C/X80PuxqlVrX X01PY2zjiD5LASCSnYpy2bQ7HQn1yTFL8iXHzEEAUE71rXD601ZFlOUVKo11OusT09GG cd7t34G5KXtmHdlsuQL5us5PpNI/cuKp/ztYySobhdpl89aAXHtPUpZv+GQhnSoN/3jV HevnQI/F1rL7G1EE5L0GyevzjfrlZ4//MB0+C4MfciZg7QvhmM+My1KXUE+7dxcWVi3x 0wyP/uPG4QRLRlrOwkb4msdhmLrOA47MHDAt7rIOq3t0S1z9adXTvJWc2/5Kj2EiXy7E xb8Q== X-Gm-Message-State: AOAM5316FDf0IlVU84QD6StBYus2AJqiqdBeBFkYlnJb0gAHBKyd9Hyx PDBDXU6TQVsSxAfAObFj9RA= X-Google-Smtp-Source: ABdhPJyhPNOa1XWROgQB+EA4KJqUQUEQ597fWUb8xq1bcW7m5/CqxV8d2Gxq0gAR4w78qCB6yjD4Tg== X-Received: by 2002:a7b:c119:: with SMTP id w25mr3617650wmi.127.1614357199103; Fri, 26 Feb 2021 08:33:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 08/16] cpu: Move CPUClass::vmsd to CPUSystemOperations Date: Fri, 26 Feb 2021 17:32:19 +0100 Message-Id: <20210226163227.4097950-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Migration is specific to system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 6 ++++-- cpu.c | 12 ++++++------ target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 21 files changed, 29 insertions(+), 27 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ab89235cb45..bd1cb3b0d37 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -84,6 +84,10 @@ struct AccelCPUClass; * struct CPUSystemOperations: System operations specific to a CPU class */ typedef struct CPUSystemOperations { + /** + * @vmsd: State description for migration. + */ + const VMStateDescription *vmsd; } CPUSystemOperations; =20 /** @@ -128,7 +132,6 @@ typedef struct CPUSystemOperations { * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @vmsd: State description for migration. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -183,7 +186,6 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); =20 - const VMStateDescription *vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/cpu.c b/cpu.c index bfbe5a66f95..619b8c14f94 100644 --- a/cpu.c +++ b/cpu.c @@ -138,13 +138,13 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) #endif /* CONFIG_TCG */ =20 #ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); + assert(cc->system_ops.vmsd =3D=3D NULL); #else if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + if (cc->system_ops.vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->system_ops.vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } @@ -154,10 +154,10 @@ void cpu_exec_unrealizefn(CPUState *cpu) CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 #ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); + assert(cc->system_ops.vmsd =3D=3D NULL); #else - if (cc->vmsd !=3D NULL) { - vmstate_unregister(NULL, cc->vmsd, cpu); + if (cc->system_ops.vmsd !=3D NULL) { + vmstate_unregister(NULL, cc->system_ops.vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index faabffe0796..ee65971da8e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -237,7 +237,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_alpha_cpu; + cc->system_ops.vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b8bc89e71fc..11505e1db10 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2299,7 +2299,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->vmsd =3D &vmstate_arm_cpu; + cc->system_ops.vmsd =3D &vmstate_arm_cpu; cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f4596932ba..0e55d5f4838 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->vmsd =3D &vms_avr_cpu; + cc->system_ops.vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 29a865b75d2..c0392c7def3 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -293,7 +293,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_cris_cpu; + cc->system_ops.vmsd =3D &vmstate_cris_cpu; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4f142de6e45..58c09824fff 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -162,7 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_hppa_cpu; + cc->system_ops.vmsd =3D &vmstate_hppa_cpu; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6a53446e6a5..ae7f7763dfc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7426,7 +7426,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; - cc->vmsd =3D &vmstate_x86_cpu; + cc->system_ops.vmsd =3D &vmstate_x86_cpu; #endif /* !CONFIG_USER_ONLY */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c23d72874c0..bc5f448584c 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -241,7 +241,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_lm32_cpu; + cc->system_ops.vmsd =3D &vmstate_lm32_cpu; #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c98fb1e33be..30cf308633f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -533,7 +533,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_m68k_cpu; + cc->system_ops.vmsd =3D &vmstate_m68k_cpu; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 335dfdc734e..17670bbfb59 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -387,7 +387,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; - cc->vmsd =3D &vmstate_mb_cpu; + cc->system_ops.vmsd =3D &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bf70c77295f..3389b879087 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -720,7 +720,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_mips_cpu; + cc->system_ops.vmsd =3D &vmstate_mips_cpu; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; cc->gdb_num_core_regs =3D 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 83bec34d36c..953a440576f 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -122,7 +122,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_moxie_cpu; + cc->system_ops.vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; cc->tcg_ops =3D &moxie_tcg_ops; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 79d246d1930..c127bcc0680 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -204,7 +204,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_openrisc_cpu; + cc->system_ops.vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16f1a342388..70651c9b721 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -623,7 +623,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ - cc->vmsd =3D &vmstate_riscv_cpu; + cc->system_ops.vmsd =3D &vmstate_riscv_cpu; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d35eb39a1bb..8ba8a96b4d5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -517,7 +517,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_s390_cpu; + cc->system_ops.vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; #endif diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index bd44de53729..706ef971c3d 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -262,7 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->gdb_num_core_regs =3D 59; =20 - cc->vmsd =3D &vmstate_sh_cpu; + cc->system_ops.vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index aece2c7dc83..f14a26c154a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -889,7 +889,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_sparc_cpu; + cc->system_ops.vmsd =3D &vmstate_sparc_cpu; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 12894ffac6a..277b41194fb 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -146,7 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_uc32_cpu; + cc->system_ops.vmsd =3D &vmstate_uc32_cpu; cc->tcg_ops =3D &uc32_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6bedd5b97b8..80f12ebf995 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -218,7 +218,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - cc->vmsd =3D &vmstate_xtensa_cpu; + cc->system_ops.vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index e7324e85cdb..65c45e7870a 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10885,7 +10885,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_ppc_cpu; + cc->system_ops.vmsd =3D &vmstate_ppc_cpu; #endif #if defined(CONFIG_SOFTMMU) cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357209; cv=none; d=zohomail.com; s=zohoarc; b=FH2ybE5R+k2EW0gKAZwimEVbh6hDH5PH68FuQjIOe+7/L/CPgYnLhiTLdsD1gCd4dG9Jwud6u1nhDYVveJrxbavcAcw43PLIkhqSP5EfZCEHO9OTD5L41nF7mDx9Y9FMsu/60kb3z2xx3V6XCg/qn8Gme8OW1gKX/PM38z45dsc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357209; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id m6sm14242583wrv.73.2021.02.26.08.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:33:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R56Oi6nr8e9B0WiiV+if7tvwfnjn9mxxVgPa8IGhuYc=; b=GIK9QnVGxJj+2JyxxpSs2kwEIQSaQgByN23qMxB9CnyIZlfO11v5Cy1mdDF7/FZg9S hT+clxlxxrXwtpxbNMie7alBa+EdYWAPFEAIaFZlxCQ4PMR4QUAAbyeidWQs4SugWkBB NkiTYrLn8oYYy6TZzgU6+066q+Z5gvVDK2YqIxJPrMgcsA2OjQTLDskYj5SgvzExQkfi MWS5BPvufyr6ibMRkbheWeD1oYk1KUxGr2CNrhDeezx0guNLLylObuwgI+JZL8gary51 h5FgfO14/4kLCyrquBEp/OMkE2yq+6lPMzxvemYCBDVaTIokK+szjW0RmD93Pv6362SI NmmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=R56Oi6nr8e9B0WiiV+if7tvwfnjn9mxxVgPa8IGhuYc=; b=MdCgMov7afpcw2FY7stXJeobN5ytX4zsoRh85TIei328BHTLJRhLxAue7HI3OxloLc xaOmvw3VgeCEvHeEoTWPUPHt1Q/mngVsLdpFOtmpRA+7aWTNU1JN7R97/SEXuILT2Y7b 4sywLb7+18KFpxtZIAtlkOz+n2yNj6nnCpphXlFJWAWIPOF1UyeTmVb3SWmvao83o2UL Ck+DzZIkuUQfmM7dR/Nz/8iOIPTuvhtNprIfYTTwUgmKLBHEX5bkop6j6Qxo9VFmwD1E g48IqD4MTgN08MoIHWYl7SSPVwWJmT8KXV7cKgOzJGJUyiGVPy8uS13LWHq0amG8B+ep aChg== X-Gm-Message-State: AOAM5328XFhuGh8+AB1pYegwZld5TbK2ai4SVLkyJp+/Z2s4ETC2domO HmU0NS5dxQ2nn/3mM4mxkR0= X-Google-Smtp-Source: ABdhPJxDb1NSzZxAVDXyJpmM/HE7k20qbNt0LkezV0LwNuf9xxvYg+GA9NeqMNOj3xAo6Ws07C81uQ== X-Received: by 2002:a5d:570c:: with SMTP id a12mr4117870wrv.209.1614357205310; Fri, 26 Feb 2021 08:33:25 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 09/16] cpu: Move CPUClass::virtio_is_big_endian to CPUSystemOperations Date: Fri, 26 Feb 2021 17:32:20 +0100 Message-Id: <20210226163227.4097950-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) VirtIO devices are only meaningful with system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 13 ++++++++----- hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 4 files changed, 12 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bd1cb3b0d37..fe85a1b81e6 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -84,6 +84,14 @@ struct AccelCPUClass; * struct CPUSystemOperations: System operations specific to a CPU class */ typedef struct CPUSystemOperations { + /** + * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts + * runtime configurable endianness is currently big-endian. + * Non-configurable CPUs can use the default implementation of this me= thod. + * This method should not be used by any callers other than the pre-1.0 + * virtio devices. + */ + bool (*virtio_is_big_endian)(CPUState *cpu); /** * @vmsd: State description for migration. */ @@ -97,10 +105,6 @@ typedef struct CPUSystemOperations { * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @virtio_is_big_endian: Callback to return %true if a CPU which supports - * runtime configurable endianness is currently big-endian. Non-configurab= le - * CPUs can use the default implementation of this method. This method sho= uld - * not be used by any callers other than the pre-1.0 virtio devices. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. @@ -159,7 +163,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 5abf8bed2e4..86b65624a9e 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->virtio_is_big_endian) { - return cc->virtio_is_big_endian(cpu); + if (cc->system_ops.virtio_is_big_endian) { + return cc->system_ops.virtio_is_big_endian(cpu); } return target_words_bigendian(); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 11505e1db10..3cbb17a5879 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2300,7 +2300,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->system_ops.vmsd =3D &vmstate_arm_cpu; - cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; + cc->system_ops.virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; #endif diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 65c45e7870a..2e5c272190b 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10909,7 +10909,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_core_xml_file =3D "power-core.xml"; #endif #ifndef CONFIG_USER_ONLY - cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; + cc->system_ops.virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif cc->disas_set_info =3D ppc_disas_set_info; =20 --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357212; cv=none; d=zohomail.com; s=zohoarc; b=WWPSIeH9cXlDZ8exVdB0otS3MErODEJnwFJjG3N10CavTSOgVyg//e9vZeYWj9Ho6yLfXCmcO8FqdnAxV8Ncz70o5uggPV/5xGZ5b/S9zqcPp15csLatlH2fILAbhdmVpR7cHwOEpSh/G14wi4v8cKakrBejIy2jouSBR4PNif0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357212; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=baCqRvN00Z/k/DEXOAL/5KZeUutEyX82NGJVX6NTZLs=; b=DUKK2dl13ikFRkPNOsjSDPtt5csLk4NNek7OQS+vMiBLDUx4MC07P11eIcqDdBs94Vfn0rkIIigpYUgMtCYdRo+0yn+7rtxErXf5szOnJEISkrk3p1G6lM/SYIqZ/TBcJWg9MAlxO9ZPKrlA4SWMc3q3r0uTipXcilplGYuOwFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1614357212861645.2861764225347; Fri, 26 Feb 2021 08:33:32 -0800 (PST) Received: by mail-wr1-f50.google.com with SMTP id n4so9180645wrx.1 for ; Fri, 26 Feb 2021 08:33:32 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id k15sm16664975wrn.0.2021.02.26.08.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:33:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=baCqRvN00Z/k/DEXOAL/5KZeUutEyX82NGJVX6NTZLs=; b=u9dJ4pVzXSwxq5IiQhegu1sOjFWEW7egjSz/FQoJsphQZou4dOyYMt0eyvd1ZgYI6r zqw8JHbducASA5HS/LZ3IDuoCxy/JoYX7PmwaANwfv1Bt2SEWk1ESZ13U652VxxjYQcA chHDFzB3YckwqnfDNaOi+A6mErQGQNHVzHcCmjtSipUb3q/7Q52B+ef0+5arwqIKxXGs c2m4stWcUo+fvEELRbJmVZjoPiEV8XVgtNdsjt4Mko0ETa5Q4OzMZezwFlgDHwg6t1fl 9og7VK24NfaTw4gzWLjpa73mLaO+wnVBT4cca6dgJXNwAfR9uX2xvLRSNbyt3Qqr5nJk j07g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=baCqRvN00Z/k/DEXOAL/5KZeUutEyX82NGJVX6NTZLs=; b=PFNXsAu1obS3FGWdPdBsMeEDezpfwHHv2+M3vGD3g9j8AoTeK0VRTPwKwB4AdJlBqu 62wgymhUwD39jkiwpcmxx4X/aQvpSGwM8WThppMNtpB7APXI2eM/WVn4Ycm7RmQBlKDZ 29HPI2mswLN1dCgyAwOSy6+HIKaHSNzev/+zujpTzLnvxCeZaVfkH1AJl2KRw4oURwGu mP1lS38Acnai207TYy+kTWVzPyHOxjRGOGSBQljetIGo0qrWnecJSwtEY2KQTB7VAXuA 8Ph2fMzt57obfMkKXdx3E5OeN7JI+4+Mki8b4rixRJAD/UA639U/E8IRMGnrbm0xayIE G0ZA== X-Gm-Message-State: AOAM532wtfaTQfTkQIi7H08nYZ4SkpVtzzV1xjEIqt5ONlWM7343gY6v yYNmbCpQliXJ3MXb8cS6FGw= X-Google-Smtp-Source: ABdhPJxjCs2JxncQfVm0YSDcSrxNvscTyYbwl/6+HAP3K697dMGc/y0VN2x7nHDMh7k8w+9BY14CcA== X-Received: by 2002:a5d:558b:: with SMTP id i11mr4035012wrv.176.1614357210978; Fri, 26 Feb 2021 08:33:30 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 10/16] cpu: Move CPUClass::get_crash_info to CPUSystemOperations Date: Fri, 26 Feb 2021 17:32:21 +0100 Message-Id: <20210226163227.4097950-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) cpu_get_crash_info() is called on GUEST_PANICKED events, which only occur in system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 6 +++++- hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- target/s390x/cpu.c | 2 +- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fe85a1b81e6..87186e85d44 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -84,6 +84,11 @@ struct AccelCPUClass; * struct CPUSystemOperations: System operations specific to a CPU class */ typedef struct CPUSystemOperations { + /** + * @get_crash_info: Callback for reporting guest crash information in + * GUEST_PANICKED events. + */ + GuestPanicInformation* (*get_crash_info)(CPUState *cpu); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. @@ -166,7 +171,6 @@ struct CPUClass { int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); - GuestPanicInformation* (*get_crash_info)(CPUState *cpu); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 86b65624a9e..ddf5635d87b 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) CPUClass *cc =3D CPU_GET_CLASS(cpu); GuestPanicInformation *res =3D NULL; =20 - if (cc->get_crash_info) { - res =3D cc->get_crash_info(cpu); + if (cc->system_ops.get_crash_info) { + res =3D cc->system_ops.get_crash_info(cpu); } return res; } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ae7f7763dfc..9692843256c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7421,7 +7421,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->get_crash_info =3D x86_cpu_get_crash_info; + cc->system_ops.get_crash_info =3D x86_cpu_get_crash_info; cc->write_elf64_note =3D x86_cpu_write_elf64_note; cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 8ba8a96b4d5..f9107cb7179 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -518,7 +518,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_s390_cpu; - cc->get_crash_info =3D s390_cpu_get_crash_info; + cc->system_ops.get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357219; cv=none; d=zohomail.com; s=zohoarc; b=kakiPWzGtnZKOZxvDhmVc3r1IOstwUbNqYiwZDSvt5Bg5TRS7zpi6nLfmu3GWPSg9ZaMR8qKdq8ELKQdPLr0H1TeFwIDNWkSLLZiB5nAgF9R3USWC3xPsd/llkndr93VG9n0UGOsHGjTfmesSo+IUC8sOJJb3770R/dL4e+zhcA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357219; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yppSFDQsnap9fkQDMIB4LM/Hd6+rcDegPvCr9hlrbG4=; b=g7KJekmypf83XTvTI+undZKEaly4Rc5b20JbqkOqQ+BvtX6syJ5svxqceg+jV4QAjLEbGjJW1K+wWBIHgMKLd4eyr2PbX8yrvuGHY+ZBJFY2uBUoDf4oWf5C9XaVBZL6WfO3gvXclwsBSfnCt2ahi0hX8p6HW3Ya76KcPJ9mf0k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1614357219137223.01495935114554; Fri, 26 Feb 2021 08:33:39 -0800 (PST) Received: by mail-wm1-f43.google.com with SMTP id o16so8346467wmh.0 for ; Fri, 26 Feb 2021 08:33:38 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id i8sm15756579wry.90.2021.02.26.08.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:33:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yppSFDQsnap9fkQDMIB4LM/Hd6+rcDegPvCr9hlrbG4=; b=RqsbZxiETkb9P1vuejki+clVSger/BhVc0Y+i01T/lyJFro47QMOYFEMQqeEX1LpL7 egUkAka5uPw2lBcHNJ0vmPvzX9kShILCt1LYd8Pc9NUFZF7PVRR9mU/2Ba6LPYuoFGiX 0QzMPnkIQ8Gipw3mRI7eJ5wJbatX3hOLnjEQwf7/+Ea9Hazd3VKiE3yb8f1F8053wia+ 8dVtdlIqd1a81+yFEZNVyrWfaC1WXzW0A1HUaR85voFyhcrK+7V6v7I6GBmEZphGFTaO SNXSDtatdL7TS9VV6VAY2aMOUueFGtwOyHf5y1DLVof1oYhLzgBmOalNvfEGE7DeiYIl 6cRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yppSFDQsnap9fkQDMIB4LM/Hd6+rcDegPvCr9hlrbG4=; b=gSKjS+GoyMB2RVO0s9QY0xIF8UOUmKS+UmV9x0fgDD92LZocsFqH/ZtF4IRTuoBZjs cwG6po1LmzOYroJavL3XP8EfmbXYq5LKqJJqdpwLigQmqxtxo1mOHXZZAfOpa2ofHRrk SYF9WMxwHA1pfcruFDSki7xmnaEUXiZk2JlGMJTcCuzl9mvJ98XOfhFCPS7d2Jw+Ix8M ceg/aituIaAcskx4RTkvcOrc/xEEthtOEcbb8+FKpon3nEiBlTTUA2FI79KcpTcDfh9e o7pYLgbjlHKwepIufD0djifRvVprBVBKi9yYE/ChoCtVq+l1eYKGEA6Oa+mxg1EXoUkA fdFA== X-Gm-Message-State: AOAM5338z20PmBXWOKjxLC/hrjt0yqYDMF6AYXchnlDqcKgC7hiiDqii jWaNE2oEb0LyH10CIj9e4i4= X-Google-Smtp-Source: ABdhPJyOK9RTuFTedODbjc7g1TL8cebAOnvvMApPg5J3vznBAKYuBzcDbmpndB9iBqkymNzHHyJROA== X-Received: by 2002:a1c:f409:: with SMTP id z9mr3633637wma.141.1614357217212; Fri, 26 Feb 2021 08:33:37 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 11/16] cpu: Move CPUClass::write_elf* to CPUSystemOperations Date: Fri, 26 Feb 2021 17:32:22 +0100 Message-Id: <20210226163227.4097950-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The write_elf*() handlers are used to dump vmcore images. This feature is only meaningful for system emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 41 +++++++++++++++++++-------------- hw/core/cpu.c | 16 ++++++------- target/arm/cpu.c | 4 ++-- target/i386/cpu.c | 8 +++---- target/s390x/cpu.c | 2 +- target/ppc/translate_init.c.inc | 4 ++-- 6 files changed, 41 insertions(+), 34 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 87186e85d44..e8c2e9af3bb 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,6 +89,30 @@ typedef struct CPUSystemOperations { * GUEST_PANICKED events. */ GuestPanicInformation* (*get_crash_info)(CPUState *cpu); + /** + * @write_elf32_note: Callback for writing a CPU-specific ELF note to a + * 32-bit VM coredump. + */ + int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf64_note: Callback for writing a CPU-specific ELF note to a + * 64-bit VM coredump. + */ + int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 32-bit VM coredump. + */ + int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + /** + * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 64-bit VM coredump. + */ + int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. @@ -133,14 +157,6 @@ typedef struct CPUSystemOperations { * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. - * @write_elf64_note: Callback for writing a CPU-specific ELF note to a - * 64-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. - * @write_elf32_note: Callback for writing a CPU-specific ELF note to a - * 32-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -184,15 +200,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 - int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/hw/core/cpu.c b/hw/core/cpu.c index ddf5635d87b..3dc8faf6086 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_qemunote) { + if (!cc->system_ops.write_elf32_qemunote) { return 0; } - return (*cc->write_elf32_qemunote)(f, cpu, opaque); + return (*cc->system_ops.write_elf32_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_note) { + if (!cc->system_ops.write_elf32_note) { return -1; } - return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); + return (*cc->system_ops.write_elf32_note)(f, cpu, cpuid, opaque); } =20 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, @@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_qemunote) { + if (!cc->system_ops.write_elf64_qemunote) { return 0; } - return (*cc->write_elf64_qemunote)(f, cpu, opaque); + return (*cc->system_ops.write_elf64_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_note) { + if (!cc->system_ops.write_elf64_note) { return -1; } - return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); + return (*cc->system_ops.write_elf64_note)(f, cpu, cpuid, opaque); } =20 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3cbb17a5879..4941a651e64 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2301,8 +2301,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->system_ops.vmsd =3D &vmstate_arm_cpu; cc->system_ops.virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; - cc->write_elf64_note =3D arm_cpu_write_elf64_note; - cc->write_elf32_note =3D arm_cpu_write_elf32_note; + cc->system_ops.write_elf64_note =3D arm_cpu_write_elf64_note; + cc->system_ops.write_elf32_note =3D arm_cpu_write_elf32_note; #endif cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9692843256c..c34d41d4c79 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7422,10 +7422,10 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->system_ops.get_crash_info =3D x86_cpu_get_crash_info; - cc->write_elf64_note =3D x86_cpu_write_elf64_note; - cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; - cc->write_elf32_note =3D x86_cpu_write_elf32_note; - cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; + cc->system_ops.write_elf64_note =3D x86_cpu_write_elf64_note; + cc->system_ops.write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; + cc->system_ops.write_elf32_note =3D x86_cpu_write_elf32_note; + cc->system_ops.write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->system_ops.vmsd =3D &vmstate_x86_cpu; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index f9107cb7179..dcfbb7832e1 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -519,7 +519,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_s390_cpu; cc->system_ops.get_crash_info =3D s390_cpu_get_crash_info; - cc->write_elf64_note =3D s390_cpu_write_elf64_note; + cc->system_ops.write_elf64_note =3D s390_cpu_write_elf64_note; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 2e5c272190b..b1ac3291be1 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10888,8 +10888,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->system_ops.vmsd =3D &vmstate_ppc_cpu; #endif #if defined(CONFIG_SOFTMMU) - cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; - cc->write_elf32_note =3D ppc32_cpu_write_elf32_note; + cc->system_ops.write_elf64_note =3D ppc64_cpu_write_elf64_note; + cc->system_ops.write_elf32_note =3D ppc32_cpu_write_elf32_note; #endif =20 cc->gdb_num_core_regs =3D 71; --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; 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Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 12/16] cpu: Move CPUClass::asidx_from_attrs to CPUSystemOperations Date: Fri, 26 Feb 2021 17:32:23 +0100 Message-Id: <20210226163227.4097950-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 8 +++++--- hw/core/cpu.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- 4 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e8c2e9af3bb..fc3c4c217b1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -84,6 +84,11 @@ struct AccelCPUClass; * struct CPUSystemOperations: System operations specific to a CPU class */ typedef struct CPUSystemOperations { + /** + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or + * a memory access with the specified memory transaction attribu= tes. + */ + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); /** * @get_crash_info: Callback for reporting guest crash information in * GUEST_PANICKED events. @@ -153,8 +158,6 @@ typedef struct CPUSystemOperations { * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -196,7 +199,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 3dc8faf6086..d38eda36bc3 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attr= s) CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); + if (cc->system_ops.asidx_from_attrs) { + ret =3D cc->system_ops.asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4941a651e64..86af15b0625 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2298,7 +2298,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; - cc->asidx_from_attrs =3D arm_asidx_from_attrs; + cc->system_ops.asidx_from_attrs =3D arm_asidx_from_attrs; cc->system_ops.vmsd =3D &vmstate_arm_cpu; cc->system_ops.virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->system_ops.write_elf64_note =3D arm_cpu_write_elf64_note; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c34d41d4c79..36b34eee62f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7418,7 +7418,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->asidx_from_attrs =3D x86_asidx_from_attrs; + cc->system_ops.asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->system_ops.get_crash_info =3D x86_cpu_get_crash_info; --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; 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Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 13/16] cpu: Move CPUClass::get_phys_page_debug to CPUSystemOperations Date: Fri, 26 Feb 2021 17:32:24 +0100 Message-Id: <20210226163227.4097950-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 21 +++++++++++++-------- hw/core/cpu.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 24 files changed, 38 insertions(+), 33 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fc3c4c217b1..5bc66653c19 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -84,6 +84,19 @@ struct AccelCPUClass; * struct CPUSystemOperations: System operations specific to a CPU class */ typedef struct CPUSystemOperations { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * and the associated memory transaction attributes to use for t= he + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. @@ -153,11 +166,6 @@ typedef struct CPUSystemOperations { * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -196,9 +204,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/hw/core/cpu.c b/hw/core/cpu.c index d38eda36bc3..f0c558c002e 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cc->system_ops.get_phys_page_attrs_debug) { + return cc->system_ops.get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); + return cc->system_ops.get_phys_page_debug(cpu, addr); } =20 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ee65971da8e..b430771b7c8 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -236,7 +236,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 86af15b0625..87a581fa47c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2297,7 +2297,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; + cc->system_ops.get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_att= rs_debug; cc->system_ops.asidx_from_attrs =3D arm_asidx_from_attrs; cc->system_ops.vmsd =3D &vmstate_arm_cpu; cc->system_ops.virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0e55d5f4838..d532a579c1b 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -212,7 +212,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; - cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D avr_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index c0392c7def3..6434f170387 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -292,7 +292,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D cris_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_cris_cpu; #endif =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 58c09824fff..cc72a6ea1ce 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -161,7 +161,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_hppa_cpu; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 36b34eee62f..f6f5c333b7e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7420,7 +7420,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) #ifndef CONFIG_USER_ONLY cc->system_ops.asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; + cc->system_ops.get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_att= rs_debug; cc->system_ops.get_crash_info =3D x86_cpu_get_crash_info; cc->system_ops.write_elf64_note =3D x86_cpu_write_elf64_note; cc->system_ops.write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index bc5f448584c..515728b7f5d 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -240,7 +240,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_lm32_cpu; #endif cc->gdb_num_core_regs =3D 32 + 7; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 30cf308633f..63c45e98e97 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -532,7 +532,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) - cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_m68k_cpu; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 17670bbfb59..73e99d2d9be 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -386,7 +386,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; + cc->system_ops.get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attr= s_debug; cc->system_ops.vmsd =3D &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 3389b879087..b95856e3137 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -719,7 +719,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_mips_cpu; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 953a440576f..8512bc50715 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -121,7 +121,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a389..615aed9729f 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -237,7 +237,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index c127bcc0680..02397842757 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -203,7 +203,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D openrisc_cpu_get_phys_page_debu= g; cc->system_ops.vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 70651c9b721..7abf7685184 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -621,7 +621,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->system_ops.vmsd =3D &vmstate_riscv_cpu; #endif diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26b..1191c686637 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -204,7 +204,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) =20 cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; - cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index dcfbb7832e1..11acf9b5727 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -516,7 +516,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_s390_cpu; cc->system_ops.get_crash_info =3D s390_cpu_get_crash_info; cc->system_ops.write_elf64_note =3D s390_cpu_write_elf64_note; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 706ef971c3d..533e02bd3d9 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -256,7 +256,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index f14a26c154a..46d3e0ec668 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -888,7 +888,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_sparc_cpu; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcba..c9ae4249fc1 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -170,7 +170,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->tcg_ops =3D &tricore_tcg_ops; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 277b41194fb..eb4eec341a1 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -145,7 +145,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->has_work =3D uc32_cpu_has_work; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->system_ops.vmsd =3D &vmstate_uc32_cpu; cc->tcg_ops =3D &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 80f12ebf995..befcb004d6f 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -215,7 +215,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; + cc->system_ops.get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; cc->system_ops.vmsd =3D &vmstate_xtensa_cpu; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index b1ac3291be1..82438c5c72b 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10884,7 +10884,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; 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Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 14/16] cpu: Move CPUClass::get_memory_mapping to CPUSystemOperations Date: Fri, 26 Feb 2021 17:32:25 +0100 Message-Id: <20210226163227.4097950-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 8 +++++--- hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5bc66653c19..caca5896592 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -84,6 +84,11 @@ struct AccelCPUClass; * struct CPUSystemOperations: System operations specific to a CPU class */ typedef struct CPUSystemOperations { + /** + * @get_memory_mapping: Callback for obtaining the memory mappings. + */ + void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, + Error **errp); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ @@ -157,7 +162,6 @@ typedef struct CPUSystemOperations { * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled. - * @get_memory_mapping: Callback for obtaining the memory mappings. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -201,8 +205,6 @@ struct CPUClass { void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); - void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, - Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/hw/core/cpu.c b/hw/core/cpu.c index f0c558c002e..606fc753bf0 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingL= ist *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_memory_mapping) { - cc->get_memory_mapping(cpu, list, errp); + if (cc->system_ops.get_memory_mapping) { + cc->system_ops.get_memory_mapping(cpu, list, errp); return; } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f6f5c333b7e..92691a22de5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7419,7 +7419,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 #ifndef CONFIG_USER_ONLY cc->system_ops.asidx_from_attrs =3D x86_asidx_from_attrs; - cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; + cc->system_ops.get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->system_ops.get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_att= rs_debug; cc->system_ops.get_crash_info =3D x86_cpu_get_crash_info; cc->system_ops.write_elf64_note =3D x86_cpu_write_elf64_note; --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357248; cv=none; d=zohomail.com; s=zohoarc; b=ZtFQBiB+LTVQI/N1V+JAQKC4bb7Tfhnv7yI0adaY72r9DfYSULsQaUhyEgC2YfxzhSXopEk+oscYruyUqkOC3cg/d6HiVeKMSC9zTBh76p8urvM7SPj+z8X/NjvJI7LdOoPufKF0F6dhdVnwB1hrvFiYLK5dpcbAPmETahmsNC4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357248; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1HLdFJWL8bdcObinvQ00cBeAj9ZX31JFSy5j9SyL+cY=; b=Dd3YBzZ6QkitMDupnhF/JL8v/EOAgcNK91m/sypu16d2L8oK8Pl647YD8SzW/6W92RI3FiOgWkcqCVdU2qgMxzAS7nR5zp6KUMXr+aXt/cMaoDhBwYKmK7hc6oMv502c8h/dGWAEc7aDTLsCXdev/QKUmE961FZrLx9Yg2xm/5w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1614357248834476.90675098452414; Fri, 26 Feb 2021 08:34:08 -0800 (PST) Received: by mail-wr1-f49.google.com with SMTP id f12so5361415wrx.8 for ; Fri, 26 Feb 2021 08:34:08 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id f7sm11919094wmh.39.2021.02.26.08.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:34:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1HLdFJWL8bdcObinvQ00cBeAj9ZX31JFSy5j9SyL+cY=; b=CK0+fUr9Ri8+o36olFsTDqO4jHpX4S2hLUOCMak8AFIZuvFCkl4UZY5Sde7CDzdoAZ VN7hNDmTHdCR40Fsbqa2HUHcJXfsb5WCj9+CfXWx0xuEoqZ2VUC3p9ViOosLoleU6VGW eKILoFtYMLRlkrL+ZFi1wWJzd417jaMdhOVdty16IvRkvRWc+1egm1/b9/N+7dQvfcVM YERC41+mZBzv3PbjZpAIAXSZFasITmylFC/4oV3e+mDLHiJGGNbVjox2RLgd5tDSJkKm rAVIf5EpViILwr3JGUUoj3q1OpiQAKiD+WSPJsI3Ljzfhk2ztY8lawfBQz6R5zpVYhfo Z+5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1HLdFJWL8bdcObinvQ00cBeAj9ZX31JFSy5j9SyL+cY=; b=SgT0GP4oBEg2ZyZTko1rioX1+t7MGlLdyjbXsFDA0MpvqEqG1t/sWzsbNYmce/aFIb 6UsNTMuIWpB3ruMu7U6QXQR8kYpdDWkunSjeGuKzJYBOONmAoWXgogTIAdLuGo8pWVPY lysugcwr1dt5PZrYy3H3bG7cPPw/yIfQQV4Txm79eo2lJvVIkehHfSCdxfCzqOdMroGH hZog9er1i747JWYawMuBQt8tGw2rdmaVlKxlWXzl9gZ2Qjl/kNPncBjVu6Fxf7rnw4xU xleCQuA7BgN1vRTzqWlOmAJgliEhbc2mlpNLYAsZ6F+PjzdDa8juGgLDUohhlpNEmZ6d 2czA== X-Gm-Message-State: AOAM530R7tbHHx+2gIhIrpYLAK6gmiagOHxtb9/21HZ9PWwtEscE9nIs DiyfSgHRKnWtuTOyMGOfkgI= X-Google-Smtp-Source: ABdhPJygu1zzxtF+KSEGtXf/vZOYHEd9DYBa2h1OBnS7mEAls1N7pxpqK3sUHi25llu9AoBf/ObXJg== X-Received: by 2002:adf:bac8:: with SMTP id w8mr4196713wrg.68.1614357246883; Fri, 26 Feb 2021 08:34:06 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. 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Iglesias" Subject: [PATCH 15/16] cpu: Move CPUClass::get_paging_enabled to CPUSystemOperations Date: Fri, 26 Feb 2021 17:32:26 +0100 Message-Id: <20210226163227.4097950-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 6 ++++-- hw/core/cpu.c | 4 ++-- target/i386/cpu.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index caca5896592..47e65d517f6 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,6 +89,10 @@ typedef struct CPUSystemOperations { */ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); + /** + * @get_paging_enabled: Callback for inquiring whether paging is enabl= ed. + */ + bool (*get_paging_enabled)(const CPUState *cpu); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ @@ -161,7 +165,6 @@ typedef struct CPUSystemOperations { * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. - * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -204,7 +207,6 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); - bool (*get_paging_enabled)(const CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 606fc753bf0..8bd7bda6b0b 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_paging_enabled) { - return cc->get_paging_enabled(cpu); + if (cc->system_ops.get_paging_enabled) { + return cc->system_ops.get_paging_enabled(cpu); } =20 return false; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 92691a22de5..743c6b6d164 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7415,7 +7415,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; - cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; + cc->system_ops.get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY cc->system_ops.asidx_from_attrs =3D x86_asidx_from_attrs; --=20 2.26.2 From nobody Wed Nov 19 03:02:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614357254; cv=none; d=zohomail.com; s=zohoarc; b=huZRXir8OnUqB5knNFqgZYEWlrtt6pjKa47T05VhBorPjVhI1cyh0VzkoKlIYwCPeHjCtWuaU3qq94Redkl4x+G1k7QK93xNNP17OaWyslMy0bQU6Fu3PtkKsX5oCkGiz3mTbvMGrJSJHu2WDw5O8Fi16waZkA0oOo9aE2Jfsi0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614357254; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PprgWzaisAMGWPHww2n0qNOft5TZjwIRKtLOc4TMAEs=; b=PqUK62wvENz5Bhxd/MSzGK1kFnqUAIdB50UW5ATEMS42Y4F6CxKqcXZb+cqEo8pm+6pUlDbFGhG1TdQa75XbClSPbqdN73YL62QSp2Lu1s59rHS11RaINYDxTpNEMEO9UT942vq/j4ot/rhU4g9ngFv8u0SddFX/4lj++cIojVc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1614357254929969.8870097506452; Fri, 26 Feb 2021 08:34:14 -0800 (PST) Received: by mail-wm1-f43.google.com with SMTP id p3so7918708wmc.2 for ; Fri, 26 Feb 2021 08:34:14 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id m6sm14245609wrv.73.2021.02.26.08.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 08:34:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PprgWzaisAMGWPHww2n0qNOft5TZjwIRKtLOc4TMAEs=; b=fuKckJ4TE33Pak2neWxSvjeCDGfEBe5OI4VvvYE7upnN7YW65eSvXkzDVPy792b2oR 7+32toOnxKag5RUh5Rdj9YZLR6jRGo8a6CdImCDp0s0ptT7S1Ju4ZyqXzpDAogd9s3bd AalOQlpEThHlN8VIIrP2rDslZHFsUgVuFU+YOWJj3ZC6/q7HRWyhOl5q7IwfVdmpo2iy lsRktn4tPQts9R+p6lW9J+3Im+atzEtWPtsX/94kom6vuIL/b9UZ8jOViXq9SK0oqFMp wRYqMbfffGHItIkhFwUHzxlyrURua2CsWH+mWqr3M48B3xHf0DQj22heQJnWkmo76q0L y4Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=PprgWzaisAMGWPHww2n0qNOft5TZjwIRKtLOc4TMAEs=; b=iAfWmTnbx+VCLye6irgqnGLHJ7TYslqJqsMjWSBINhRrEfSS632BDXTXUNsivIgtul JupZm3Y69cryHcTnbGw1z2QRJGbKNvXNd/mVhfbniKKrE2V6DrDCql7d74Ehsw8dr01W A3KxGVuGsf+sJCEQwtB2V/8lDMSk5xdtqNT/1QFhsQBUOLH0Iz7MwWYkbUEGbPf7UUuI suKX7t3qV9znKyf+OAxrhIr+hsfW9RhSKC9h+f9AMNx7pI9X25fNc2yOsRPkjEXL9w14 ZgFQyA15qm20cdx+h9bTogd0MOCJXAnsBEjxgC4uXxZU22+OIwONiWfjy6cVqr9dvFps i+3A== X-Gm-Message-State: AOAM5312AhuNO0UAZqe1VVf+l7sSQtHEvp8jYwjmtb+W1m1eWkysvc45 NX9fmIUGdU9iNjjs6OsgMks= X-Google-Smtp-Source: ABdhPJz1v3KCRjGGB0E6fhsxandwsh0yCO9HrvXjARyoJ89417mlFvI7GVKmBNlyu2hIh/hHajJ1wA== X-Received: by 2002:a1c:c244:: with SMTP id s65mr3706705wmf.96.1614357253121; Fri, 26 Feb 2021 08:34:13 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Sarah Harris , Paolo Bonzini , Max Filippov , Yoshinori Sato , qemu-s390x@nongnu.org, Michael Rolnik , qemu-ppc@nongnu.org, Marek Vasut , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Michael Walle , Guan Xuetao , Laurent Vivier , Anthony Green , Palmer Dabbelt , David Hildenbrand , qemu-riscv@nongnu.org, David Gibson , Peter Maydell , Cornelia Huck , Jiaxun Yang , Richard Henderson , Chris Wulff , "Michael S. Tsirkin" , Aurelien Jarno , Aleksandar Rikalo , Sagar Karandikar , Claudio Fontana , Thomas Huth , Artyom Tarasenko , Greg Kurz , Stafford Horne , Bastian Koppelmann , Mark Cave-Ayland , Marcel Apfelbaum , "Edgar E. Iglesias" Subject: [PATCH 16/16] cpu: Restrict cpu_paging_enabled / cpu_get_memory_mapping to sysemu Date: Fri, 26 Feb 2021 17:32:27 +0100 Message-Id: <20210226163227.4097950-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210226163227.4097950-1-f4bug@amsat.org> References: <20210226163227.4097950-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 47e65d517f6..29e1623f775 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -499,6 +499,8 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) extern bool mttcg_enabled; #define qemu_tcg_mttcg_enabled() (mttcg_enabled) =20 +#if !defined(CONFIG_USER_ONLY) + /** * cpu_paging_enabled: * @cpu: The CPU whose state is to be inspected. @@ -516,8 +518,6 @@ bool cpu_paging_enabled(const CPUState *cpu); void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, Error **errp); =20 -#if !defined(CONFIG_USER_ONLY) - /** * cpu_write_elf64_note: * @f: pointer to a function that writes memory to a file --=20 2.26.2