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Thu, 25 Feb 2021 19:25:54 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns Date: Fri, 26 Feb 2021 11:18:59 +0800 Message-Id: <20210226031902.23656-76-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> References: <20210226031902.23656-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.c.inc | 40 +++++++++++++++++++++++++ target/riscv/vector_helper.c | 21 +++++++++++++ 4 files changed, 67 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6dffd9be45d..f0cbddcd94f 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -96,6 +96,8 @@ DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle1_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse1_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 472626f1950..bb7b1d30f4f 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -251,6 +251,10 @@ vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2= _nfvm vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm =20 +# Vector unit-stride mask load/store insns. +vle1_v 000 000 1 01011 ..... 000 ..... 0000111 @r2 +vse1_v 000 000 1 01011 ..... 000 ..... 0100111 @r2 + # Vector strided insns. vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 1e9f5148ccd..4dd1e29368c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -747,6 +747,46 @@ GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op, st_us= _check) GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check) GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check) =20 +/* + *** unit stride mask load and store + */ +static bool ld_us_mask_op(DisasContext *s, arg_vle1_v *a, uint8_t eew) +{ + uint32_t data =3D 0; + gen_helper_ldst_us *fn =3D gen_helper_vle1_v; + + /* EMUL =3D 1, NFIELDS =3D 1 */ + data =3D FIELD_DP32(data, VDATA, LMUL, 0); + data =3D FIELD_DP32(data, VDATA, NF, 1); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); +} + +static bool ld_us_mask_check(DisasContext *s, arg_vle1_v *a, uint8_t eew) +{ + /* EMUL =3D 1, NFIELDS =3D 1 */ + return require_rvv(s) && vext_check_isa_ill(s); +} + +static bool st_us_mask_op(DisasContext *s, arg_vse1_v *a, uint8_t eew) +{ + uint32_t data =3D 0; + gen_helper_ldst_us *fn =3D gen_helper_vse1_v; + + /* EMUL =3D 1, NFIELDS =3D 1 */ + data =3D FIELD_DP32(data, VDATA, LMUL, 0); + data =3D FIELD_DP32(data, VDATA, NF, 1); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); +} + +static bool st_us_mask_check(DisasContext *s, arg_vse1_v *a, uint8_t eew) +{ + /* EMUL =3D 1, NFIELDS =3D 1 */ + return require_rvv(s) && vext_check_isa_ill(s); +} + +GEN_VEXT_TRANS(vle1_v, MO_8, vle1_v, ld_us_mask_op, ld_us_mask_check) +GEN_VEXT_TRANS(vse1_v, MO_8, vse1_v, st_us_mask_op, st_us_mask_check) + /* *** stride load and store */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 55560116ff6..e7a3084876d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -361,6 +361,27 @@ GEN_VEXT_ST_US(vse16_v, int16_t, ste_h) GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) =20 +/* + *** unit stride mask load and store, EEW =3D 1 + */ +void HELPER(vle1_v)(void *vd, void *v0, target_ulong base, + CPURISCVState *env, uint32_t desc) +{ + /* evl =3D ceil(vl/8) */ + uint8_t evl =3D (env->vl + 7) >> 3; + vext_ldst_us(vd, base, env, desc, lde_b, + 0, evl, GETPC(), MMU_DATA_LOAD); +} + +void HELPER(vse1_v)(void *vd, void *v0, target_ulong base, + CPURISCVState *env, uint32_t desc) +{ + /* evl =3D ceil(vl/8) */ + uint8_t evl =3D (env->vl + 7) >> 3; + vext_ldst_us(vd, base, env, desc, ste_b, + 0, evl, GETPC(), MMU_DATA_STORE); +} + /* *** index: access vector element from indexed memory */ --=20 2.17.1