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Thu, 25 Feb 2021 19:25:30 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 Date: Fri, 26 Feb 2021 11:18:52 +0800 Message-Id: <20210226031902.23656-69-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> References: <20210226031902.23656-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Sagar Karandikar , Frank Chang , Bastian Koppelmann , Hsiangkai Wang , Palmer Dabbelt , Greentime Hu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/gdbstub.c | 184 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d95165b3acb..a110b6ead9b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -575,6 +575,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 if (strcmp(xmlname, "riscv-csr.xml") =3D=3D 0) { return cpu->dyn_csr_xml; + } else if (strcmp(xmlname, "riscv-vector.xml") =3D=3D 0) { + return cpu->dyn_vreg_xml; } =20 return NULL; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ad2497229db..f324949beb1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -275,6 +275,7 @@ struct RISCVCPU { CPURISCVState env; =20 char *dyn_csr_xml; + char *dyn_vreg_xml; =20 /* Configuration Settings */ struct { diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5f96b7ea2a9..dd883612c77 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -20,6 +20,32 @@ #include "exec/gdbstub.h" #include "cpu.h" =20 +struct TypeSize { + const char *gdb_type; + const char *id; + int size; + const char suffix; +}; + +static const struct TypeSize vec_lanes[] =3D { + /* quads */ + { "uint128", "quads", 128, 'q' }, + /* 64 bit */ + { "uint64", "longs", 64, 'l' }, + /* 32 bit */ + { "uint32", "words", 32, 'w' }, + /* 16 bit */ + { "uint16", "shorts", 16, 's' }, + /* + * TODO: currently there is no reliable way of telling + * if the remote gdb actually understands ieee_half so + * we don't expose it in the target description for now. + * { "ieee_half", 16, 'h', 'f' }, + */ + /* bytes */ + { "uint8", "bytes", 8, 'b' }, +}; + int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -101,6 +127,96 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8= _t *mem_buf, int n) return 0; } =20 +/* + * Convert register index number passed by GDB to the correspond + * vector CSR number. Vector CSRs are defined after vector registers + * in dynamic generated riscv-vector.xml, thus the starting register index + * of vector CSRs is 32. + * Return 0 if register index number is out of range. + */ +static int riscv_gdb_vector_csrno(int num_regs) +{ + /* + * The order of vector CSRs in the switch case + * should match with the order defined in csr_ops[]. + */ + switch (num_regs) { + case 32: + return CSR_VSTART; + case 33: + return CSR_VXSAT; + case 34: + return CSR_VXRM; + case 35: + return CSR_VCSR; + case 36: + return CSR_VL; + case 37: + return CSR_VTYPE; + case 38: + return CSR_VLENB; + default: + /* Unknown register. */ + return 0; + } +} + +static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +{ + uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + int cnt =3D 0; + for (i =3D 0; i < vlenb; i +=3D 8) { + cnt +=3D gdb_get_reg64(buf, + env->vreg[(n * vlenb + i) / 8]); + } + return cnt; + } + + int csrno =3D riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val =3D 0; + int result =3D riscv_csrrw_debug(env, csrno, &val, 0, 0); + + if (result =3D=3D 0) { + return gdb_get_regl(buf, val); + } + + return 0; +} + +static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int = n) +{ + uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + for (i =3D 0; i < vlenb; i +=3D 8) { + env->vreg[(n * vlenb + i) / 8] =3D ldq_p(mem_buf + i); + } + return vlenb; + } + + int csrno =3D riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val =3D ldtul_p(mem_buf); + int result =3D riscv_csrrw_debug(env, csrno, NULL, val, -1); + + if (result =3D=3D 0) { + return sizeof(target_ulong); + } + + return 0; +} + static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) { if (n < CSR_TABLE_SIZE) { @@ -187,6 +303,68 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int= base_reg) return CSR_TABLE_SIZE; } =20 +static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + GString *s =3D g_string_new(NULL); + g_autoptr(GString) ts =3D g_string_new(""); + int reg_width =3D cpu->cfg.vlen; + int num_regs =3D 0; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, "= "); + g_string_append_printf(s, ""); + + /* First define types and totals in a whole VL */ + for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count =3D reg_width / vec_lanes[i].size; + g_string_printf(ts, "%s", vec_lanes[i].id); + g_string_append_printf(s, + "", + ts->str, vec_lanes[i].gdb_type, count); + } + + /* Define unions */ + g_string_append_printf(s, ""); + for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { + g_string_append_printf(s, "", + vec_lanes[i].suffix, + vec_lanes[i].id); + } + g_string_append(s, ""); + + /* Define vector registers */ + for (i =3D 0; i < 32; i++) { + g_string_append_printf(s, + "", + i, reg_width, base_reg++); + num_regs++; + } + + /* Define vector CSRs */ + const char *vector_csrs[7] =3D { + "vstart", "vxsat", "vxrm", "vcsr", + "vl", "vtype", "vlenb" + }; + + for (i =3D 0; i < 7; i++) { + g_string_append_printf(s, + "", + vector_csrs[i], TARGET_LONG_BITS, base_reg+= +); + num_regs++; + } + + g_string_append_printf(s, ""); + + cpu->dyn_vreg_xml =3D g_string_free(s, false); + return num_regs; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); @@ -198,6 +376,12 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } + if (env->misa & RVV) { + gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_v= ector, + ricsv_gen_dynamic_vector_xml(cs, + cs->gdb_num_= regs), + "riscv-vector.xml", 0); + } #if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virt= ual, 1, "riscv-32bit-virtual.xml", 0); --=20 2.17.1