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Thu, 25 Feb 2021 19:24:42 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum Date: Fri, 26 Feb 2021 11:18:43 +0800 Message-Id: <20210226031902.23656-60-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> References: <20210226031902.23656-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 12 ++++++------ target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++--------- target/riscv/internals.h | 9 +++++++++ 3 files changed, 24 insertions(+), 15 deletions(-) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 7c4ab92ecbe..ad84aeebc1c 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint3= 2_t rm) { int softrm; =20 - if (rm =3D=3D 7) { + if (rm =3D=3D RISCV_FRM_DYN) { rm =3D env->frm; } switch (rm) { - case 0: + case RISCV_FRM_RNE: softrm =3D float_round_nearest_even; break; - case 1: + case RISCV_FRM_RTZ: softrm =3D float_round_to_zero; break; - case 2: + case RISCV_FRM_RDN: softrm =3D float_round_down; break; - case 3: + case RISCV_FRM_RUP: softrm =3D float_round_up; break; - case 4: + case RISCV_FRM_RMM: softrm =3D float_round_ties_away; break; default: diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index de7152dc323..3f453ed457a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2321,7 +2321,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_d, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2400,7 +2400,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_w, \ gen_helper_##NAME##_d, \ }; \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2432,7 +2432,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2468,7 +2468,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ static gen_helper_opfvf *const fns[2] =3D { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2498,7 +2498,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2534,7 +2534,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ static gen_helper_opfvf *const fns[2] =3D { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2611,7 +2611,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_helper_##NAME##_d, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2757,7 +2757,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2804,7 +2804,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 959b81b3016..469cc418c4e 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -36,6 +36,15 @@ target_ulong fclass_d(uint64_t frs1); extern const VMStateDescription vmstate_riscv_cpu; #endif =20 +enum { + RISCV_FRM_RNE =3D 0, /* Round to Nearest, ties to Even */ + RISCV_FRM_RTZ =3D 1, /* Round towards Zero */ + RISCV_FRM_RDN =3D 2, /* Round Down */ + RISCV_FRM_RUP =3D 3, /* Round Up */ + RISCV_FRM_RMM =3D 4, /* Round to Nearest, ties to Max Magnitude */ + RISCV_FRM_DYN =3D 7, /* Dynamic rounding mode */ +}; + static inline uint64_t nanbox_s(float32 f) { return f | MAKE_64BIT_MASK(32, 32); --=20 2.17.1