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Thu, 25 Feb 2021 19:19:19 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field Date: Fri, 26 Feb 2021 11:17:47 +0800 Message-Id: <20210226031902.23656-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> References: <20210226031902.23656-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 7 +++++++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 15 ++++++++++++++- target/riscv/csr.c | 25 ++++++++++++++++++++++++- 4 files changed, 46 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9d911f81093..2c1e6c46a2d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -327,6 +327,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArr= ay *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); +bool riscv_cpu_vector_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); @@ -373,6 +374,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ul= ong); #define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS =20 typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; @@ -428,6 +430,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *= env, target_ulong *pc, =20 #ifdef CONFIG_USER_ONLY flags |=3D TB_FLAGS_MSTATUS_FS; + flags |=3D TB_FLAGS_MSTATUS_VS; #else flags |=3D cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { @@ -442,6 +445,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } } + + if (riscv_cpu_vector_enabled(env)) { + flags |=3D env->mstatus & MSTATUS_VS; + } #endif =20 *pflags =3D flags; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4196ef8b692..ba4c1c7076f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -370,6 +370,7 @@ #define MSTATUS_SPIE 0x00000020 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2f43939fb6d..b07e10d472f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -109,11 +109,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } =20 +/* Return true is vector support is currently enabled */ +bool riscv_cpu_vector_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_VS) { + if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)= ) { + return false; + } + return true; + } + + return false; +} + void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL; + MSTATUS64_UXL | MSTATUS_VS; bool current_virt =3D riscv_cpu_virt_enabled(env); =20 g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d2ae73e4a08..778d5b85e92 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -260,6 +260,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong val) return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; + env->mstatus |=3D MSTATUS_VS; #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; if (vs(env, csrno) >=3D 0) { @@ -290,6 +291,13 @@ static int read_vxrm(CPURISCVState *env, int csrno, ta= rget_ulong *val) =20 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + env->mstatus |=3D MSTATUS_VS; +#endif + env->vxrm =3D val; return 0; } @@ -302,6 +310,13 @@ static int read_vxsat(CPURISCVState *env, int csrno, t= arget_ulong *val) =20 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + env->mstatus |=3D MSTATUS_VS; +#endif + env->vxsat =3D val; return 0; } @@ -314,6 +329,13 @@ static int read_vstart(CPURISCVState *env, int csrno, = target_ulong *val) =20 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return -RISCV_EXCP_ILLEGAL_INST; + } + env->mstatus |=3D MSTATUS_VS; +#endif + env->vstart =3D val; return 0; } @@ -477,7 +499,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW; + MSTATUS_TW | MSTATUS_VS; =20 if (!riscv_cpu_is_32bit(env)) { /* @@ -490,6 +512,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) mstatus =3D (mstatus & ~mask) | (val & mask); =20 dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | + ((mstatus & MSTATUS_VS) =3D=3D MSTATUS_VS) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); env->mstatus =3D mstatus; --=20 2.17.1