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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id p11sm7083709pjb.31.2021.02.25.19.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Feb 2021 19:21:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=slvNnSfOOMqStV16Kdm2mbEbsrFhdjQ7TW2K/w2z7kw=; b=bCphI4g7sisltEyWc3RgN+HWtYOiVreaq7ExKzTnE+tFHxw/DB0yWEhpvnV8WM2BBp KPxG2xMIk/XsgqEgO5gqbkbZgYZakP9oAH9VKbuVKnglQODSCfzbjv80zw4q6MOVRIA9 VoCkn4d0YpOyn4IICOuuoYKbZ7JXZFsBr+HF6qn2fQ3nrHKo4ffBgi5mpqiZ84bCSc2f j5q4UInoSrADm6falNXdcyyEx8iEACx+uKjYdRaBv/aaoyLhyOFil62kNf1f87VlISx2 V634nwQyoxmpMfWUkFrVM9HCjAxQ4ci+YIi18KNXYuMMG0LGVwRVulx0FGHIw30WP6zK 5yag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=slvNnSfOOMqStV16Kdm2mbEbsrFhdjQ7TW2K/w2z7kw=; b=Gg5GOVKCLN7QkVNRJnXY0lZhlPOhBs6+eSb3vSRalzAZYFdW6Ae5kt0nrLufAY+fGt cwoagxuZmVG1mK2aIq2zdxTkqvCV7U5KiyO9dWkydpwe9h7852MFdt/0VUaLX945LcfF qONInDz2YPrZl0oHN2/y7PfINSuknSXAPex0XYwF7BUj3z8R8XXg9jP0UMf7yUwsrq0P 7pPAmxweS3hfJtok8n5LRYBpGL0sVOry9WDEswvUjC1LrGkcKhVPpRbTSNwJPC2K0gHd 7nVywLs8HoIFf0E7jqD2b1dsC1QlWzyk8EXB1ej+dD+SwnQNYMZtczbpl7cBAJx1UTrL 86ZQ== X-Gm-Message-State: AOAM533KXLUbgXhKaiikbPYeyvwaNUlQgRwFCHqkJo5ffCASNTKNb/B5 1KC/K7uFacyotKBRluOr6tG2JT1qmRUuWA== X-Google-Smtp-Source: ABdhPJxdy5COrI5WZClo/mDMc9PBwEAC3AofDGfE096/XfEJPycU8I5xj5+mmq+svkInQfWROHrxZw== X-Received: by 2002:a63:4f57:: with SMTP id p23mr994141pgl.281.1614309695342; Thu, 25 Feb 2021 19:21:35 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Date: Fri, 26 Feb 2021 11:18:09 +0800 Message-Id: <20210226031902.23656-26-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> References: <20210226031902.23656-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 43 ++++++++++++++++++------- target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++- 2 files changed, 42 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ad79669a2ce..367b182735f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -395,18 +395,27 @@ FIELD(TB_FLAGS, HLSX, 15, 1) bool riscv_cpu_is_32bit(CPURISCVState *env); =20 /* - * A simplification for VLMAX - * =3D (1 << LMUL) * VLEN / (8 * (1 << SEW)) - * =3D (VLEN << LMUL) / (8 << SEW) - * =3D (VLEN << LMUL) >> (SEW + 3) - * =3D VLEN >> (SEW + 3 - LMUL) + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + * + * then, we can calculate VLMAX =3D vlen >> (vsew + 3 - lmul) + * e.g. vlen =3D 256 bits, SEW =3D 16, LMUL =3D 1/8 + * =3D> VLMAX =3D vlen >> (1 + 3 - (-3)) + * =3D 256 >> 7 + * =3D 2 */ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) { - uint8_t sew, lmul; - - sew =3D FIELD_EX64(vtype, VTYPE, VSEW); - lmul =3D FIELD_EX64(vtype, VTYPE, VLMUL); + uint8_t sew =3D FIELD_EX64(vtype, VTYPE, VSEW); + int8_t lmul =3D sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); return cpu->cfg.vlen >> (sew + 3 - lmul); } =20 @@ -419,12 +428,22 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState= *env, target_ulong *pc, *cs_base =3D 0; =20 if (riscv_has_ext(env, RVV)) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ uint32_t vlmax =3D vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl); + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t maxsz =3D vlmax << sew; + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) + && (maxsz >=3D 8); flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, FIELD_EX64(env->vtype, VTYPE, VILL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 367fb28186f..72d0bc109b0 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1268,7 +1268,17 @@ GEN_VEXT_AMO_TRANS(vamomaxuei64_v, MO_64, 35, rwdvm,= amo_op, amo_check) /* *** Vector Integer Arithmetic Instructions */ -#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) + +/* + * MAXSZ returns the maximum vector size can be operated in bytes, + * which is used in GVEC IR when vl_eq_vlmax flag is set to true + * to accerlate vector operation. + */ +static inline uint32_t MAXSZ(DisasContext *s) +{ + int scale =3D s->lmul - 3; + return scale < 0 ? s->vlen >> -scale : s->vlen << scale; +} =20 static bool opivv_check(DisasContext *s, arg_rmrr *a) { --=20 2.17.1