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Thu, 25 Feb 2021 19:20:53 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions Date: Fri, 26 Feb 2021 11:18:01 +0800 Message-Id: <20210226031902.23656-18-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> References: <20210226031902.23656-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 53 +++++++++---------------- target/riscv/vector_helper.c | 14 ++++++- 2 files changed, 31 insertions(+), 36 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index ccfa93cf2f8..a3732e76e09 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -132,28 +132,29 @@ static bool require_noover_seg(const int8_t dst, cons= t int8_t nf, return !is_overlapped(dst, nf, src, 1); } =20 -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) +static bool do_vsetvl(DisasContext *ctx, int rd, int rs1, TCGv s2) { - TCGv s1, s2, dst; + TCGv s1, dst; =20 if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { return false; } =20 - s2 =3D tcg_temp_new(); dst =3D tcg_temp_new(); =20 - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 =3D=3D 0) { + if (rd =3D=3D 0 && rs1 =3D=3D 0) { + s1 =3D tcg_temp_new(); + tcg_gen_mov_tl(s1, cpu_vl); + } else if (rs1 =3D=3D 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ s1 =3D tcg_const_tl(RV_VLEN_MAX); } else { s1 =3D tcg_temp_new(); - gen_get_gpr(s1, a->rs1); + gen_get_gpr(s1, rs1); } - gen_get_gpr(s2, a->rs2); + gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(a->rd, dst); + gen_set_gpr(rd, dst); mark_vs_dirty(ctx); tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); lookup_and_goto_ptr(ctx); @@ -165,35 +166,17 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetv= l *a) return true; } =20 -static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) +static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) { - TCGv s1, s2, dst; - - if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { - return false; - } - - s2 =3D tcg_const_tl(a->zimm); - dst =3D tcg_temp_new(); - - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 =3D=3D 0) { - /* As the mask is at least one bit, RV_VLEN_MAX is >=3D VLMAX */ - s1 =3D tcg_const_tl(RV_VLEN_MAX); - } else { - s1 =3D tcg_temp_new(); - gen_get_gpr(s1, a->rs1); - } - gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(a->rd, dst); - mark_vs_dirty(ctx); - gen_goto_tb(ctx, 0, ctx->pc_succ_insn); - ctx->base.is_jmp =3D DISAS_NORETURN; + TCGv s2 =3D tcg_temp_new(); + gen_get_gpr(s2, a->rs2); + return do_vsetvl(ctx, a->rd, a->rs1, s2); +} =20 - tcg_temp_free(s1); - tcg_temp_free(s2); - tcg_temp_free(dst); - return true; +static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) +{ + TCGv s2 =3D tcg_const_tl(a->zimm); + return do_vsetvl(ctx, a->rd, a->rs1, s2); } =20 /* vector register offset from env */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 89aa7cbf73f..61917d34ffe 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -31,12 +31,24 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_= ulong s1, { int vlmax, vl; RISCVCPU *cpu =3D env_archcpu(env); + uint64_t lmul =3D FIELD_EX64(s2, VTYPE, VLMUL); uint16_t sew =3D 8 << FIELD_EX64(s2, VTYPE, VSEW); uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); bool vill =3D FIELD_EX64(s2, VTYPE, VILL); target_ulong reserved =3D FIELD_EX64(s2, VTYPE, RESERVED); =20 - if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { + if (lmul & 4) { + /* Fractional LMUL. */ + if (lmul =3D=3D 4 || + cpu->cfg.elen >> (8 - lmul) < sew) { + vill =3D true; + } + } + + if ((sew > cpu->cfg.elen) + || vill + || (ediv !=3D 0) + || (reserved !=3D 0)) { /* only set vill bit. */ env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); env->vl =3D 0; --=20 2.17.1