From nobody Wed Nov 19 04:35:03 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1614311019; cv=none; d=zohomail.com; s=zohoarc; b=gSwp5b4r6ZgxjUCpTGq+59O+8DHAtT0RcWeg+M3x1lX3a3e7TNPcSqYELNYrQOzDs9NNPZ9wO++Wj3vbOHKGZNhj3E7jVdTRiYeqEeELOEmX+EIgMWtsv9jnQ98AW/FDezkF+0NvLy9lXdlh/24l3de0dMb+t+S4QT6y4s/Xi44= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614311019; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=S6xkQfRd6vUSxqxVLXftVFLAZqRmy4HsvooD2JMQJkM=; b=CNwhz/G5UMKC9pwF2O4J7uEENhQ8VGbxC+JcjHeemSfN+jHaICel2WXFjNpeUdWgw6PxsW8JkuBetEmoYOhytjPGQq24G++AUqH5a2ubC2eNS4JcRtEE2FFPPzlfL5ZsJEWn28QhiavIB4Gqp0zgehrqsDEw+8nRSnfUEl1AsxY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614311019918754.6287591479361; Thu, 25 Feb 2021 19:43:39 -0800 (PST) Received: from localhost ([::1]:45296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lFU2U-00054u-OA for importer@patchew.org; Thu, 25 Feb 2021 22:43:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33856) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFTg0-0006po-O5 for qemu-devel@nongnu.org; Thu, 25 Feb 2021 22:20:24 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:34892) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lFTfv-0000oK-V9 for qemu-devel@nongnu.org; Thu, 25 Feb 2021 22:20:24 -0500 Received: by mail-pj1-x1034.google.com with SMTP id e9so5280899pjj.0 for ; Thu, 25 Feb 2021 19:20:19 -0800 (PST) Received: from frankchang-ThinkPad-T490.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id p11sm7083709pjb.31.2021.02.25.19.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Feb 2021 19:20:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S6xkQfRd6vUSxqxVLXftVFLAZqRmy4HsvooD2JMQJkM=; b=d6HEWVxkYflth2qZk8cEma4j2QOqOxF1w5MUvwNYGd3MTGm/GZ2u5k0ZsPs3gawENZ VVcz0okBYksjNa40KgKrAcISXLLDaEb3BAlZnmDLeDyhTaWx1IY/a5PdxsaLPRjuehNK W6BMVxi2M0h5bhihDmK/qHe2ldVk8dL0wyvAAq/iLXcuRFIA6wDII6aTOks8+MJrQHoq 7H7lrSbLuIzH1+OmJLWqL3h7OPXJ53Tqb03TF+isbIY6pqTyo43DdI/O4+YM+znsCMvS wozfpslIunFIhqOqPQ5gwa/yBg31iBFU2Dsaz+gn8lD0Gy9hDr73v/DSsuTOFyTjOkRD pknA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=S6xkQfRd6vUSxqxVLXftVFLAZqRmy4HsvooD2JMQJkM=; b=YQyKH/uSPyR1dDjkh+iwLVqiTcOgzhFaXRG58k+1eNTXMRXGybr0Dlq0Dqf2YQMSTM glddODEZg2XTRhHx9oJWXe70s+W0BRpATbA6nkbIPH/pAW1uOiNiRp6IO5XireZGHLn0 ncLS+cIKuKOm/L/QfbATcHLTCp+V4x3JLCXtSIFBWBy3KVe7aMegRAQvi0DmeN6neJ7S hwl/KsxOjOZLAU0YqyBXdPKRRTZkyvLwPmFdpNP1Iq0+tUCbZ1zupHqIRDDbC/X3tDfT inH897a9aqueoSQLAKkCfTz4299tgfR1YNK04youXZdcoCc/svHrDqU02Weh+8YqDrpr snhw== X-Gm-Message-State: AOAM531aHp/imrV8Injlkf/bbyxShWPRrkX/7tgJKSRg/93T0QIzUiL8 0u3ySJstJTvqJwRLiMBYSWVmAP1RzICXuw== X-Google-Smtp-Source: ABdhPJxAU7iyWHdo3w/+tJ8gyw68m0fSLfHGD0d2bJICs7EAGlosvlgSCvIoxemTbx7htAli4c6tQQ== X-Received: by 2002:a17:90a:c588:: with SMTP id l8mr1180018pjt.120.1614309618442; Thu, 25 Feb 2021 19:20:18 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL Date: Fri, 26 Feb 2021 11:17:56 +0800 Message-Id: <20210226031902.23656-13-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> References: <20210226031902.23656-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600) and MSTATUS_FS (0x6000) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 18 ++++++++++-------- target/riscv/translate.c | 16 ++++++++++++++-- target/riscv/vector_helper.c | 16 ++++++++++++++-- 3 files changed, 38 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2c1e6c46a2d..0ba330e613d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -105,10 +105,10 @@ typedef struct CPURISCVState CPURISCVState; =20 #define RV_VLEN_MAX 256 =20 -FIELD(VTYPE, VLMUL, 0, 2) -FIELD(VTYPE, VSEW, 2, 3) -FIELD(VTYPE, VEDIV, 5, 2) -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) +FIELD(VTYPE, VLMUL, 0, 3) +FIELD(VTYPE, VSEW, 3, 3) +FIELD(VTYPE, VEDIV, 8, 2) +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) =20 struct CPURISCVState { @@ -381,12 +381,14 @@ typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, MEM_IDX, 0, 3) -FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) -FIELD(TB_FLAGS, LMUL, 4, 2) +FIELD(TB_FLAGS, LMUL, 3, 3) FIELD(TB_FLAGS, SEW, 6, 3) -FIELD(TB_FLAGS, VILL, 9, 1) +/* Skip MSTATUS_VS (0x600) bits */ +FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) +FIELD(TB_FLAGS, VILL, 12, 1) +/* Skip MSTATUS_FS (0x6000) bits */ /* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 10, 1) +FIELD(TB_FLAGS, HLSX, 15, 1) =20 bool riscv_cpu_is_32bit(CPURISCVState *env); =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6e1896188c0..75ed94c802b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -60,7 +60,19 @@ typedef struct DisasContext { bool hlsx; /* vector extension */ bool vill; - uint8_t lmul; + /* + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ + int8_t lmul; uint8_t sew; uint16_t vlen; bool vl_eq_vlmax; @@ -853,7 +865,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); - ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); + ctx->lmul =3D sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->cs =3D cs; } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12301e943e6..aa8348ea25a 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -86,9 +86,21 @@ static inline uint32_t vext_vm(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, VM); } =20 -static inline uint32_t vext_lmul(uint32_t desc) +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) { - return FIELD_EX32(simd_data(desc), VDATA, LMUL); + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); } =20 static uint32_t vext_wd(uint32_t desc) --=20 2.17.1