From nobody Wed Nov 19 03:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1614305461; cv=none; d=zohomail.com; s=zohoarc; b=WS5AaJJMB3WqT5+3aCtPgfVobP/AgMRLFOqGlDMMZ/Nlg+tloCpj+VWMIfG79Kem8QctGFYXmvlyCss4FJ8J3c5l3d7UOYmB7mWNvyfVo+RHzWhDsVgQEctVUZTsfypKd8dqqDielyZrK0Py0k4YoqDeekfiBUd6V69No85/4qc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614305461; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=wnZr9dehy8KBl022we1BfN1EVLchy3OF983i88k9Y+g=; b=VRN3slWD1XRJz8IrxbvulsWWtOFFoqfWM0xCL2CznSzrs/Uz2e7te7OJfNIbSG6UrF/2V4vDj30Oqkf2sN3uaAPR2WZ0Y3HUTIti9Gd5pbqTrYnahfGckT6WCHnBIZasikeGCx8VyslY6wn/4Z6Yb/XwZ2D7N5z5q+yo/lNG+2c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614305461308388.48473727709245; Thu, 25 Feb 2021 18:11:01 -0800 (PST) Received: from localhost ([::1]:45954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lFSam-0007PD-8q for importer@patchew.org; Thu, 25 Feb 2021 21:10:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49394) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFSZU-0005rz-3M for qemu-devel@nongnu.org; Thu, 25 Feb 2021 21:09:36 -0500 Received: from mga14.intel.com ([192.55.52.115]:7375) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFSZR-0002ce-F6 for qemu-devel@nongnu.org; Thu, 25 Feb 2021 21:09:35 -0500 Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2021 18:09:28 -0800 Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.166]) by orsmga008.jf.intel.com with ESMTP; 25 Feb 2021 18:09:26 -0800 IronPort-SDR: dYYgzz86QH6tpuN1wOyhRmDXNNMKoFZmVWvI0KcHnKjxiWHP7HJHae8/FA5j3QhPbSIJgUP3Dk Fxijc+8TOHRQ== X-IronPort-AV: E=McAfee;i="6000,8403,9906"; a="185057277" X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="185057277" IronPort-SDR: bjxgzeF6JzUJvY+97ND+UZZ8321fSgbVuxHpTasxMTYoKWPQrp3t/mcZWYUPaCKZYopX/0jmow tZDhYwDD6zgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="404679946" From: Yang Weijiang To: pbonzini@redhat.com, richard.henderson@linaro.org, ehabkost@redhat.com, mtosatti@redhat.com, sean.j.christopherson@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v7 1/6] target/i386: Change XSAVE related feature-word names Date: Fri, 26 Feb 2021 10:20:53 +0800 Message-Id: <20210226022058.24562-2-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20210226022058.24562-1-weijiang.yang@intel.com> References: <20210226022058.24562-1-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=weijiang.yang@intel.com; helo=mga14.intel.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rename XSAVE related feature-words for introducing XSAVES related feature-words. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 24 ++++++++++++------------ target/i386/cpu.h | 4 ++-- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5a8c96072e..89edab4240 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1073,7 +1073,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { .cpuid =3D { .eax =3D 6, .reg =3D R_EAX, }, .tcg_features =3D TCG_6_EAX_FEATURES, }, - [FEAT_XSAVE_COMP_LO] =3D { + [FEAT_XSAVE_XCR0_LO] =3D { .type =3D CPUID_FEATURE_WORD, .cpuid =3D { .eax =3D 0xD, @@ -1086,7 +1086,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_M= ASK | XSTATE_PKRU_MASK, }, - [FEAT_XSAVE_COMP_HI] =3D { + [FEAT_XSAVE_XCR0_HI] =3D { .type =3D CPUID_FEATURE_WORD, .cpuid =3D { .eax =3D 0xD, @@ -1491,8 +1491,8 @@ static inline bool accel_uses_host_cpuid(void) =20 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) { - return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 | - cpu->env.features[FEAT_XSAVE_COMP_LO]; + return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | + cpu->env.features[FEAT_XSAVE_XCR0_LO]; } =20 const char *get_register_name_32(unsigned int reg) @@ -4663,8 +4663,8 @@ static const char *x86_cpu_feature_name(FeatureWord w= , int bitnr) /* XSAVE components are automatically enabled by other features, * so return the original feature name instead */ - if (w =3D=3D FEAT_XSAVE_COMP_LO || w =3D=3D FEAT_XSAVE_COMP_HI) { - int comp =3D (w =3D=3D FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr; + if (w =3D=3D FEAT_XSAVE_XCR0_LO || w =3D=3D FEAT_XSAVE_XCR0_HI) { + int comp =3D (w =3D=3D FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; =20 if (comp < ARRAY_SIZE(x86_ext_save_areas) && x86_ext_save_areas[comp].bits) { @@ -5717,8 +5717,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, =20 if (count =3D=3D 0) { *ecx =3D xsave_area_size(x86_cpu_xsave_components(cpu)); - *eax =3D env->features[FEAT_XSAVE_COMP_LO]; - *edx =3D env->features[FEAT_XSAVE_COMP_HI]; + *eax =3D env->features[FEAT_XSAVE_XCR0_LO]; + *edx =3D env->features[FEAT_XSAVE_XCR0_HI]; /* * The initial value of xcr0 and ebx =3D=3D 0, On host without= kvm * commit 412a3c41(e.g., CentOS 6), the ebx's value always =3D= =3D 0 @@ -6282,8 +6282,8 @@ static void x86_cpu_enable_xsave_components(X86CPU *c= pu) uint64_t mask; =20 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { - env->features[FEAT_XSAVE_COMP_LO] =3D 0; - env->features[FEAT_XSAVE_COMP_HI] =3D 0; + env->features[FEAT_XSAVE_XCR0_LO] =3D 0; + env->features[FEAT_XSAVE_XCR0_HI] =3D 0; return; } =20 @@ -6295,8 +6295,8 @@ static void x86_cpu_enable_xsave_components(X86CPU *c= pu) } } =20 - env->features[FEAT_XSAVE_COMP_LO] =3D mask; - env->features[FEAT_XSAVE_COMP_HI] =3D mask >> 32; + env->features[FEAT_XSAVE_XCR0_LO] =3D mask; + env->features[FEAT_XSAVE_XCR0_HI] =3D mask >> 32; } =20 /***** Steps involved on loading and filtering CPUID data diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 88e8586f8f..52f31335c4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -527,8 +527,8 @@ typedef enum FeatureWord { FEAT_SVM, /* CPUID[8000_000A].EDX */ FEAT_XSAVE, /* CPUID[EAX=3D0xd,ECX=3D1].EAX */ FEAT_6_EAX, /* CPUID[6].EAX */ - FEAT_XSAVE_COMP_LO, /* CPUID[EAX=3D0xd,ECX=3D0].EAX */ - FEAT_XSAVE_COMP_HI, /* CPUID[EAX=3D0xd,ECX=3D0].EDX */ + FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=3D0xd,ECX=3D0].EAX */ + FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=3D0xd,ECX=3D0].EDX */ FEAT_ARCH_CAPABILITIES, FEAT_CORE_CAPABILITY, FEAT_PERF_CAPABILITIES, --=20 2.26.2 From nobody Wed Nov 19 03:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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25 Feb 2021 18:09:30 -0800 Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.166]) by orsmga008.jf.intel.com with ESMTP; 25 Feb 2021 18:09:28 -0800 IronPort-SDR: tEbwVWC6AJXp2KA3bqiBCxkqMaV+TqvevfpFWMxrZsVyqMljkBCuivCTOoq3AYoXvEU+tBll7A l57npRSEyqYA== X-IronPort-AV: E=McAfee;i="6000,8403,9906"; a="185057281" X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="185057281" IronPort-SDR: z8elN4nmMyPkRHVMlzUQRR5Wz+T0BW3LoL+nlkrCvb3JTdz0Vdmjx+5+YsKohwU3UZv90mNwhK cnfRArgsykTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="404679990" From: Yang Weijiang To: pbonzini@redhat.com, richard.henderson@linaro.org, ehabkost@redhat.com, mtosatti@redhat.com, sean.j.christopherson@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v7 2/6] target/i386: Enable XSS feature enumeration for CPUID Date: Fri, 26 Feb 2021 10:20:54 +0800 Message-Id: <20210226022058.24562-3-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20210226022058.24562-1-weijiang.yang@intel.com> References: <20210226022058.24562-1-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=weijiang.yang@intel.com; helo=mga14.intel.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently, CPUID.(EAX=3D0DH,ECX=3D01H) doesn't enumerate features in XSS properly, add the support here. XCR0 bits indicate user-mode XSAVE components, and XSS bits indicate supervisor-mode XSAVE components. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++----- target/i386/cpu.h | 12 ++++++++++++ 2 files changed, 55 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 89edab4240..f3923988ed 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1058,6 +1058,24 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, .tcg_features =3D TCG_XSAVE_FEATURES, }, + [FEAT_XSAVE_XSS_LO] =3D { + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { + .eax =3D 0xD, + .needs_ecx =3D true, + .ecx =3D 1, + .reg =3D R_ECX, + }, + }, + [FEAT_XSAVE_XSS_HI] =3D { + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { + .eax =3D 0xD, + .needs_ecx =3D true, + .ecx =3D 1, + .reg =3D R_EDX + }, + }, [FEAT_6_EAX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -1478,6 +1496,9 @@ static uint32_t xsave_area_size(uint64_t mask) for (i =3D 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; if ((mask >> i) & 1) { + if (i >=3D 2 && !esa->offset) { + continue; + } ret =3D MAX(ret, esa->offset + esa->size); } } @@ -1489,12 +1510,18 @@ static inline bool accel_uses_host_cpuid(void) return kvm_enabled() || hvf_enabled(); } =20 -static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) +static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) { return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | cpu->env.features[FEAT_XSAVE_XCR0_LO]; } =20 +static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) +{ + return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | + cpu->env.features[FEAT_XSAVE_XSS_LO]; +} + const char *get_register_name_32(unsigned int reg) { if (reg >=3D CPU_NB_REGS32) { @@ -5716,7 +5743,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } =20 if (count =3D=3D 0) { - *ecx =3D xsave_area_size(x86_cpu_xsave_components(cpu)); + *ecx =3D xsave_area_size(x86_cpu_xsave_xcr0_components(cpu)); *eax =3D env->features[FEAT_XSAVE_XCR0_LO]; *edx =3D env->features[FEAT_XSAVE_XCR0_HI]; /* @@ -5728,11 +5755,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *ebx =3D kvm_enabled() ? *ecx : xsave_area_size(env->xcr0); } else if (count =3D=3D 1) { *eax =3D env->features[FEAT_XSAVE]; + *ecx =3D env->features[FEAT_XSAVE_XSS_LO]; + *edx =3D env->features[FEAT_XSAVE_XSS_HI]; } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { - if ((x86_cpu_xsave_components(cpu) >> count) & 1) { - const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; + const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; + if ((x86_cpu_xsave_xcr0_components(cpu) >> count) & 1) { *eax =3D esa->size; *ebx =3D esa->offset; + } else if ((x86_cpu_xsave_xss_components(cpu) >> count) & 1) { + *eax =3D esa->size; + *ebx =3D 0; + *ecx =3D 1; } } break; @@ -6059,6 +6092,9 @@ static void x86_cpu_reset(DeviceState *dev) } for (i =3D 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; + if (!esa->offset) { + continue; + } if (env->features[esa->feature] & esa->bits) { xcr0 |=3D 1ull << i; } @@ -6295,8 +6331,10 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) } } =20 - env->features[FEAT_XSAVE_XCR0_LO] =3D mask; + env->features[FEAT_XSAVE_XCR0_LO] =3D mask & CPUID_XSTATE_XCR0_MASK; env->features[FEAT_XSAVE_XCR0_HI] =3D mask >> 32; + env->features[FEAT_XSAVE_XSS_LO] =3D mask & CPUID_XSTATE_XSS_MASK; + env->features[FEAT_XSAVE_XSS_HI] =3D mask >> 32; } =20 /***** Steps involved on loading and filtering CPUID data diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 52f31335c4..8aeaa8869a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -504,6 +504,16 @@ typedef enum X86Seg { #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) =20 +/* CPUID feature bits available in XCR0 */ +#define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ + XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \ + XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |= \ + XSTATE_ZMM_Hi256_MASK | \ + XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK) + +/* CPUID feature bits available in XSS */ +#define CPUID_XSTATE_XSS_MASK 0 + /* CPUID feature words */ typedef enum FeatureWord { FEAT_1_EDX, /* CPUID[1].EDX */ @@ -541,6 +551,8 @@ typedef enum FeatureWord { FEAT_VMX_EPT_VPID_CAPS, FEAT_VMX_BASIC, FEAT_VMX_VMFUNC, + FEAT_XSAVE_XSS_LO, /* CPUID[EAX=3D0xd,ECX=3D1].ECX */ + FEAT_XSAVE_XSS_HI, /* CPUID[EAX=3D0xd,ECX=3D1].EDX */ FEATURE_WORDS, } FeatureWord; =20 --=20 2.26.2 From nobody Wed Nov 19 03:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1614305462; cv=none; d=zohomail.com; s=zohoarc; b=mK4cgANxMZKsINmVadAiXusUtX2lNi/VYXrKwBlyD0WAMDNk972gcpFMC97fkX+VsSLg4o3km4Kc2yQ/4yDlJgxhcjtWSn2R377AsP6bNYi3vxqyTSkB0P0cj292jH/9NedT4y0R17eEZdqpLNbTWqv2fnqvA/cXI373Iol2KgM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614305462; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=M1Rx5nAFS3WtVks9DiLvvgeXpW+cdZM4KTMIgJ4GcHI=; b=ZLRV9IVrsxLpZ757DhOou9LFaq6/HpjjM4uGc8yPZLdpEgCRV88VcVJBQ7Y4aupbKIsUIrneGF0161nrXzTkZYWVZlEC8I+1TjpmjBnUFxgTsUyzWx/yF2ZPUVoOZFyemmzbeSi7lYJUpnXHLYi2RQ1XcSqf6gjkM7hYbawV0YI= ARC-Authentication-Results: i=1; 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Thu, 25 Feb 2021 21:09:38 -0500 Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2021 18:09:33 -0800 Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.166]) by orsmga008.jf.intel.com with ESMTP; 25 Feb 2021 18:09:31 -0800 IronPort-SDR: bGgG9aAIsVolAXPFHWeSZ+vRPPSQq0HLOyU+Hzyeh30j7jnsQU5xZqXAuFMuq6V6I4mkxtnTc+ X/caTNLhWPqw== X-IronPort-AV: E=McAfee;i="6000,8403,9906"; a="185057288" X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="185057288" IronPort-SDR: UeD3u/olY9BJc1HeewxWiOGPguAkQ3LHsi5ShKkODOggqjxM7pppYq9G7ej4IeoZfdTLgNHyM7 JC0VJu6A8ugQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="404680036" From: Yang Weijiang To: pbonzini@redhat.com, richard.henderson@linaro.org, ehabkost@redhat.com, mtosatti@redhat.com, sean.j.christopherson@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v7 3/6] target/i386: Enable CET components support for XSAVES Date: Fri, 26 Feb 2021 10:20:55 +0800 Message-Id: <20210226022058.24562-4-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20210226022058.24562-1-weijiang.yang@intel.com> References: <20210226022058.24562-1-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=weijiang.yang@intel.com; helo=mga14.intel.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CET Shadow Stack(SHSTK) and Indirect Branch Tracking(IBT) are enumerated via CPUID.(EAX=3D07H,ECX=3D0H):ECX[bit 7] and EDX[bit 20] respectively. Two CET bits (bit 11 and 12) are defined in MSR_IA32_XSS for XSAVES. They correspond to CET states in user and supervisor mode respectively. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 35 +++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 23 ++++++++++++++++++++++- 2 files changed, 57 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f3923988ed..ef786b920e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1060,6 +1060,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, [FEAT_XSAVE_XSS_LO] =3D { .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "cet-u", + "cet-s", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, .cpuid =3D { .eax =3D 0xD, .needs_ecx =3D true, @@ -1486,6 +1496,14 @@ static const ExtSaveArea x86_ext_save_areas[] =3D { { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, .offset =3D offsetof(X86XSaveArea, pkru_state), .size =3D sizeof(XSavePKRU) }, + [XSTATE_CET_U_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + .offset =3D 0, + .size =3D sizeof(XSavesCETU) }, + [XSTATE_CET_S_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + .offset =3D 0, + .size =3D sizeof(XSavesCETS) }, }; =20 static uint32_t xsave_area_size(uint64_t mask) @@ -6329,6 +6347,23 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) if (env->features[esa->feature] & esa->bits) { mask |=3D (1ULL << i); } + + /* + * Both CET SHSTK and IBT feature requires XSAVES support, but two + * features can be controlled independently by kernel, and we only + * have one correlated bit set in x86_ext_save_areas, so if either + * of two features is enabled, we set the XSAVES support bit to ma= ke + * the enabled feature work. + */ + if (i =3D=3D XSTATE_CET_U_BIT || i =3D=3D XSTATE_CET_S_BIT) { + uint64_t ecx =3D env->features[FEAT_7_0_ECX]; + uint64_t edx =3D env->features[FEAT_7_0_EDX]; + + if ((ecx & CPUID_7_0_ECX_CET_SHSTK) || + (edx & CPUID_7_0_EDX_CET_IBT)) { + mask |=3D (1ULL << i); + } + } } =20 env->features[FEAT_XSAVE_XCR0_LO] =3D mask & CPUID_XSTATE_XCR0_MASK; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8aeaa8869a..a43fb6d597 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -493,6 +493,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_CET_U_BIT 11 +#define XSTATE_CET_S_BIT 12 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -503,6 +505,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT) +#define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT) =20 /* CPUID feature bits available in XCR0 */ #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ @@ -512,7 +516,7 @@ typedef enum X86Seg { XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK) =20 /* CPUID feature bits available in XSS */ -#define CPUID_XSTATE_XSS_MASK 0 +#define CPUID_XSTATE_XSS_MASK (XSTATE_CET_U_MASK) =20 /* CPUID feature words */ typedef enum FeatureWord { @@ -760,6 +764,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_WAITPKG (1U << 5) /* Additional AVX-512 Vector Byte Manipulation Instruction */ #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) +/* CET SHSTK feature */ +#define CPUID_7_0_ECX_CET_SHSTK (1U << 7) /* Galois Field New Instructions */ #define CPUID_7_0_ECX_GFNI (1U << 8) /* Vector AES Instructions */ @@ -795,6 +801,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_SERIALIZE (1U << 14) /* TSX Suspend Load Address Tracking instruction */ #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) +/* CET IBT feature */ +#define CPUID_7_0_EDX_CET_IBT (1U << 20) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ @@ -1285,6 +1293,19 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +/* Ext. save area 11: User mode CET state */ +typedef struct XSavesCETU { + uint64_t u_cet; + uint64_t user_ssp; +} XSavesCETU; + +/* Ext. save area 12: Supervisor mode CET state */ +typedef struct XSavesCETS { + uint64_t kernel_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; +} XSavesCETS; + typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; X86XSaveHeader header; --=20 2.26.2 From nobody Wed Nov 19 03:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1614305728; cv=none; d=zohomail.com; s=zohoarc; b=JE/lYy15ALQorSPhIK7cFbLjigz3ABTkPbQcFE58KXHJe71hQ2vEUZB8gpgwxuz0bflu58WND22op+AXXAJTOIw9DXjHSmC/6JiWM3uH/J+b5sKtKlArKHm1CO1tgvTNmlHbblKykUSw5sq+fPTIn9ooreNhmTCmfg1WoyTX+yY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614305728; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=vwoeVGo4Xdd4FobZWsqcGL6L2/vanhSuGXI4ZgwA62I=; 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Thu, 25 Feb 2021 21:09:39 -0500 Received: from mga14.intel.com ([192.55.52.115]:7370) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFSZV-0002bP-4L for qemu-devel@nongnu.org; Thu, 25 Feb 2021 21:09:38 -0500 Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2021 18:09:35 -0800 Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.166]) by orsmga008.jf.intel.com with ESMTP; 25 Feb 2021 18:09:33 -0800 IronPort-SDR: KysJvGRAiZUiWTEexJNI34YvrJkI854C3QHBWdzI+ywlhqdL4QWPfPJXW8FRIDNS+2m5pcbci0 RSq+Lo4kZ4jg== X-IronPort-AV: E=McAfee;i="6000,8403,9906"; a="185057298" X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="185057298" IronPort-SDR: JDHpce75e1uFfvdHv/L9hyXSWvhZ3ObaTrnDgG90MBW4X34CoWaT1C2iYeQcv8QdMlp4vR/Dw+ Zk84rCAswIgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="404680085" From: Yang Weijiang To: pbonzini@redhat.com, richard.henderson@linaro.org, ehabkost@redhat.com, mtosatti@redhat.com, sean.j.christopherson@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v7 4/6] target/i386: Add user-space MSR access interface for CET Date: Fri, 26 Feb 2021 10:20:56 +0800 Message-Id: <20210226022058.24562-5-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20210226022058.24562-1-weijiang.yang@intel.com> References: <20210226022058.24562-1-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=weijiang.yang@intel.com; helo=mga14.intel.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CET states are divided into user-mode and supervisor-mode states, MSR_KVM_GUEST_SSP holds current SHSTK pointer in use, MSR_IA32_U_CET and MSR_IA32_PL3_SSP are for user-mode states, others are for supervisor-mode states. Expose access according to current CET supported bits in CPUID and XSS. Signed-off-by: Yang Weijiang --- target/i386/cpu.h | 18 ++++++++++++ target/i386/kvm.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a43fb6d597..83628e823c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -484,6 +484,15 @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 =20 +#define MSR_IA32_U_CET 0x000006a0 +#define MSR_IA32_S_CET 0x000006a2 +#define MSR_IA32_PL0_SSP 0x000006a4 +#define MSR_IA32_PL1_SSP 0x000006a5 +#define MSR_IA32_PL2_SSP 0x000006a6 +#define MSR_IA32_PL3_SSP 0x000006a7 +#define MSR_IA32_SSP_TBL 0x000006a8 +#define MSR_KVM_GUEST_SSP 0x4b564d08 + #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 #define XSTATE_YMM_BIT 2 @@ -1584,6 +1593,15 @@ typedef struct CPUX86State { =20 uintptr_t retaddr; =20 + uint64_t u_cet; + uint64_t s_cet; + uint64_t pl0_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; + uint64_t pl3_ssp; + uint64_t ssp_tbl; + uint64_t guest_ssp; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index a2934dda02..67d5203d19 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -2992,6 +2992,30 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } } =20 + if (((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) && + (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_U_MASK)) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, env->u_cet); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, env->pl3_ssp); + } + + if (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_S_MASK) { + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, env->pl1_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, env->pl2_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL, env->ssp_tbl); + } + + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, env->s_cet); + } + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + (env->features[FEAT_XSAVE_XSS_LO] & (XSTATE_CET_U_MASK | + XSTATE_CET_S_MASK))) { + kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, env->guest_ssp); + } + return kvm_buf_set_msrs(cpu); } =20 @@ -3311,6 +3335,30 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 + if (((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) && + (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_U_MASK)) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, 0); + } + + if (env->features[FEAT_XSAVE_XSS_LO] & XSTATE_CET_S_MASK) { + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL, 0); + } + + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, 0); + } + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + (env->features[FEAT_XSAVE_XSS_LO] & (XSTATE_CET_U_MASK | + XSTATE_CET_S_MASK))) { + kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, 0); + } + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -3597,6 +3645,30 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] =3D msrs[i]= .data; break; + case MSR_IA32_U_CET: + env->u_cet =3D msrs[i].data; + break; + case MSR_IA32_S_CET: + env->s_cet =3D msrs[i].data; + break; + case MSR_IA32_PL0_SSP: + env->pl0_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL1_SSP: + env->pl1_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL2_SSP: + env->pl2_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL3_SSP: + env->pl3_ssp =3D msrs[i].data; + break; + case MSR_IA32_SSP_TBL: + env->ssp_tbl =3D msrs[i].data; + break; + case MSR_KVM_GUEST_SSP: + env->guest_ssp =3D msrs[i].data; + break; } } =20 --=20 2.26.2 From nobody Wed Nov 19 03:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1614305601; 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Thu, 25 Feb 2021 18:13:21 -0800 (PST) Received: from localhost ([::1]:52950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lFSd4-0001vd-PU for importer@patchew.org; Thu, 25 Feb 2021 21:13:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFSZY-0005vG-Au for qemu-devel@nongnu.org; Thu, 25 Feb 2021 21:09:40 -0500 Received: from mga14.intel.com ([192.55.52.115]:7378) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFSZW-0002dW-HK for qemu-devel@nongnu.org; Thu, 25 Feb 2021 21:09:40 -0500 Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2021 18:09:37 -0800 Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.166]) by orsmga008.jf.intel.com with ESMTP; 25 Feb 2021 18:09:35 -0800 IronPort-SDR: mSUvHwg6JspQB6xwqOSUrhTNvSvOw3xk4/uxDIsWvV7qT+M6gi2pgtRAAPgbOeZY599gv9BREQ q2cK2osp3QEw== X-IronPort-AV: E=McAfee;i="6000,8403,9906"; a="185057308" X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="185057308" IronPort-SDR: lOD7m08hreyDN3buUMqVk4jPc3TcXvnKhAgbx+9tjUrVLe8+GQvtN10CsNHwhmQy4F2jcVwBXm qTuYmv4OfipQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="404680139" From: Yang Weijiang To: pbonzini@redhat.com, richard.henderson@linaro.org, ehabkost@redhat.com, mtosatti@redhat.com, sean.j.christopherson@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v7 5/6] target/i386: Add CET state support for guest migration Date: Fri, 26 Feb 2021 10:20:57 +0800 Message-Id: <20210226022058.24562-6-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20210226022058.24562-1-weijiang.yang@intel.com> References: <20210226022058.24562-1-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=weijiang.yang@intel.com; helo=mga14.intel.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Save the MSRs being used on source machine and restore them on destination machine. Signed-off-by: Yang Weijiang --- target/i386/machine.c | 161 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 161 insertions(+) diff --git a/target/i386/machine.c b/target/i386/machine.c index 233e46bb70..c76a7caeec 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -980,6 +980,159 @@ static const VMStateDescription vmstate_umwait =3D { } }; =20 +static bool u_cet_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->u_cet !=3D 0; +} + +static const VMStateDescription vmstate_u_cet =3D { + .name =3D "cpu/u_cet", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D u_cet_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.u_cet, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool s_cet_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->s_cet !=3D 0; +} + +static const VMStateDescription vmstate_s_cet =3D { + .name =3D "cpu/s_cet", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D s_cet_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.s_cet, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl0_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl0_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl0_ssp =3D { + .name =3D "cpu/pl0_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl0_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl0_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl1_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl1_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl1_ssp =3D { + .name =3D "cpu/pl1_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl1_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl1_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl2_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl2_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl2_ssp =3D { + .name =3D "cpu/pl2_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl2_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl2_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + + +static bool pl3_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->pl3_ssp !=3D 0; +} + +static const VMStateDescription vmstate_pl3_ssp =3D { + .name =3D "cpu/pl3_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pl3_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.pl3_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool ssp_tbl_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->ssp_tbl !=3D 0; +} + +static const VMStateDescription vmstate_ssp_tbl =3D { + .name =3D "cpu/ssp_tbl", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ssp_tbl_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.ssp_tbl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool guest_ssp_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->guest_ssp !=3D 0; +} + +static const VMStateDescription vmstate_guest_ssp =3D { + .name =3D "cpu/guest_ssp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D guest_ssp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.guest_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + #ifdef TARGET_X86_64 static bool pkru_needed(void *opaque) { @@ -1495,6 +1648,14 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_nested_state, #endif &vmstate_msr_tsx_ctrl, + &vmstate_u_cet, + &vmstate_s_cet, + &vmstate_pl0_ssp, + &vmstate_pl1_ssp, + &vmstate_pl2_ssp, + &vmstate_pl3_ssp, + &vmstate_ssp_tbl, + &vmstate_guest_ssp, NULL } }; --=20 2.26.2 From nobody Wed Nov 19 03:02:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1614305463; cv=none; d=zohomail.com; s=zohoarc; b=dNiZ4QVzMqd2T9re0LXhLeYlPgjxcXGYnBmss4PcptlMFkmt3sku5NSMv0BUhkEx5No/UOvxwyPCBpKMj16Qerjoh01BDu9wyHf2A/4n2+oYGrC6NthonKayfkXsr/F/GmTZ/6JQFVUVZXv1ttw41FPMStLOIUKP2iGFtNa/y3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Thu, 25 Feb 2021 21:09:42 -0500 Received: from mga14.intel.com ([192.55.52.115]:7378) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFSZY-0002dW-Q8 for qemu-devel@nongnu.org; Thu, 25 Feb 2021 21:09:42 -0500 Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2021 18:09:40 -0800 Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.166]) by orsmga008.jf.intel.com with ESMTP; 25 Feb 2021 18:09:37 -0800 IronPort-SDR: afjBJSzs5Hw7SIdwBEYNI5Kn05wJ8IlBnzuBQ4JFMUPAYDU9v3GaUdyS2rqAZE3Ye6k9s0arES 1PJMiOsqXIBA== X-IronPort-AV: E=McAfee;i="6000,8403,9906"; a="185057319" X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="185057319" IronPort-SDR: wStmTtDX93fdampCzql84sre2j4URVf8d/sD4BMi2z7RCR0l6gO3bB84MWA3sTVRSV0/SDqp3v if4FVIWtiHRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,207,1610438400"; d="scan'208";a="404680191" From: Yang Weijiang To: pbonzini@redhat.com, richard.henderson@linaro.org, ehabkost@redhat.com, mtosatti@redhat.com, sean.j.christopherson@intel.com, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v7 6/6] target/i386: Advise CET bits in CPU/MSR feature words Date: Fri, 26 Feb 2021 10:20:58 +0800 Message-Id: <20210226022058.24562-7-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20210226022058.24562-1-weijiang.yang@intel.com> References: <20210226022058.24562-1-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=weijiang.yang@intel.com; helo=mga14.intel.com X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CET SHSTK and IBT feature are enumerated via CPUID.(EAX=3D07H,ECX=3D0H):ECX= [bit 7] and EDX[bit 20]. CET state load/restore at vmentry/vmexit are enabled via VMX_ENTRY_CTLS[bit 20] and VMX_EXIT_CTLS[bit 28]. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ef786b920e..d1dcc7210d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -954,7 +954,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, + NULL /* ospke */, "waitpkg", "avx512vbmi2", "shstk", "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, @@ -977,7 +977,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, "serialize", NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, - NULL, NULL, NULL, NULL, + "ibt", NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", }, @@ -1239,7 +1239,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { "vmx-exit-save-efer", "vmx-exit-load-efer", "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, - NULL, NULL, NULL, NULL, + "vmx-exit-save-cet-ctl", NULL, NULL, NULL, }, .msr =3D { .index =3D MSR_IA32_VMX_TRUE_EXIT_CTLS, @@ -1254,7 +1254,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { NULL, "vmx-entry-ia32e-mode", NULL, NULL, NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat",= "vmx-entry-load-efer", "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NUL= L, - NULL, NULL, NULL, NULL, + "vmx-entry-load-cet-ctl", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, --=20 2.26.2