From nobody Sat Feb 7 06:03:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1614266598; cv=none; d=zohomail.com; s=zohoarc; b=FC1nQI/6HHk1aYzsB6UigpcQrZkrTRIHXx+Z/aFX+0INhtmAGWb29z9pTQq2uh2L6bAw4smD36o59WYDyD8cLVOS1cfJgAJB9WFJUJQdJ1yjfIupdPqLHgRFc2exUWbotmofaKHLn3c5zblFQAc2Slr9Pp50uRvGOvrJjyuNaQQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614266598; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=kvCrBq+qiD1jQK8XJ31q4EtUpfuT9FrJS1SbT9Hm7O0=; b=kFw1Pfy4qzlBd+cNpXtBk/wFIuOqFuBCHZIrMH6FwOiYbyzKyGBPV48oxD69/mlcZVMiHqAllC4o37q5hE/s6zpATgb/JZ1w9wz4XIiQjqNUP/bQCpb22098tbjup7sydXkh/k6luDbYMYa0NI4ck+1zy8EoacCFnN9sRql7Csg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1614266598052957.5283577237979; Thu, 25 Feb 2021 07:23:18 -0800 (PST) Received: from localhost ([::1]:35022 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lFIU0-0007Ua-O8 for importer@patchew.org; Thu, 25 Feb 2021 10:23:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFIQO-0002KW-9q for qemu-devel@nongnu.org; Thu, 25 Feb 2021 10:19:32 -0500 Received: from rev.ng ([5.9.113.41]:50865) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFIQJ-0001D0-4I for qemu-devel@nongnu.org; Thu, 25 Feb 2021 10:19:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=kvCrBq+qiD1jQK8XJ31q4EtUpfuT9FrJS1SbT9Hm7O0=; b=OdhDmKV/wupXcj2Lhm9orUadtG 2YDcGQcigwCKbjFtztbGOjjp09b5WHVwEL6p3Afltk/sAlWxPblX9qyAYuzWNJsJ5/Fog6PRXiMuh 1ppl75RtdDfztUP8Ijqr3vsMOeHQNoXv5i3ZIH8loohj6QiHHIH3nWm3ubzOpNCbAMG0=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v2 04/10] target/hexagon: introduce new helper functions Date: Thu, 25 Feb 2021 16:18:50 +0100 Message-Id: <20210225151856.3284701-5-ale.qemu@rev.ng> In-Reply-To: <20210225151856.3284701-1-ale.qemu@rev.ng> References: <20210225151856.3284701-1-ale.qemu@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) From: Niccol=C3=B2 Izzo These helpers will be employed by the idef-parser generated code. Signed-off-by: Alessandro Di Federico Signed-off-by: Niccol=C3=B2 Izzo --- target/hexagon/genptr.c | 227 +++++++++++++++++++++++++++++++++++++++- target/hexagon/genptr.h | 19 ++++ target/hexagon/macros.h | 2 +- 3 files changed, 245 insertions(+), 3 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 97de669f38..78cda032db 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -40,7 +40,8 @@ TCGv gen_read_preg(TCGv pred, uint8_t num) return pred; } =20 -static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int sl= ot) +static inline void gen_log_predicated_reg_write(int rnum, TCGv val, + unsigned slot) { TCGv one =3D tcg_const_tl(1); TCGv zero =3D tcg_const_tl(0); @@ -69,7 +70,8 @@ void gen_log_reg_write(int rnum, TCGv val) #endif } =20 -static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int = slot) +static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, + unsigned slot) { TCGv val32 =3D tcg_temp_new(); TCGv one =3D tcg_const_tl(1); @@ -334,5 +336,226 @@ static inline void gen_store_conditional8(CPUHexagonS= tate *env, tcg_gen_movi_tl(hex_llsc_addr, ~0); } =20 +void gen_fbrev(TCGv result, TCGv src) +{ + TCGv lo =3D tcg_temp_new(); + TCGv tmp1 =3D tcg_temp_new(); + TCGv tmp2 =3D tcg_temp_new(); + + /* Bit reversal of low 16 bits */ + tcg_gen_extract_tl(lo, src, 0, 16); + tcg_gen_andi_tl(tmp1, lo, 0xaaaa); + tcg_gen_shri_tl(tmp1, tmp1, 1); + tcg_gen_andi_tl(tmp2, lo, 0x5555); + tcg_gen_shli_tl(tmp2, tmp2, 1); + tcg_gen_or_tl(lo, tmp1, tmp2); + tcg_gen_andi_tl(tmp1, lo, 0xcccc); + tcg_gen_shri_tl(tmp1, tmp1, 2); + tcg_gen_andi_tl(tmp2, lo, 0x3333); + tcg_gen_shli_tl(tmp2, tmp2, 2); + tcg_gen_or_tl(lo, tmp1, tmp2); + tcg_gen_andi_tl(tmp1, lo, 0xf0f0); + tcg_gen_shri_tl(tmp1, tmp1, 4); + tcg_gen_andi_tl(tmp2, lo, 0x0f0f); + tcg_gen_shli_tl(tmp2, tmp2, 4); + tcg_gen_or_tl(lo, tmp1, tmp2); + tcg_gen_bswap16_tl(lo, lo); + + /* Final tweaks */ + tcg_gen_extract_tl(result, src, 16, 16); + tcg_gen_or_tl(result, result, lo); + + tcg_temp_free(lo); + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); +} + +TCGv gen_set_bit(tcg_target_long i, TCGv result, TCGv src) +{ + TCGv mask =3D tcg_const_tl(~(1 << i)); + TCGv bit =3D tcg_temp_new(); + tcg_gen_shli_tl(bit, src, i); + tcg_gen_and_tl(result, result, mask); + tcg_gen_or_tl(result, result, bit); + tcg_temp_free(mask); + tcg_temp_free(bit); + + return result; +} + +void gen_cancel(tcg_target_ulong slot) +{ + TCGv one =3D tcg_const_tl(1); + tcg_gen_deposit_tl(hex_slot_cancelled, hex_slot_cancelled, one, slot, = 1); + tcg_temp_free(one); +} + +void gen_store32(TCGv vaddr, TCGv src, tcg_target_long width, unsigned slo= t) +{ + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], width); + tcg_gen_mov_tl(hex_store_val32[slot], src); +} + +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot) +{ + gen_store32(vaddr, src, 1, slot); + ctx->store_width[slot] =3D 1; +} + +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot) +{ + gen_store32(vaddr, src, 2, slot); + ctx->store_width[slot] =3D 2; +} + +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot) +{ + gen_store32(vaddr, src, 4, slot); + ctx->store_width[slot] =3D 4; +} + + +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *= ctx, + unsigned slot) +{ + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], 8); + tcg_gen_mov_i64(hex_store_val64[slot], src); + ctx->store_width[slot] =3D 8; +} + +void gen_set_usr_field(int field, TCGv val) +{ + tcg_gen_deposit_tl(hex_gpr[HEX_REG_USR], hex_gpr[HEX_REG_USR], val, + reg_field_info[field].offset, + reg_field_info[field].width); +} + +void gen_set_usr_fieldi(int field, int x) +{ + TCGv val =3D tcg_const_tl(x); + gen_set_usr_field(field, val); + tcg_temp_free(val); +} + +void gen_write_new_pc(TCGv addr) +{ + /* If there are multiple branches in a packet, ignore the second one */ + TCGv zero =3D tcg_const_tl(0); + tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, hex_branch_taken, zero, + hex_next_PC, addr); + tcg_gen_movi_tl(hex_branch_taken, 1); + tcg_temp_free(zero); +} + +void gen_sat_i32(TCGv dest, TCGv source, int width, bool set_overflow) +{ + TCGv max_val =3D tcg_const_i32((1 << (width - 1)) - 1); + TCGv min_val =3D tcg_const_i32(-(1 << (width - 1))); + tcg_gen_movcond_i32(TCG_COND_GT, dest, source, max_val, max_val, sourc= e); + tcg_gen_movcond_i32(TCG_COND_LT, dest, source, min_val, min_val, dest); + /* Set Overflow Bit */ + if (set_overflow) { + TCGv ovf =3D tcg_temp_new(); + TCGv one =3D tcg_const_i32(1); + GET_USR_FIELD(USR_OVF, ovf); + tcg_gen_movcond_i32(TCG_COND_GT, ovf, source, max_val, one, ovf); + tcg_gen_movcond_i32(TCG_COND_LT, ovf, source, min_val, one, ovf); + SET_USR_FIELD(USR_OVF, ovf); + tcg_temp_free_i32(ovf); + tcg_temp_free_i32(one); + } + tcg_temp_free_i32(max_val); + tcg_temp_free_i32(min_val); +} + +void gen_satu_i32(TCGv dest, TCGv source, int width, bool set_overflow) +{ + TCGv max_val =3D tcg_const_i32((1 << width) - 1); + tcg_gen_movcond_i32(TCG_COND_GTU, dest, source, max_val, max_val, sour= ce); + TCGv_i32 zero =3D tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_LT, dest, source, zero, zero, dest); + /* Set Overflow Bit */ + if (set_overflow) { + TCGv ovf =3D tcg_temp_new(); + TCGv one =3D tcg_const_i32(1); + GET_USR_FIELD(USR_OVF, ovf); + tcg_gen_movcond_i32(TCG_COND_GTU, ovf, source, max_val, one, ovf); + SET_USR_FIELD(USR_OVF, ovf); + tcg_temp_free_i32(ovf); + tcg_temp_free_i32(one); + } + tcg_temp_free_i32(max_val); + tcg_temp_free_i32(zero); +} + +void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width, bool set_overf= low) +{ + TCGv_i64 max_val =3D tcg_const_i64((1 << (width - 1)) - 1); + TCGv_i64 min_val =3D tcg_const_i64(-(1 << (width - 1))); + tcg_gen_movcond_i64(TCG_COND_GT, dest, source, max_val, max_val, sourc= e); + tcg_gen_movcond_i64(TCG_COND_LT, dest, source, min_val, min_val, dest); + /* Set Overflow Bit */ + if (set_overflow) { + TCGv ovf =3D tcg_temp_new(); + TCGv_i64 ovf_ext =3D tcg_temp_new_i64(); + TCGv_i64 one =3D tcg_const_i64(1); + GET_USR_FIELD(USR_OVF, ovf); + tcg_gen_ext_i32_i64(ovf_ext, ovf); + tcg_gen_movcond_i64(TCG_COND_GT, + ovf_ext, + source, + max_val, + one, + ovf_ext); + tcg_gen_movcond_i64(TCG_COND_LT, + ovf_ext, + source, + min_val, + one, + ovf_ext); + tcg_gen_trunc_i64_tl(ovf, ovf_ext); + SET_USR_FIELD(USR_OVF, ovf); + tcg_temp_free_i32(ovf); + tcg_temp_free_i64(ovf_ext); + tcg_temp_free_i64(one); + } + tcg_temp_free_i64(max_val); + tcg_temp_free_i64(min_val); +} + +void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width, bool set_over= flow) +{ + TCGv_i64 max_val =3D tcg_const_i64((1 << width) - 1); + tcg_gen_movcond_i64(TCG_COND_GTU, dest, source, max_val, max_val, sour= ce); + TCGv_i64 zero =3D tcg_const_i64(0); + tcg_gen_movcond_i64(TCG_COND_LT, dest, source, zero, zero, dest); + /* Set Overflow Bit */ + if (set_overflow) { + TCGv ovf =3D tcg_temp_new(); + TCGv_i64 ovf_ext =3D tcg_temp_new_i64(); + TCGv_i64 one =3D tcg_const_i64(1); + GET_USR_FIELD(USR_OVF, ovf); + tcg_gen_ext_i32_i64(ovf_ext, ovf); + tcg_gen_movcond_i64(TCG_COND_GTU, + ovf_ext, + source, + max_val, + one, + ovf_ext); + tcg_gen_trunc_i64_tl(ovf, ovf_ext); + SET_USR_FIELD(USR_OVF, ovf); + tcg_temp_free_i32(ovf); + tcg_temp_free_i64(ovf_ext); + tcg_temp_free_i64(one); + } + tcg_temp_free_i64(max_val); + tcg_temp_free_i64(zero); +} + #include "tcg_funcs_generated.c.inc" #include "tcg_func_table_generated.c.inc" diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 0bfa99b463..86f5d5222e 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -28,5 +28,24 @@ TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); void gen_log_reg_write(int rnum, TCGv val); void gen_log_pred_write(int pnum, TCGv val); +void gen_fbrev(TCGv result, TCGv src); +void gen_cancel(tcg_target_ulong slot); +TCGv gen_set_bit(tcg_target_long i, TCGv result, TCGv src); +void gen_store32(TCGv vaddr, TCGv src, tcg_target_long width, unsigned slo= t); +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot); +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot); +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot); +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *= ctx, + unsigned slot); +void gen_set_usr_field(int field, TCGv val); +void gen_set_usr_fieldi(int field, int x); +void gen_write_new_pc(TCGv addr); +void gen_sat_i32(TCGv dest, TCGv source, int width, bool set_overflow); +void gen_satu_i32(TCGv dest, TCGv source, int width, bool set_overflow); +void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width, bool set_overf= low); +void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width, bool set_over= flow); =20 #endif diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 78c4efb5cb..7b6556b07b 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -154,7 +154,7 @@ #define LOAD_CANCEL(EA) do { CANCEL; } while (0) =20 #ifdef QEMU_GENERATE -static inline void gen_pred_cancel(TCGv pred, int slot_num) +static inline void gen_pred_cancel(TCGv pred, tcg_target_ulong slot_num) { TCGv slot_mask =3D tcg_const_tl(1 << slot_num); TCGv tmp =3D tcg_temp_new(); --=20 2.30.1