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bh=jVKKWvVoOg+XYg6v0Z6BnfNXsvRHogwcr1q+jcDS2Rw=; b=IB3hQbqgBEdv0bBzcXJe4b/wJS7q4gmc2MkYmuRtqaiXrFEpKtoPthqZfm6x0rJyGGYToI p3u4QACPc5L2xqVqODz8ajgzNnr/1WohucdwBoFAnMb5HD8ZQRtY6UcDb9iuouGYs7BDGH oL3swg/mzvFTsJy/mecm9pWJHZIx2Ss= X-MC-Unique: tV2MiKr6N9erAjz57tsb9Q-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, jean-philippe@linaro.org, peterx@redhat.com, jasowang@redhat.com, pbonzini@redhat.com Subject: [PATCH v2 1/7] intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate Date: Thu, 25 Feb 2021 10:14:29 +0100 Message-Id: <20210225091435.644762-2-eric.auger@redhat.com> In-Reply-To: <20210225091435.644762-1-eric.auger@redhat.com> References: <20210225091435.644762-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.205.24.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: vivek.gautam@arm.com, shameerali.kolothum.thodi@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) With -Werror=3Dmaybe-uninitialized configuration we get ../hw/i386/intel_iommu.c: In function =E2=80=98vtd_context_device_invalidat= e=E2=80=99: ../hw/i386/intel_iommu.c:1888:10: error: =E2=80=98mask=E2=80=99 may be used uninitialized in this function [-Werror=3Dmaybe-uninitialized] 1888 | mask =3D ~mask; | ~~~~~^~~~~~~ Add a g_assert_not_reached() to avoid the error. Signed-off-by: Eric Auger Reviewed-by: Peter Xu Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/intel_iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index b4f5094259..3206f379f8 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1884,6 +1884,8 @@ static void vtd_context_device_invalidate(IntelIOMMUS= tate *s, case 3: mask =3D 7; /* Mask bit 2:0 in the SID field */ break; + default: + g_assert_not_reached(); } mask =3D ~mask; =20 --=20 2.26.2 From nobody Wed Nov 19 03:02:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1614244801; cv=none; d=zohomail.com; s=zohoarc; b=IVkifrrabmuV2jSageDiPnTuAhcJJ9otIi8EVFlCZKdd/k0hJ7H2/XnVmBW4bG+Pkb1hNhws5bgIfb+FYihvTzaug7qQmG3QRxYGm+3MmoPJjZ/0F3GSavEaGpUy1sKvn68CfRSIbaT1CWLg/jrx9dCdENeMmupOBK7vCTwF2/M= ARC-Message-Signature: i=1; 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Thu, 25 Feb 2021 09:14:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1614244499; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QlhJLFza2TC8LpFNbS9wemapCKG9sKwTwXXw925Wq/U=; b=DM9CCFVMRRqH+NCIruE7X1/rY0AYNeXfVc6odPCB8J6Lervxc3RRIJghIPdpz0WRrv9F+f 40UlgC/0v3sxswkkbhHZwaW6fp5fJtINZ/UBXL73SRiWX6NAlGsjbVcQL3ekR9KuFzsyi1 iaBiZLdWXGVusVExe21GFCR9OxRXCak= X-MC-Unique: c9t8RHzxN_SYwN8bJm7BWw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, jean-philippe@linaro.org, peterx@redhat.com, jasowang@redhat.com, pbonzini@redhat.com Subject: [PATCH v2 2/7] dma: Introduce dma_aligned_pow2_mask() Date: Thu, 25 Feb 2021 10:14:30 +0100 Message-Id: <20210225091435.644762-3-eric.auger@redhat.com> In-Reply-To: <20210225091435.644762-1-eric.auger@redhat.com> References: <20210225091435.644762-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; 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charset="utf-8" Currently get_naturally_aligned_size() is used by the intel iommu to compute the maximum invalidation range based on @size which is a power of 2 while being aligned with the @start address and less than the maximum range defined by @gaw. This helper is also useful for other iommu devices (virtio-iommu, SMMUv3) to make sure IOMMU UNMAP notifiers only are called with power of 2 range sizes. Let's move this latter into dma-helpers.c and rename it into dma_aligned_pow2_mask(). Also rewrite the helper so that it accomodates UINT64_MAX values for the size mask and max mask. It now returns a mask instead of a size. Change the caller. Signed-off-by: Eric Auger Reviewed-by: Peter Xu --- hw/i386/intel_iommu.c | 30 +++++++----------------------- include/sysemu/dma.h | 3 +++ softmmu/dma-helpers.c | 26 ++++++++++++++++++++++++++ 3 files changed, 36 insertions(+), 23 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3206f379f8..6be8f32918 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -35,6 +35,7 @@ #include "hw/i386/x86-iommu.h" #include "hw/pci-host/q35.h" #include "sysemu/kvm.h" +#include "sysemu/dma.h" #include "sysemu/sysemu.h" #include "hw/i386/apic_internal.h" #include "kvm/kvm_i386.h" @@ -3455,24 +3456,6 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, int devfn) return vtd_dev_as; } =20 -static uint64_t get_naturally_aligned_size(uint64_t start, - uint64_t size, int gaw) -{ - uint64_t max_mask =3D 1ULL << gaw; - uint64_t alignment =3D start ? start & -start : max_mask; - - alignment =3D MIN(alignment, max_mask); - size =3D MIN(size, max_mask); - - if (alignment <=3D size) { - /* Increase the alignment of start */ - return alignment; - } else { - /* Find the largest page mask from size */ - return 1ULL << (63 - clz64(size)); - } -} - /* Unmap the whole range in the notifier's scope. */ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n) { @@ -3501,13 +3484,14 @@ static void vtd_address_space_unmap(VTDAddressSpace= *as, IOMMUNotifier *n) =20 while (remain >=3D VTD_PAGE_SIZE) { IOMMUTLBEvent event; - uint64_t mask =3D get_naturally_aligned_size(start, remain, s->aw_= bits); + uint64_t mask =3D dma_aligned_pow2_mask(start, end, s->aw_bits); + uint64_t size =3D mask + 1; =20 - assert(mask); + assert(size); =20 event.type =3D IOMMU_NOTIFIER_UNMAP; event.entry.iova =3D start; - event.entry.addr_mask =3D mask - 1; + event.entry.addr_mask =3D mask; event.entry.target_as =3D &address_space_memory; event.entry.perm =3D IOMMU_NONE; /* This field is meaningless for unmap */ @@ -3515,8 +3499,8 @@ static void vtd_address_space_unmap(VTDAddressSpace *= as, IOMMUNotifier *n) =20 memory_region_notify_iommu_one(n, &event); =20 - start +=3D mask; - remain -=3D mask; + start +=3D size; + remain -=3D size; } =20 assert(!remain); diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index a052f7bca3..2acb303be2 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -296,4 +296,7 @@ uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUS= GList *sg); void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie, QEMUSGList *sg, enum BlockAcctType type); =20 +uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end, + int max_addr_bits); + #endif diff --git a/softmmu/dma-helpers.c b/softmmu/dma-helpers.c index 29001b5459..7d766a5e89 100644 --- a/softmmu/dma-helpers.c +++ b/softmmu/dma-helpers.c @@ -330,3 +330,29 @@ void dma_acct_start(BlockBackend *blk, BlockAcctCookie= *cookie, { block_acct_start(blk_get_stats(blk), cookie, sg->size, type); } + +uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end, int max_addr_= bits) +{ + uint64_t max_mask =3D UINT64_MAX, addr_mask =3D end - start; + uint64_t alignment_mask, size_mask; + + if (max_addr_bits !=3D 64) { + max_mask =3D (1ULL << max_addr_bits) - 1; + } + + alignment_mask =3D start ? (start & -start) - 1 : max_mask; + alignment_mask =3D MIN(alignment_mask, max_mask); + size_mask =3D MIN(addr_mask, max_mask); + + if (alignment_mask <=3D size_mask) { + /* Increase the alignment of start */ + return alignment_mask; + } else { + /* Find the largest page mask from size */ + if (addr_mask =3D=3D UINT64_MAX) { + return UINT64_MAX; + } + return (1ULL << (63 - clz64(addr_mask + 1))) - 1; + } +} + --=20 2.26.2 From nobody Wed Nov 19 03:02:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1614244817; cv=none; d=zohomail.com; s=zohoarc; b=bu62FRLuVKDnhnoF6pQqGLr57Inm5DrFlU0I7LF0EX4n4TTWBlT+tTc3hETw6nA3OglaLDq1y/+A4pAvVwWLxxwVzl6wBWYXENIoe2Rp+393wEjCywQNR3aUHA0fJYXZSfy3E5SUKRkhSZ7/Ebe+tVYVP0R2v5KeEIav9KLE+q0= ARC-Message-Signature: i=1; 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Thu, 25 Feb 2021 09:14:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1614244502; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8CBiTjBBrSUvl7XaxpyhYLNyR7QNYng/yBdBtviVWFo=; b=Z6FMpttrDpOSXpchllwOqeob80+/FCJg2MlP+7fvL9EYOQ76WIW95M8HGY9m975YNDvJfq 4tWe1IllSgCQ+IR3PtRQXsddM05kzOKRvluIi1NBgRGHPvnMsIbM+dayh/aLAWxoQJjMld M6mcGv7YO53lWNCoFT55WZOo3VR3AuI= X-MC-Unique: WXpuI9esPQqQjbXlh6PTUw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, jean-philippe@linaro.org, peterx@redhat.com, jasowang@redhat.com, pbonzini@redhat.com Subject: [PATCH v2 3/7] virtio-iommu: Handle non power of 2 range invalidations Date: Thu, 25 Feb 2021 10:14:31 +0100 Message-Id: <20210225091435.644762-4-eric.auger@redhat.com> In-Reply-To: <20210225091435.644762-1-eric.auger@redhat.com> References: <20210225091435.644762-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; 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charset="utf-8" Unmap notifiers work with an address mask assuming an invalidation range of a power of 2. Nothing mandates this in the VIRTIO-IOMMU spec. So in case the range is not a power of 2, split it into several invalidations. Signed-off-by: Eric Auger Reviewed-by: Peter Xu --- hw/virtio/virtio-iommu.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index c2883a2f6c..1b23e8e18c 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -155,6 +155,7 @@ static void virtio_iommu_notify_unmap(IOMMUMemoryRegion= *mr, hwaddr virt_start, hwaddr virt_end) { IOMMUTLBEvent event; + uint64_t delta =3D virt_end - virt_start; =20 if (!(mr->iommu_notify_flags & IOMMU_NOTIFIER_UNMAP)) { return; @@ -164,12 +165,24 @@ static void virtio_iommu_notify_unmap(IOMMUMemoryRegi= on *mr, hwaddr virt_start, =20 event.type =3D IOMMU_NOTIFIER_UNMAP; event.entry.target_as =3D &address_space_memory; - event.entry.addr_mask =3D virt_end - virt_start; - event.entry.iova =3D virt_start; event.entry.perm =3D IOMMU_NONE; event.entry.translated_addr =3D 0; + event.entry.addr_mask =3D delta; + event.entry.iova =3D virt_start; =20 - memory_region_notify_iommu(mr, 0, event); + if (delta =3D=3D UINT64_MAX) { + memory_region_notify_iommu(mr, 0, event); + } + + + while (virt_start !=3D virt_end + 1) { + uint64_t mask =3D dma_aligned_pow2_mask(virt_start, virt_end, 64); + + event.entry.addr_mask =3D mask; + event.entry.iova =3D virt_start; + memory_region_notify_iommu(mr, 0, event); + virt_start +=3D mask + 1; + } } =20 static gboolean virtio_iommu_notify_unmap_cb(gpointer key, gpointer value, --=20 2.26.2 From nobody Wed Nov 19 03:02:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1614244949; cv=none; d=zohomail.com; s=zohoarc; b=CHgTCMpvIA4Pns5M+3HIu1v51eY3qXcrOMT1LCa9ufxYIcIZSoF5ljDmb7VDyiEIqjVbChOMscxDCw1I3jFhJGEMJdKHEe7c37qooW9NKq6jqO6M50Ar9C0XuMp52YacI6LikGP1ATYaqHFWhFancab+B+nnlMigyircSPMZNq0= ARC-Message-Signature: i=1; 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Thu, 25 Feb 2021 09:14:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1614244507; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=14p+j/CpjB0GM1QQbxolieRgFGzs9w3/Zsqc0TRnMgI=; b=ihPjVvQTB2df1xGhYomaQ9DJPusZHHvMwmI3kbSgwqnou4jJcFaKkizt5jyZnORda0CSG3 m0AGR8lkpeiGJmN+q5QJX6F5DVaTyuILdcJ+REl1qP5Ewlvkjv+LXtsfqMVJzOqZavbZOM idfSteFjsfwaN2dBNJ3ovVhihgBb86Y= X-MC-Unique: 00eL2p83MAiKr4Bl8JnJvQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, jean-philippe@linaro.org, peterx@redhat.com, jasowang@redhat.com, pbonzini@redhat.com Subject: [PATCH v2 4/7] hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set Date: Thu, 25 Feb 2021 10:14:32 +0100 Message-Id: <20210225091435.644762-5-eric.auger@redhat.com> In-Reply-To: <20210225091435.644762-1-eric.auger@redhat.com> References: <20210225091435.644762-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; 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charset="utf-8" If the asid is not set, do not attempt to locate the key directly as all inserted keys have a valid asid. Use g_hash_table_foreach_remove instead. Signed-off-by: Eric Auger --- hw/arm/smmu-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 405d5c5325..e9ca3aebb2 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -151,7 +151,7 @@ inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl) { - if (ttl && (num_pages =3D=3D 1)) { + if (ttl && (num_pages =3D=3D 1) && (asid >=3D 0)) { SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova, tg, ttl); =20 g_hash_table_remove(s->iotlb, &key); --=20 2.26.2 From nobody Wed Nov 19 03:02:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1614244732; cv=none; d=zohomail.com; s=zohoarc; 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Thu, 25 Feb 2021 09:15:11 +0000 (UTC) Received: from laptop.redhat.com (ovpn-114-34.ams2.redhat.com [10.36.114.34]) by smtp.corp.redhat.com (Postfix) with ESMTP id C7A6262A25; Thu, 25 Feb 2021 09:15:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1614244514; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xZePj1I1XRw41ZbDfqFmf7rcCnjhoBo+XZjBz8WpUOQ=; b=AJc1NVjVApA6Gyvhku3mW6LzROAm3GZjY+L6v5hW+oOviWYREhijiST7ROS0aH5rAyf7ln U8iJItbhBXpZJkvKcSkUk8JgghfP1KYhLQ7FmXZtuKnfb23RnYuGSHcEhKTtDAk5Isia7B 9u/vt87acf/Mo0+VHFObeAxUqGb++dQ= X-MC-Unique: uNnOs8H9N0-96ZTiz_LgnQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, jean-philippe@linaro.org, peterx@redhat.com, jasowang@redhat.com, pbonzini@redhat.com Subject: [PATCH v2 5/7] hw/arm/smmuv3: Enforce invalidation on a power of two range Date: Thu, 25 Feb 2021 10:14:33 +0100 Message-Id: <20210225091435.644762-6-eric.auger@redhat.com> In-Reply-To: <20210225091435.644762-1-eric.auger@redhat.com> References: <20210225091435.644762-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; 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charset="utf-8" As of today, the driver can invalide a number of pages that is not a power of 2. However IOTLB unmap notifications and internal IOTLB invalidations work with masks leading to erroneous invalidations. In case the range is not a power of 2, split invalidations into power of 2 invalidations. When looking for a single page entry in the vSMMU internal IOTLB, let's make sure that if the entry is not found using a g_hash_table_remove() we iterate over all the entries to find a potential range that overlaps it. Signed-off-by: Eric Auger --- hw/arm/smmu-common.c | 30 ++++++++++++++++++------------ hw/arm/smmuv3.c | 24 ++++++++++++++++++++---- 2 files changed, 38 insertions(+), 16 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index e9ca3aebb2..84d2c62c26 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -151,22 +151,28 @@ inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, uint8_t tg, uint64_t num_pages, uint8_t ttl) { + /* if tg is not set we use 4KB range invalidation */ + uint8_t granule =3D tg ? tg * 2 + 10 : 12; + if (ttl && (num_pages =3D=3D 1) && (asid >=3D 0)) { SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, iova, tg, ttl); =20 - g_hash_table_remove(s->iotlb, &key); - } else { - /* if tg is not set we use 4KB range invalidation */ - uint8_t granule =3D tg ? tg * 2 + 10 : 12; - - SMMUIOTLBPageInvInfo info =3D { - .asid =3D asid, .iova =3D iova, - .mask =3D (num_pages * 1 << granule) - 1}; - - g_hash_table_foreach_remove(s->iotlb, - smmu_hash_remove_by_asid_iova, - &info); + if (g_hash_table_remove(s->iotlb, &key)) { + return; + } + /* + * if the entry is not found, let's see if it does not + * belong to a larger IOTLB entry + */ } + + SMMUIOTLBPageInvInfo info =3D { + .asid =3D asid, .iova =3D iova, + .mask =3D (num_pages * 1 << granule) - 1}; + + g_hash_table_foreach_remove(s->iotlb, + smmu_hash_remove_by_asid_iova, + &info); } =20 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bd1f97000d..fdd6332ce5 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -861,7 +861,8 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cm= d) uint16_t vmid =3D CMD_VMID(cmd); bool leaf =3D CMD_LEAF(cmd); uint8_t tg =3D CMD_TG(cmd); - hwaddr num_pages =3D 1; + uint64_t first_page =3D 0, last_page; + uint64_t num_pages =3D 1; int asid =3D -1; =20 if (tg) { @@ -874,9 +875,24 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *c= md) if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { asid =3D CMD_ASID(cmd); } - trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf= ); - smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages); - smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); + + /* Split invalidations into ^2 range invalidations */ + last_page =3D num_pages - 1; + while (num_pages) { + uint8_t granule =3D tg * 2 + 10; + uint64_t mask, count; + + mask =3D dma_aligned_pow2_mask(first_page, last_page, 64 - granule= ); + count =3D mask + 1; + + trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, count, ttl, leaf= ); + smmuv3_inv_notifiers_iova(s, asid, addr, tg, count); + smmu_iotlb_inv_iova(s, asid, addr, tg, count, ttl); + + num_pages -=3D count; + first_page +=3D count; + addr +=3D count * BIT_ULL(granule); + } } =20 static int smmuv3_cmdq_consume(SMMUv3State *s) --=20 2.26.2 From nobody Wed Nov 19 03:02:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 25 Feb 2021 04:15:16 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0370D18C35CA; Thu, 25 Feb 2021 09:15:15 +0000 (UTC) Received: from laptop.redhat.com (ovpn-114-34.ams2.redhat.com [10.36.114.34]) by smtp.corp.redhat.com (Postfix) with ESMTP id 88F7863623; Thu, 25 Feb 2021 09:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1614244520; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X7z56cssujukh5mVL51YBukB9pXuTLOc3hfcaaMOgCE=; b=PJ970ATYNrNNtnyQy9jmuXoWcZBBHgtJ/eoJY2nVkdz4hSykOVsIf+FaadX/CdrlT1q8G0 WcXszfXKZWm0AsQijS/75/lmKyYFiYlzHWUC4UEoo/JlV+9RRr8/pOy370BQ4mFXHU7V9C aKEvvQJYUMdNnUN0FK6wf+Atv/AzHJ8= X-MC-Unique: IeEZNgmvPhiuO0wHvfQ5Sw-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, jean-philippe@linaro.org, peterx@redhat.com, jasowang@redhat.com, pbonzini@redhat.com Subject: [PATCH v2 6/7] hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling Date: Thu, 25 Feb 2021 10:14:34 +0100 Message-Id: <20210225091435.644762-7-eric.auger@redhat.com> In-Reply-To: <20210225091435.644762-1-eric.auger@redhat.com> References: <20210225091435.644762-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; 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charset="utf-8" If the whole SID range (32b) is invalidated (SMMU_CMD_CFGI_ALL), @end overflows and we fail to handle the command properly. Once this gets fixed, the current code really is awkward in the sense it loops over the whole range instead of removing the currently cached configs through a hash table lookup. Fix both the overflow and the lookup. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- hw/arm/smmu-internal.h | 5 +++++ hw/arm/smmuv3.c | 34 ++++++++++++++++++++-------------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index 55147f29be..2d75b31953 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -104,4 +104,9 @@ typedef struct SMMUIOTLBPageInvInfo { uint64_t mask; } SMMUIOTLBPageInvInfo; =20 +typedef struct SMMUSIDRange { + uint32_t start; + uint32_t end; +} SMMUSIDRange; + #endif diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index fdd6332ce5..3b87324ce2 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -32,6 +32,7 @@ =20 #include "hw/arm/smmuv3.h" #include "smmuv3-internal.h" +#include "smmu-internal.h" =20 /** * smmuv3_trigger_irq - pulse @irq if enabled and update @@ -895,6 +896,20 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *c= md) } } =20 +static gboolean +smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data) +{ + SMMUDevice *sdev =3D (SMMUDevice *)key; + uint32_t sid =3D smmu_get_sid(sdev); + SMMUSIDRange *sid_range =3D (SMMUSIDRange *)user_data; + + if (sid < sid_range->start || sid > sid_range->end) { + return false; + } + trace_smmuv3_config_cache_inv(sid); + return true; +} + static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); @@ -965,27 +980,18 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) } case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ { - uint32_t start =3D CMD_SID(&cmd), end, i; + uint32_t start =3D CMD_SID(&cmd); uint8_t range =3D CMD_STE_RANGE(&cmd); + uint64_t end =3D start + (1ULL << (range + 1)) - 1; + SMMUSIDRange sid_range =3D {start, end}; =20 if (CMD_SSEC(&cmd)) { cmd_error =3D SMMU_CERROR_ILL; break; } - - end =3D start + (1 << (range + 1)) - 1; trace_smmuv3_cmdq_cfgi_ste_range(start, end); - - for (i =3D start; i <=3D end; i++) { - IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, i); - SMMUDevice *sdev; - - if (!mr) { - continue; - } - sdev =3D container_of(mr, SMMUDevice, iommu); - smmuv3_flush_config(sdev); - } + g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste, + &sid_range); break; } case SMMU_CMD_CFGI_CD: --=20 2.26.2 From nobody Wed Nov 19 03:02:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1614244945; cv=none; d=zohomail.com; s=zohoarc; b=BQzfku4pBmA03yZ3aUsutOM7ZD1qoeDIBgkelE1x+Bpwh1kqJALP7xZXjRTc/HeQtGm73HLrAr7i5LeJovIajF2TqtnBcoAogLp55k5vTKXfQeHTiVJqxOEOiNHbETgI+Ewqw5uJ2oRIJqAoZVW8ag8el7q4UAM5lqrPge2iNIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614244945; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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d=redhat.com; s=mimecast20190719; t=1614244526; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iB/7Ge7AocTxeaZGZjq3gM/zWnXIQCTlec0VIFG3FNA=; b=gVOKRnSWL/KfTvAIIa10LLqi2x13jn/NUV11PFSC/b75dpLFp4VcPDKhMh1PKXAJw7QVln FuhrZzkJ8Vs1fkZp1+p+X3KQzgccmskDP8P0+dZUuza0oz8psLtQdIObX7wHyS/0gFZ8I4 wgo/zg+cXVofwU1d6+cOrLSLX/qVOt4= X-MC-Unique: io960E4LOUazH5iSEqLoTQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, jean-philippe@linaro.org, peterx@redhat.com, jasowang@redhat.com, pbonzini@redhat.com Subject: [PATCH v2 7/7] hw/arm/smmuv3: Uniformize sid traces Date: Thu, 25 Feb 2021 10:14:35 +0100 Message-Id: <20210225091435.644762-8-eric.auger@redhat.com> In-Reply-To: <20210225091435.644762-1-eric.auger@redhat.com> References: <20210225091435.644762-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; 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charset="utf-8" Convert all sid printouts to sid=3D0x%x. Signed-off-by: Eric Auger Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/trace-events | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index a335ee891d..b79a91af5f 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -29,26 +29,26 @@ smmuv3_cmdq_opcode(const char *opcode) "<--- %s" smmuv3_cmdq_consume_out(uint32_t prod, uint32_t cons, uint8_t prod_wrap, u= int8_t cons_wrap) "prod:%d, cons:%d, prod_wrap:%d, cons_wrap:%d " smmuv3_cmdq_consume_error(const char *cmd_name, uint8_t cmd_error) "Error = on %s command execution: %d" smmuv3_write_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) = "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" -smmuv3_record_event(const char *type, uint32_t sid) "%s sid=3D%d" -smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "SID:= 0x%x features:0x%x, sid_split:0x%x" +smmuv3_record_event(const char *type, uint32_t sid) "%s sid=3D0x%x" +smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "sid= =3D0x%x features:0x%x, sid_split:0x%x" smmuv3_find_ste_2lvl(uint64_t strtab_base, uint64_t l1ptr, int l1_ste_offs= et, uint64_t l2ptr, int l2_ste_offset, int max_l2_ste) "strtab_base:0x%"PRI= x64" l1ptr:0x%"PRIx64" l1_off:0x%x, l2ptr:0x%"PRIx64" l2_off:0x%x max_l2_st= e:%d" smmuv3_get_ste(uint64_t addr) "STE addr: 0x%"PRIx64 -smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool = is_write) "%s sid=3D%d bypass (smmu disabled) iova:0x%"PRIx64" is_write=3D%= d" -smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool i= s_write) "%s sid=3D%d STE bypass iova:0x%"PRIx64" is_write=3D%d" -smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is= _write) "%s sid=3D%d abort on iova:0x%"PRIx64" is_write=3D%d" -smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint6= 4_t translated, int perm) "%s sid=3D%d iova=3D0x%"PRIx64" translated=3D0x%"= PRIx64" perm=3D0x%x" +smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool = is_write) "%s sid=3D0x%x bypass (smmu disabled) iova:0x%"PRIx64" is_write= =3D%d" +smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool i= s_write) "%s sid=3D0x%x STE bypass iova:0x%"PRIx64" is_write=3D%d" +smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is= _write) "%s sid=3D0x%x abort on iova:0x%"PRIx64" is_write=3D%d" +smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint6= 4_t translated, int perm) "%s sid=3D0x%x iova=3D0x%"PRIx64" translated=3D0x= %"PRIx64" perm=3D0x%x" smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64 smmuv3_decode_cd(uint32_t oas) "oas=3D%d" smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz= , bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d" -smmuv3_cmdq_cfgi_ste(int streamid) "streamid =3D%d" +smmuv3_cmdq_cfgi_ste(int streamid) "streamid=3D 0x%x" smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0x%x - end=3D0x%x" -smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" -smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" -smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit rate= =3D%d)" -smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint6= 4_t num_pages, uint8_t ttl, bool leaf) "vmid =3D%d asid =3D%d addr=3D0x%"PR= Ix64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" +smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=3D0x%x" +smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid=3D0x%x (hits=3D%d, misses=3D%d, hit ra= te=3D%d)" +smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid=3D0x%x (hits=3D%d, misses=3D%d, hit = rate=3D%d)" +smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint6= 4_t num_pages, uint8_t ttl, bool leaf) "vmid=3D%d asid=3D%d addr=3D0x%"PRIx= 64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" -smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d" +smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=3D0x%x" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 --=20 2.26.2