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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id i8sm6364961wry.90.2021.02.24.14.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Feb 2021 14:46:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1614206818; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EVnue42BrttlBCQCGj0TZzTKP7+Zxi1Gm+4446lormI=; b=B1hB2tYmOvtiyaoTjqSPJvrDafiWKPFsoSS+jIwTvUbqBMjGKP4acwpsgw3h87/lvlgGUe gHih3nM5ba9hnG7R9SBZqlhD9RseQGj3uvvdp3QoEQ2GUo+Nu3RehsaYKntB9rGzT4HTzD mrQrvpUQ4512/FM6jUanA4EGhfHTeKc= X-MC-Unique: P0GGfzGONbieKFwoj4ObHQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EVnue42BrttlBCQCGj0TZzTKP7+Zxi1Gm+4446lormI=; b=oEm8hgL7FK0N5WhJsjNqi9U2El6VvL2ePt/rsK7ubjvUX5SFmuHo7klSdbGLPHP5cZ +i692wb5wxIhARMkePIkj9oXe+TK8lBoI7QQifrnk3MvLLSs76B1frx3ELD7scHJEBbd PrSBTUVZmS+jtUFy79Ioi/2nAOl2yVUKlqy0qXNCTnIatEh7Jz6hIjYk95YJyxZC8RFR R52vDmElvly2yBf6ph1OnO/rBUk4CTP9qrJowYomp1BoMxNb98rLFSuFjUuwYON2a2c0 YKNGCIKSgHFAaRiJPTLPcds4ORAEx4QwuknpfeAtwNzlOWzNa0u8w/tAh73Gr1kWLvv9 gzbg== X-Gm-Message-State: AOAM531z0kyCjKKkgC7wN6NVi0OuI6kH+VYerOXZZ113SCNR92YuGy/M Z8DUd07eWkd1tFT5wqaZb7ngh9tgg7wRwRzQ8MFRPkyZhe6Myy6lH3mW1QhvQG2YWMaNKM0w0c1 uvr6DgKse7M2Shw== X-Received: by 2002:a1c:65d6:: with SMTP id z205mr278831wmb.88.1614206815169; Wed, 24 Feb 2021 14:46:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJy1uPTEQliKMX3O/FOW4JYYaofFyYjKURWoqSHU31T+txdc51Rk/0Y43hyBTLMML56sBzmwng== X-Received: by 2002:a1c:65d6:: with SMTP id z205mr278821wmb.88.1614206814986; Wed, 24 Feb 2021 14:46:54 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Eduardo Habkost , Markus Armbruster , Laurent Vivier , Eric Blake , Marcel Apfelbaum , Claudio Fontana , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 2/4] target/i386/cpu: Restrict x86_cpu_get_feature_words to sysemu Date: Wed, 24 Feb 2021 23:46:41 +0100 Message-Id: <20210224224643.3369940-3-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210224224643.3369940-1-philmd@redhat.com> References: <20210224224643.3369940-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) Only qemu-system-FOO and qemu-storage-daemon provide QMP monitors, therefore such declarations and definitions are irrelevant for user-mode emulation. Restricting the x86-specific commands to machine-target.json pulls less QAPI-generated code into user-mode. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/cpu-internal.h | 3 +++ target/i386/cpu-softmmu.c | 36 ++++++++++++++++++++++++++++++++++ target/i386/cpu.c | 40 +++----------------------------------- 3 files changed, 42 insertions(+), 37 deletions(-) diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h index 9df24c482ea..9355f86f6e1 100644 --- a/target/i386/cpu-internal.h +++ b/target/i386/cpu-internal.h @@ -69,6 +69,9 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, void x86_cpu_apic_create(X86CPU *cpu, Error **errp); void x86_cpu_apic_realize(X86CPU *cpu, Error **errp); void x86_cpu_machine_reset_cb(void *opaque); +void x86_cpu_get_feature_words(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp); #endif /* CONFIG_USER_ONLY */ =20 #endif /* CPU_INTERNAL_H */ diff --git a/target/i386/cpu-softmmu.c b/target/i386/cpu-softmmu.c index c824408e8eb..34fd7b0de02 100644 --- a/target/i386/cpu-softmmu.c +++ b/target/i386/cpu-softmmu.c @@ -23,6 +23,7 @@ #include "sysemu/whpx.h" #include "kvm/kvm_i386.h" #include "qapi/error.h" +#include "qapi/qapi-visit-machine.h" #include "qapi/qapi-visit-run-state.h" #include "qapi/qmp/qdict.h" #include "qom/qom-qobject.h" @@ -350,3 +351,38 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *= v, qapi_free_GuestPanicInformation(panic_info); } =20 +/* Generic getter for "feature-words" and "filtered-features" properties */ +void x86_cpu_get_feature_words(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint64_t *array =3D (uint64_t *)opaque; + FeatureWord w; + X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] =3D { }; + X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] =3D { }; + X86CPUFeatureWordInfoList *list =3D NULL; + + for (w =3D 0; w < FEATURE_WORDS; w++) { + FeatureWordInfo *wi =3D &feature_word_info[w]; + /* + * We didn't have MSR features when "feature-words" was + * introduced. Therefore skipped other type entries. + */ + if (wi->type !=3D CPUID_FEATURE_WORD) { + continue; + } + X86CPUFeatureWordInfo *qwi =3D &word_infos[w]; + qwi->cpuid_input_eax =3D wi->cpuid.eax; + qwi->has_cpuid_input_ecx =3D wi->cpuid.needs_ecx; + qwi->cpuid_input_ecx =3D wi->cpuid.ecx; + qwi->cpuid_register =3D get_register_enum_32(w); + qwi->features =3D array[w]; + + /* List will be in reverse order, but order shouldn't matter */ + list_entries[w].next =3D list; + list_entries[w].value =3D &word_infos[w]; + list =3D &list_entries[w]; + } + + visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); +} diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ffa342171ba..c088bcf3113 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -27,7 +27,7 @@ #include "sysemu/hvf.h" #include "kvm/kvm_i386.h" #include "sev_i386.h" -#include "qapi/qapi-visit-machine.h" +#include "qapi/qapi-builtin-visit.h" #include "qapi/qmp/qerror.h" #include "qapi/qapi-commands-machine-target.h" #include "standard-headers/asm-x86/kvm_para.h" @@ -4529,42 +4529,6 @@ static void x86_cpuid_set_tsc_freq(Object *obj, Visi= tor *v, const char *name, cpu->env.tsc_khz =3D cpu->env.user_tsc_khz =3D value / 1000; } =20 -/* Generic getter for "feature-words" and "filtered-features" properties */ -static void x86_cpu_get_feature_words(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) -{ - uint64_t *array =3D (uint64_t *)opaque; - FeatureWord w; - X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] =3D { }; - X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] =3D { }; - X86CPUFeatureWordInfoList *list =3D NULL; - - for (w =3D 0; w < FEATURE_WORDS; w++) { - FeatureWordInfo *wi =3D &feature_word_info[w]; - /* - * We didn't have MSR features when "feature-words" was - * introduced. Therefore skipped other type entries. - */ - if (wi->type !=3D CPUID_FEATURE_WORD) { - continue; - } - X86CPUFeatureWordInfo *qwi =3D &word_infos[w]; - qwi->cpuid_input_eax =3D wi->cpuid.eax; - qwi->has_cpuid_input_ecx =3D wi->cpuid.needs_ecx; - qwi->cpuid_input_ecx =3D wi->cpuid.ecx; - qwi->cpuid_register =3D get_register_enum_32(w); - qwi->features =3D array[w]; - - /* List will be in reverse order, but order shouldn't matter */ - list_entries[w].next =3D list; - list_entries[w].value =3D &word_infos[w]; - list =3D &list_entries[w]; - } - - visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); -} - /* Convert all '_' in a feature string option name to '-', to make feature * name conform to QOM property naming rule, which uses '-' instead of '_'. */ @@ -6422,12 +6386,14 @@ static void x86_cpu_initfn(Object *obj) env->nr_dies =3D 1; cpu_set_cpustate_pointers(cpu); =20 +#if !defined(CONFIG_USER_ONLY) object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", x86_cpu_get_feature_words, NULL, NULL, (void *)env->features); object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", x86_cpu_get_feature_words, NULL, NULL, (void *)cpu->filtered_features); +#endif /* !CONFIG_USER_ONLY */ =20 object_property_add_alias(obj, "sse3", obj, "pni"); object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); --=20 2.26.2