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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id fw18sm2057773pjb.46.2021.02.23.00.19.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 00:19:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=1qrHobv3NrqcH2ghUvMxccLmDGRDxe+jf1v0dL2ZvGc=; b=CHe+3qGRmKPjDneLse1yoCmabbOJHPKRRd3negZwA6Dns/gspK+Vp0p5RVrJVrPrHv zRbsYTLDPoOPpS2kkKQ3MRMmufKk020InNtDsEkHap6jeo4RY98auhn9pIblb9OWD1zB ec+k86HsgEvLuru1/obSbI7d1qXLOhbdXs43ZSFQD/o8/0sdfzEYKHsjLUHXPYoabk8o tKNTFY7uj2gNyOvy/QLgJPxno2MXbL4kvjsksWPsytLppkdWqNaUj1MkCSUB/bWeqA1a /pvKuwaFAT2ay5tPJ1DK2yIBsRVPXj77X7iOFk6bckRCkFUKlIpD74vSzTPjxU8kcO1z e9tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=1qrHobv3NrqcH2ghUvMxccLmDGRDxe+jf1v0dL2ZvGc=; b=tIVzpjG5O6+kOe7ZXqbkmI6xsFWaN/uPqu3raSugeB21gEQOCMaHrolM3QSdXjCndn TaNRa/N/7E/pq6cRKtGu8cs1YTck0Yr5Pv37qQnryvme6oVAfMJCKd5Jkh2u3ytMwHKw rwv52j4WPfyrfIeHhHb8gub2GaI5qk1bq1TslDQbgYxcuVtAEL7826uTNWaqYfLPF1wr 4JP4kcB14cSFgzb5aLVWho1p4cQaWkm/VQcBdn8n0az5TWSy8MHXxhHXT1CzbPzjePx/ dbW2A+tmHBpEbH7dsn8iuY671crkKDUDr3jO00FfFkbw0R0MYJUDuiL/hVizENDhdErl baLQ== X-Gm-Message-State: AOAM533fT5dDa4XhwGh+qgB3nNWh2pB++r235D94yE/WLZ60ePyaIj1b CsqQG7Jm4bEc8evcv8qjS1P9udLb0EH2kg== X-Google-Smtp-Source: ABdhPJynpt1oPBg6mxQ6bAbaDCMYbwM2xs56qmZ2updBWlD1Bvds9RMBgAJ2oe+Kv3GVrse6pvzB3Q== X-Received: by 2002:a62:7e58:0:b029:1ed:b833:a305 with SMTP id z85-20020a627e580000b02901edb833a305mr6050729pfc.66.1614068397429; Tue, 23 Feb 2021 00:19:57 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh Date: Tue, 23 Feb 2021 16:19:49 +0800 Message-Id: <20210223081951.20226-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in commit: c445593, but other TB_FLAGS bits for rvv and rvh were not shift as well so these bits may overlap with each other when rvv is enabled. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 12 ++++++------ target/riscv/translate.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 02758ae0eb4..116b16b9362 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -370,7 +370,6 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState = *env, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_MMU_MASK 7 #define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS @@ -379,12 +378,13 @@ typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" =20 -FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) -FIELD(TB_FLAGS, LMUL, 3, 2) -FIELD(TB_FLAGS, SEW, 5, 3) -FIELD(TB_FLAGS, VILL, 8, 1) +FIELD(TB_FLAGS, MEM_IDX, 0, 3) +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) +FIELD(TB_FLAGS, LMUL, 4, 2) +FIELD(TB_FLAGS, SEW, 6, 3) +FIELD(TB_FLAGS, VILL, 9, 1) /* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 9, 1) +FIELD(TB_FLAGS, HLSX, 10, 1) =20 bool riscv_cpu_is_32bit(CPURISCVState *env); =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0f28b5f41e4..9b518cdff46 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -802,7 +802,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) uint32_t tb_flags =3D ctx->base.tb->flags; =20 ctx->pc_succ_insn =3D ctx->base.pc_first; - ctx->mem_idx =3D tb_flags & TB_FLAGS_MMU_MASK; + ctx->mem_idx =3D FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); ctx->mstatus_fs =3D tb_flags & TB_FLAGS_MSTATUS_FS; ctx->priv_ver =3D env->priv_ver; #if !defined(CONFIG_USER_ONLY) --=20 2.17.1