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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id g10sm10964772ejk.88.2021.02.22.14.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KE7Pv3FR29RHJNt2Ewyj6WvD7fKOv1MAXLDq1W60PP8=; b=A/MrfTmxZ74Y3a/v338lU+obhWjPBSWfrz5+B4FiPAATAUwRRcltfeuV4/pGwkVfy0 YIbw/+W8+Cx7KJOZeGRsnF7u4uOV1jupRCjO7DRMbBZNlEGKX9LMOsrKF0mSZ31zgK2d j3CZB87L+rNKSgvVnoJauI7wI5jT6h6HrYpg2PGitd+FFZI8R6+jeFt9fMbeUM96zswY FloL+yRY19+Wge1tQIH9AueqQ7VHQp7UM1KfqTTTEGrSrURZkYJPks2oZjRIrWetIpAL +/uSzQs5UHEEe6iW7Dcv2dSM8pgi8Nm2+UzlIe+fWvVZ7zIhKwh72lC+0FU3cs3oLNQL DpiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=KE7Pv3FR29RHJNt2Ewyj6WvD7fKOv1MAXLDq1W60PP8=; b=sqrss8KmVistuuttQaxsP5ONUbiRI5Xm0lzCVne1WdEzOXZtXiQCOepLYRYr23D7dL zmc9B+6JMUYXbbBw63O6PT21g4WSHJ3dr4DwjKB7CTrZL8nnlEwnaGJkGj2vpf1+/yyy 2d5nDhxWfsyUjWlNgFXYdYKxDZcCkN2MENMzgcrUprDS8k7HaTqyHaRK/yppO6wSmhQS RKILG2RGFPeULmSPt2Wcho7Jrw2R1BAk7g4zBszfuUcIwV+kg1vC1bR8Py16Qc0r/o4X Mz/nhWYG+OEh/4ikzF4Z0JGdBASD/s+E1WXSnqtBcGUNR8B373ZvmtYVZ3Fo/RlWGY2Z iy6Q== X-Gm-Message-State: AOAM532O3C7birQlaBUOuCdyQkPuNVSi15ewBhDvTXAq4RDXntx5aRM+ 2Mchnfyi/HvWbdFvx14m67c= X-Google-Smtp-Source: ABdhPJzChzvdS3YB8sE1fkJkzHZ/3jk0+shyqB9me3TptSd2YBkebsmNd4UOkJpCAh/lQx71EjYzag== X-Received: by 2002:a17:906:d8c3:: with SMTP id re3mr11717768ejb.82.1614033549316; Mon, 22 Feb 2021 14:39:09 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 01/10] target/mips: Rewrite complex ifdef'ry Date: Mon, 22 Feb 2021 23:38:52 +0100 Message-Id: <20210222223901.2792336-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No need for this obfuscated ifdef'ry, KISS. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 70891c37cdd..1f1c5f33c87 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28276,13 +28276,16 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) #if defined(TARGET_MIPS64) if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI))= { decode_mmi(env, ctx); -#else + break; + } +#endif +#if !defined(TARGET_MIPS64) if (ctx->insn_flags & ASE_MXU) { decode_opc_mxu(env, ctx); -#endif - } else { - decode_opc_special2_legacy(env, ctx); + break; } +#endif + decode_opc_special2_legacy(env, ctx); break; case OPC_SPECIAL3: #if defined(TARGET_MIPS64) --=20 2.26.2 From nobody Mon Feb 9 14:35:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.45 as permitted sender) client-ip=209.85.218.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614033557; cv=none; d=zohomail.com; s=zohoarc; b=Lmxb3vsdspq6BbwgM4R83kHQ48KWu9ezMzTo9rybNQ6aBV13yC9yojFa7VdHdKob1vPVbliki8BiasKpKgQsXPBrsXabA5ov9lIauRUw2TPSI8RdDewzq06oNDd/XdSQIwE4AyH/wgLQEPTunFxAo7/oKWOqAmsEhuW6UP1JP6Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614033557; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/+fUHjHQzA9nBfh2GEe8qUxmTXV/2kN9U/A1rM+oOcI=; b=VwgfigTj/5pFUVlP3aT2j8v0Q6JtywcQOETqlNQLfHFvEOLO3pu/0WpAuKndqse9fmEhyUWrsyZbGqtk+1tDSux0YMZiK/lbejOI5z3H89ad2bAfMj+8ZVhRnS0+p5wM5ci1hZkp2zL4qh0qJLOC/b2Yl0a0bEbUxAhhMwdi1Nw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) by mx.zohomail.com with SMTPS id 1614033557387171.70103232014708; Mon, 22 Feb 2021 14:39:17 -0800 (PST) Received: by mail-ej1-f45.google.com with SMTP id w1so31652670ejf.11 for ; Mon, 22 Feb 2021 14:39:16 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id i18sm12958066eds.19.2021.02.22.14.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/+fUHjHQzA9nBfh2GEe8qUxmTXV/2kN9U/A1rM+oOcI=; b=MkGulXJBI7k29OT9cRwnbMzdwNjThl9qz4RvAqK4W0jK8PdK8ubSKns5DBqebsGOjZ WaelSbi/gnInmehexu1JgoFJ+iv9mNodGeUW5dw3kdDi7mJz8N4ni3QvDHQz31rOSyeQ WpwJJiuFXrCuZVcHQW3jgtT0l4KvfhfE2J5uGSCZRQPM2Sl32ErkhUpDkKCNtZ9qmJ2W RkmBgntzbuIh06h2+3jMpHTbX2hbBMIotw8PJ6NV5MSqydSAj6FxZSeWkR9NvcULzFao HAQJviLUcfmUcFUAyQNkodthqK5McI17WO0QvD/AKjz5+03IbQSm/hSilzKrIdxssUl1 sd9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/+fUHjHQzA9nBfh2GEe8qUxmTXV/2kN9U/A1rM+oOcI=; b=YRW9+oiPmiZ/SC0hsISIzp7ftN3UE7rOeUsUG42qIQFcjCL+t5OYBFmzS/gX791lXi WJW3GWUUouGVYO3krbTgk0sM+1YwtBKr8VYsKlaZ2QLrV+xHNM4c58eVjUyBPZ5pf0FM z/2iVnGBizGhETb6L1A8ASq+4UvEDKr464enfu573x2kUjDTgtjd4lzOjCtklAVCcgRH ec6WuxNbD6+WiMeTIi9FSYSMn2JmXaA3JAGxJ0/WN9MevtRXY/ddmXYmwJ0pvdif8+fn vjA1GBAjmK9WY1SVGkV1cNu0X29Zob0v+kWuwaAGEVufS1kl643bP7mOBi82K6117/mX UjgA== X-Gm-Message-State: AOAM532ActBkD0SBi2zioCSSHYCHobJsFX5jOkF9TO5cTgWu5BybNXKJ KmajyQQ0qhjpqCoXkThJni0= X-Google-Smtp-Source: ABdhPJz4gkYznIgfTEcQ28v6oHDV07qWty6PLhul7Y17qb1TJ5VHMeh8vD7thAidBhebODLHfEmScw== X-Received: by 2002:a17:906:ad83:: with SMTP id la3mr22338090ejb.257.1614033554966; Mon, 22 Feb 2021 14:39:14 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 02/10] target/mips: Remove XBurst Media eXtension Unit dead code Date: Mon, 22 Feb 2021 23:38:53 +0100 Message-Id: <20210222223901.2792336-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) All these unimplemented MXU opcodes end up calling gen_reserved_instruction() which is the default switch case in decode_opc_mxu(). The translate.c file is already big enough and hard to maintain, remove 1300 lines of unnecessary code and /* TODO */ comments. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 1286 --------------------------------------- 1 file changed, 1286 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 1f1c5f33c87..a53ce6adb9a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1464,70 +1464,16 @@ enum { */ =20 enum { - OPC_MXU_S32MADD =3D 0x00, - OPC_MXU_S32MADDU =3D 0x01, OPC__MXU_MUL =3D 0x02, OPC_MXU__POOL00 =3D 0x03, - OPC_MXU_S32MSUB =3D 0x04, - OPC_MXU_S32MSUBU =3D 0x05, - OPC_MXU__POOL01 =3D 0x06, - OPC_MXU__POOL02 =3D 0x07, OPC_MXU_D16MUL =3D 0x08, - OPC_MXU__POOL03 =3D 0x09, OPC_MXU_D16MAC =3D 0x0A, - OPC_MXU_D16MACF =3D 0x0B, - OPC_MXU_D16MADL =3D 0x0C, - OPC_MXU_S16MAD =3D 0x0D, - OPC_MXU_Q16ADD =3D 0x0E, - OPC_MXU_D16MACE =3D 0x0F, OPC_MXU__POOL04 =3D 0x10, - OPC_MXU__POOL05 =3D 0x11, - OPC_MXU__POOL06 =3D 0x12, - OPC_MXU__POOL07 =3D 0x13, - OPC_MXU__POOL08 =3D 0x14, - OPC_MXU__POOL09 =3D 0x15, - OPC_MXU__POOL10 =3D 0x16, - OPC_MXU__POOL11 =3D 0x17, - OPC_MXU_D32ADD =3D 0x18, - OPC_MXU__POOL12 =3D 0x19, - /* not assigned 0x1A */ - OPC_MXU__POOL13 =3D 0x1B, - OPC_MXU__POOL14 =3D 0x1C, - OPC_MXU_Q8ACCE =3D 0x1D, - /* not assigned 0x1E */ - /* not assigned 0x1F */ - /* not assigned 0x20 */ - /* not assigned 0x21 */ OPC_MXU_S8LDD =3D 0x22, - OPC_MXU_S8STD =3D 0x23, - OPC_MXU_S8LDI =3D 0x24, - OPC_MXU_S8SDI =3D 0x25, - OPC_MXU__POOL15 =3D 0x26, OPC_MXU__POOL16 =3D 0x27, - OPC_MXU__POOL17 =3D 0x28, - /* not assigned 0x29 */ - OPC_MXU_S16LDD =3D 0x2A, - OPC_MXU_S16STD =3D 0x2B, - OPC_MXU_S16LDI =3D 0x2C, - OPC_MXU_S16SDI =3D 0x2D, OPC_MXU_S32M2I =3D 0x2E, OPC_MXU_S32I2M =3D 0x2F, - OPC_MXU_D32SLL =3D 0x30, - OPC_MXU_D32SLR =3D 0x31, - OPC_MXU_D32SARL =3D 0x32, - OPC_MXU_D32SAR =3D 0x33, - OPC_MXU_Q16SLL =3D 0x34, - OPC_MXU_Q16SLR =3D 0x35, - OPC_MXU__POOL18 =3D 0x36, - OPC_MXU_Q16SAR =3D 0x37, OPC_MXU__POOL19 =3D 0x38, - OPC_MXU__POOL20 =3D 0x39, - OPC_MXU__POOL21 =3D 0x3A, - OPC_MXU_Q16SCOP =3D 0x3B, - OPC_MXU_Q8MADL =3D 0x3C, - OPC_MXU_S32SFL =3D 0x3D, - OPC_MXU_Q8SAD =3D 0x3E, - /* not assigned 0x3F */ }; =20 =20 @@ -1541,39 +1487,6 @@ enum { OPC_MXU_D16MIN =3D 0x03, OPC_MXU_Q8MAX =3D 0x04, OPC_MXU_Q8MIN =3D 0x05, - OPC_MXU_Q8SLT =3D 0x06, - OPC_MXU_Q8SLTU =3D 0x07, -}; - -/* - * MXU pool 01 - */ -enum { - OPC_MXU_S32SLT =3D 0x00, - OPC_MXU_D16SLT =3D 0x01, - OPC_MXU_D16AVG =3D 0x02, - OPC_MXU_D16AVGR =3D 0x03, - OPC_MXU_Q8AVG =3D 0x04, - OPC_MXU_Q8AVGR =3D 0x05, - OPC_MXU_Q8ADD =3D 0x07, -}; - -/* - * MXU pool 02 - */ -enum { - OPC_MXU_S32CPS =3D 0x00, - OPC_MXU_D16CPS =3D 0x02, - OPC_MXU_Q8ABD =3D 0x04, - OPC_MXU_Q16SAT =3D 0x06, -}; - -/* - * MXU pool 03 - */ -enum { - OPC_MXU_D16MULF =3D 0x00, - OPC_MXU_D16MULE =3D 0x01, }; =20 /* @@ -1584,136 +1497,17 @@ enum { OPC_MXU_S32LDDR =3D 0x01, }; =20 -/* - * MXU pool 05 - */ -enum { - OPC_MXU_S32STD =3D 0x00, - OPC_MXU_S32STDR =3D 0x01, -}; - -/* - * MXU pool 06 - */ -enum { - OPC_MXU_S32LDDV =3D 0x00, - OPC_MXU_S32LDDVR =3D 0x01, -}; - -/* - * MXU pool 07 - */ -enum { - OPC_MXU_S32STDV =3D 0x00, - OPC_MXU_S32STDVR =3D 0x01, -}; - -/* - * MXU pool 08 - */ -enum { - OPC_MXU_S32LDI =3D 0x00, - OPC_MXU_S32LDIR =3D 0x01, -}; - -/* - * MXU pool 09 - */ -enum { - OPC_MXU_S32SDI =3D 0x00, - OPC_MXU_S32SDIR =3D 0x01, -}; - -/* - * MXU pool 10 - */ -enum { - OPC_MXU_S32LDIV =3D 0x00, - OPC_MXU_S32LDIVR =3D 0x01, -}; - -/* - * MXU pool 11 - */ -enum { - OPC_MXU_S32SDIV =3D 0x00, - OPC_MXU_S32SDIVR =3D 0x01, -}; - -/* - * MXU pool 12 - */ -enum { - OPC_MXU_D32ACC =3D 0x00, - OPC_MXU_D32ACCM =3D 0x01, - OPC_MXU_D32ASUM =3D 0x02, -}; - -/* - * MXU pool 13 - */ -enum { - OPC_MXU_Q16ACC =3D 0x00, - OPC_MXU_Q16ACCM =3D 0x01, - OPC_MXU_Q16ASUM =3D 0x02, -}; - -/* - * MXU pool 14 - */ -enum { - OPC_MXU_Q8ADDE =3D 0x00, - OPC_MXU_D8SUM =3D 0x01, - OPC_MXU_D8SUMC =3D 0x02, -}; - -/* - * MXU pool 15 - */ -enum { - OPC_MXU_S32MUL =3D 0x00, - OPC_MXU_S32MULU =3D 0x01, - OPC_MXU_S32EXTR =3D 0x02, - OPC_MXU_S32EXTRV =3D 0x03, -}; - /* * MXU pool 16 */ enum { - OPC_MXU_D32SARW =3D 0x00, - OPC_MXU_S32ALN =3D 0x01, OPC_MXU_S32ALNI =3D 0x02, - OPC_MXU_S32LUI =3D 0x03, OPC_MXU_S32NOR =3D 0x04, OPC_MXU_S32AND =3D 0x05, OPC_MXU_S32OR =3D 0x06, OPC_MXU_S32XOR =3D 0x07, }; =20 -/* - * MXU pool 17 - */ -enum { - OPC_MXU_LXB =3D 0x00, - OPC_MXU_LXH =3D 0x01, - OPC_MXU_LXW =3D 0x03, - OPC_MXU_LXBU =3D 0x04, - OPC_MXU_LXHU =3D 0x05, -}; - -/* - * MXU pool 18 - */ -enum { - OPC_MXU_D32SLLV =3D 0x00, - OPC_MXU_D32SLRV =3D 0x01, - OPC_MXU_D32SARV =3D 0x03, - OPC_MXU_Q16SLLV =3D 0x04, - OPC_MXU_Q16SLRV =3D 0x05, - OPC_MXU_Q16SARV =3D 0x07, -}; - /* * MXU pool 19 */ @@ -1722,26 +1516,6 @@ enum { OPC_MXU_Q8MULSU =3D 0x01, }; =20 -/* - * MXU pool 20 - */ -enum { - OPC_MXU_Q8MOVZ =3D 0x00, - OPC_MXU_Q8MOVN =3D 0x01, - OPC_MXU_D16MOVZ =3D 0x02, - OPC_MXU_D16MOVN =3D 0x03, - OPC_MXU_S32MOVZ =3D 0x04, - OPC_MXU_S32MOVN =3D 0x05, -}; - -/* - * MXU pool 21 - */ -enum { - OPC_MXU_Q8MAC =3D 0x00, - OPC_MXU_Q8MACSU =3D 0x01, -}; - /* * Overview of the TX79-specific instruction set * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -25332,11 +25106,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *c= tx) * S32NOR XRa, XRb, XRc * Update XRa with the result of logical bitwise 'nor' operation * applied to the content of XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32NOR(DisasContext *ctx) { @@ -25373,11 +25142,6 @@ static void gen_mxu_S32NOR(DisasContext *ctx) * S32AND XRa, XRb, XRc * Update XRa with the result of logical bitwise 'and' operation * applied to the content of XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32AND(DisasContext *ctx) { @@ -25408,11 +25172,6 @@ static void gen_mxu_S32AND(DisasContext *ctx) * S32OR XRa, XRb, XRc * Update XRa with the result of logical bitwise 'or' operation * applied to the content of XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32OR(DisasContext *ctx) { @@ -25449,11 +25208,6 @@ static void gen_mxu_S32OR(DisasContext *ctx) * S32XOR XRa, XRb, XRc * Update XRa with the result of logical bitwise 'xor' operation * applied to the content of XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32XOR(DisasContext *ctx) { @@ -25503,11 +25257,6 @@ static void gen_mxu_S32XOR(DisasContext *ctx) * S32MIN XRa, XRb, XRc * Update XRa with the minimum of signed 32-bit integers contained * in XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx) { @@ -25558,11 +25307,6 @@ static void gen_mxu_S32MAX_S32MIN(DisasContext *ct= x) * D16MIN * Update XRa with the 16-bit-wise minimums of signed integers * contained in XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) { @@ -25660,11 +25404,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ct= x) * Q8MIN * Update XRa with the 8-bit-wise minimums of signed integers * contained in XRb and XRc. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| - * +-----------+---------+-----+-------+-------+-------+-----------+ */ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) { @@ -25774,12 +25513,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) * S32ALNI XRc, XRb, XRa, optn3 * Arrange bytes from XRb and XRc according to one of five sets of * rules determined by optn3, and place the result in XRa. - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+-----+---+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |optn3|0 0|x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+-----+---+-----+-------+-------+-------+-----------+ - * */ static void gen_mxu_S32ALNI(DisasContext *ctx) { @@ -25961,16 +25694,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 -/* - * - * Decode MXU pool00 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL00| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); @@ -25988,16 +25711,6 @@ static void decode_opc_mxu__pool00(CPUMIPSState *e= nv, DisasContext *ctx) case OPC_MXU_Q8MIN: gen_mxu_Q8MAX_Q8MIN(ctx); break; - case OPC_MXU_Q8SLT: - /* TODO: Implement emulation of Q8SLT instruction. */ - MIPS_INVAL("OPC_MXU_Q8SLT"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8SLTU: - /* TODO: Implement emulation of Q8SLTU instruction. */ - MIPS_INVAL("OPC_MXU_Q8SLTU"); - gen_reserved_instruction(ctx); - break; default: MIPS_INVAL("decode_opc_mxu"); gen_reserved_instruction(ctx); @@ -26005,161 +25718,6 @@ static void decode_opc_mxu__pool00(CPUMIPSState *= env, DisasContext *ctx) } } =20 -/* - * - * Decode MXU pool01 - * - * S32SLT, D16SLT, D16AVG, D16AVGR, Q8AVG, Q8AVGR: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - * Q8ADD: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+-----+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |en2|0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01| - * +-----------+---+-----+-----+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool01(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_S32SLT: - /* TODO: Implement emulation of S32SLT instruction. */ - MIPS_INVAL("OPC_MXU_S32SLT"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16SLT: - /* TODO: Implement emulation of D16SLT instruction. */ - MIPS_INVAL("OPC_MXU_D16SLT"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16AVG: - /* TODO: Implement emulation of D16AVG instruction. */ - MIPS_INVAL("OPC_MXU_D16AVG"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16AVGR: - /* TODO: Implement emulation of D16AVGR instruction. */ - MIPS_INVAL("OPC_MXU_D16AVGR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8AVG: - /* TODO: Implement emulation of Q8AVG instruction. */ - MIPS_INVAL("OPC_MXU_Q8AVG"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8AVGR: - /* TODO: Implement emulation of Q8AVGR instruction. */ - MIPS_INVAL("OPC_MXU_Q8AVGR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8ADD: - /* TODO: Implement emulation of Q8ADD instruction. */ - MIPS_INVAL("OPC_MXU_Q8ADD"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool02 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL02| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool02(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_S32CPS: - /* TODO: Implement emulation of S32CPS instruction. */ - MIPS_INVAL("OPC_MXU_S32CPS"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16CPS: - /* TODO: Implement emulation of D16CPS instruction. */ - MIPS_INVAL("OPC_MXU_D16CPS"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8ABD: - /* TODO: Implement emulation of Q8ABD instruction. */ - MIPS_INVAL("OPC_MXU_Q8ABD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SAT: - /* TODO: Implement emulation of Q16SAT instruction. */ - MIPS_INVAL("OPC_MXU_Q16SAT"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool03 - * - * D16MULF: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |x x|on2|0 0 0 0| XRc | XRb | XRa |MXU__POOL03| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - * D16MULE: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |x x|on2| Xd | XRc | XRb | XRa |MXU__POOL03| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool03(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 24, 2); - - switch (opcode) { - case OPC_MXU_D16MULF: - /* TODO: Implement emulation of D16MULF instruction. */ - MIPS_INVAL("OPC_MXU_D16MULF"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MULE: - /* TODO: Implement emulation of D16MULE instruction. */ - MIPS_INVAL("OPC_MXU_D16MULE"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool04 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-+-------------------+-------+-----------+ - * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL04| - * +-----------+---------+-+-------------------+-------+-----------+ - * - */ static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 20, 1); @@ -26176,455 +25734,14 @@ static void decode_opc_mxu__pool04(CPUMIPSState = *env, DisasContext *ctx) } } =20 -/* - * - * Decode MXU pool05 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-+-------------------+-------+-----------+ - * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL05| - * +-----------+---------+-+-------------------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool05(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 20, 1); - - switch (opcode) { - case OPC_MXU_S32STD: - /* TODO: Implement emulation of S32STD instruction. */ - MIPS_INVAL("OPC_MXU_S32STD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32STDR: - /* TODO: Implement emulation of S32STDR instruction. */ - MIPS_INVAL("OPC_MXU_S32STDR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool06 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL06| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool06(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 10, 4); - - switch (opcode) { - case OPC_MXU_S32LDDV: - /* TODO: Implement emulation of S32LDDV instruction. */ - MIPS_INVAL("OPC_MXU_S32LDDV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32LDDVR: - /* TODO: Implement emulation of S32LDDVR instruction. */ - MIPS_INVAL("OPC_MXU_S32LDDVR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool07 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL07| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool07(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 10, 4); - - switch (opcode) { - case OPC_MXU_S32STDV: - /* TODO: Implement emulation of S32TDV instruction. */ - MIPS_INVAL("OPC_MXU_S32TDV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32STDVR: - /* TODO: Implement emulation of S32TDVR instruction. */ - MIPS_INVAL("OPC_MXU_S32TDVR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool08 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-+-------------------+-------+-----------+ - * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL08| - * +-----------+---------+-+-------------------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool08(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 20, 1); - - switch (opcode) { - case OPC_MXU_S32LDI: - /* TODO: Implement emulation of S32LDI instruction. */ - MIPS_INVAL("OPC_MXU_S32LDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32LDIR: - /* TODO: Implement emulation of S32LDIR instruction. */ - MIPS_INVAL("OPC_MXU_S32LDIR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool09 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-+-------------------+-------+-----------+ - * | SPECIAL2 | rb |x| s12 | XRa |MXU__POOL09| - * +-----------+---------+-+-------------------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool09(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 5, 0); - - switch (opcode) { - case OPC_MXU_S32SDI: - /* TODO: Implement emulation of S32SDI instruction. */ - MIPS_INVAL("OPC_MXU_S32SDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32SDIR: - /* TODO: Implement emulation of S32SDIR instruction. */ - MIPS_INVAL("OPC_MXU_S32SDIR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool10 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL10| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool10(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 5, 0); - - switch (opcode) { - case OPC_MXU_S32LDIV: - /* TODO: Implement emulation of S32LDIV instruction. */ - MIPS_INVAL("OPC_MXU_S32LDIV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32LDIVR: - /* TODO: Implement emulation of S32LDIVR instruction. */ - MIPS_INVAL("OPC_MXU_S32LDIVR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool11 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | rc |st2|x x x x| XRa |MXU__POOL11| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool11(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 10, 4); - - switch (opcode) { - case OPC_MXU_S32SDIV: - /* TODO: Implement emulation of S32SDIV instruction. */ - MIPS_INVAL("OPC_MXU_S32SDIV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32SDIVR: - /* TODO: Implement emulation of S32SDIVR instruction. */ - MIPS_INVAL("OPC_MXU_S32SDIVR"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool12 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |an2|x x| Xd | XRc | XRb | XRa |MXU__POOL12| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool12(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_D32ACC: - /* TODO: Implement emulation of D32ACC instruction. */ - MIPS_INVAL("OPC_MXU_D32ACC"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32ACCM: - /* TODO: Implement emulation of D32ACCM instruction. */ - MIPS_INVAL("OPC_MXU_D32ACCM"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32ASUM: - /* TODO: Implement emulation of D32ASUM instruction. */ - MIPS_INVAL("OPC_MXU_D32ASUM"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool13 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |en2|x x|0 0 0 0| XRc | XRb | XRa |MXU__POOL13| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool13(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_Q16ACC: - /* TODO: Implement emulation of Q16ACC instruction. */ - MIPS_INVAL("OPC_MXU_Q16ACC"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16ACCM: - /* TODO: Implement emulation of Q16ACCM instruction. */ - MIPS_INVAL("OPC_MXU_Q16ACCM"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16ASUM: - /* TODO: Implement emulation of Q16ASUM instruction. */ - MIPS_INVAL("OPC_MXU_Q16ASUM"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool14 - * - * Q8ADDE, Q8ACCE: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL14| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - * D8SUM, D8SUMC: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |en2|x x|0 0 0 0| XRc | XRb | XRa |MXU__POOL14| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool14(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_Q8ADDE: - /* TODO: Implement emulation of Q8ADDE instruction. */ - MIPS_INVAL("OPC_MXU_Q8ADDE"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D8SUM: - /* TODO: Implement emulation of D8SUM instruction. */ - MIPS_INVAL("OPC_MXU_D8SUM"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D8SUMC: - /* TODO: Implement emulation of D8SUMC instruction. */ - MIPS_INVAL("OPC_MXU_D8SUMC"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool15 - * - * S32MUL, S32MULU, S32EXTRV: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rs | rt |x x| XRd | XRa |MXU__POOL15| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - * S32EXTR: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+-------+-------+-----------+ - * | SPECIAL2 | rb | sft5 |x x| XRd | XRa |MXU__POOL15| - * +-----------+---------+---------+---+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool15(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 14, 2); - - switch (opcode) { - case OPC_MXU_S32MUL: - /* TODO: Implement emulation of S32MUL instruction. */ - MIPS_INVAL("OPC_MXU_S32MUL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MULU: - /* TODO: Implement emulation of S32MULU instruction. */ - MIPS_INVAL("OPC_MXU_S32MULU"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32EXTR: - /* TODO: Implement emulation of S32EXTR instruction. */ - MIPS_INVAL("OPC_MXU_S32EXTR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32EXTRV: - /* TODO: Implement emulation of S32EXTRV instruction. */ - MIPS_INVAL("OPC_MXU_S32EXTRV"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool16 - * - * D32SARW: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | rb |x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - * S32ALN: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | rs |x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - * S32ALNI: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+-----+---+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | s3 |0 0|x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+-----+---+-----+-------+-------+-------+-----------+ - * - * S32LUI: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+-----+---+-----+-------+---------------+-----------+ - * | SPECIAL2 |optn3|0 0|x x x| XRc | s8 |MXU__POOL16| - * +-----------+-----+---+-----+-------+---------------+-----------+ - * - * S32NOR, S32AND, S32OR, S32XOR: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); =20 switch (opcode) { - case OPC_MXU_D32SARW: - /* TODO: Implement emulation of D32SARW instruction. */ - MIPS_INVAL("OPC_MXU_D32SARW"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32ALN: - /* TODO: Implement emulation of S32ALN instruction. */ - MIPS_INVAL("OPC_MXU_S32ALN"); - gen_reserved_instruction(ctx); - break; case OPC_MXU_S32ALNI: gen_mxu_S32ALNI(ctx); break; - case OPC_MXU_S32LUI: - /* TODO: Implement emulation of S32LUI instruction. */ - MIPS_INVAL("OPC_MXU_S32LUI"); - gen_reserved_instruction(ctx); - break; case OPC_MXU_S32NOR: gen_mxu_S32NOR(ctx); break; @@ -26644,114 +25761,6 @@ static void decode_opc_mxu__pool16(CPUMIPSState *= env, DisasContext *ctx) } } =20 -/* - * - * Decode MXU pool17 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---+---------+-----+-----------+ - * | SPECIAL2 | rs | rt |0 0| rd |x x x|MXU__POOL15| - * +-----------+---------+---------+---+---------+-----+-----------+ - * - */ -static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 6, 2); - - switch (opcode) { - case OPC_MXU_LXW: - /* TODO: Implement emulation of LXW instruction. */ - MIPS_INVAL("OPC_MXU_LXW"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_LXH: - /* TODO: Implement emulation of LXH instruction. */ - MIPS_INVAL("OPC_MXU_LXH"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_LXHU: - /* TODO: Implement emulation of LXHU instruction. */ - MIPS_INVAL("OPC_MXU_LXHU"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_LXB: - /* TODO: Implement emulation of LXB instruction. */ - MIPS_INVAL("OPC_MXU_LXB"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_LXBU: - /* TODO: Implement emulation of LXBU instruction. */ - MIPS_INVAL("OPC_MXU_LXBU"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} -/* - * - * Decode MXU pool18 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL18| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_D32SLLV: - /* TODO: Implement emulation of D32SLLV instruction. */ - MIPS_INVAL("OPC_MXU_D32SLLV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SLRV: - /* TODO: Implement emulation of D32SLRV instruction. */ - MIPS_INVAL("OPC_MXU_D32SLRV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SARV: - /* TODO: Implement emulation of D32SARV instruction. */ - MIPS_INVAL("OPC_MXU_D32SARV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SLLV: - /* TODO: Implement emulation of Q16SLLV instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLLV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SLRV: - /* TODO: Implement emulation of Q16SLRV instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLRV"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SARV: - /* TODO: Implement emulation of Q16SARV instruction. */ - MIPS_INVAL("OPC_MXU_Q16SARV"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool19 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL19| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 22, 2); @@ -26768,107 +25777,11 @@ static void decode_opc_mxu__pool19(CPUMIPSState = *env, DisasContext *ctx) } } =20 -/* - * - * Decode MXU pool20 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL20| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_Q8MOVZ: - /* TODO: Implement emulation of Q8MOVZ instruction. */ - MIPS_INVAL("OPC_MXU_Q8MOVZ"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8MOVN: - /* TODO: Implement emulation of Q8MOVN instruction. */ - MIPS_INVAL("OPC_MXU_Q8MOVN"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MOVZ: - /* TODO: Implement emulation of D16MOVZ instruction. */ - MIPS_INVAL("OPC_MXU_D16MOVZ"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MOVN: - /* TODO: Implement emulation of D16MOVN instruction. */ - MIPS_INVAL("OPC_MXU_D16MOVN"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MOVZ: - /* TODO: Implement emulation of S32MOVZ instruction. */ - MIPS_INVAL("OPC_MXU_S32MOVZ"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MOVN: - /* TODO: Implement emulation of S32MOVN instruction. */ - MIPS_INVAL("OPC_MXU_S32MOVN"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -/* - * - * Decode MXU pool21 - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL21| - * +-----------+---+---+-------+-------+-------+-------+-----------+ - * - */ -static void decode_opc_mxu__pool21(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_Q8MAC: - /* TODO: Implement emulation of Q8MAC instruction. */ - MIPS_INVAL("OPC_MXU_Q8MAC"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8MACSU: - /* TODO: Implement emulation of Q8MACSU instruction. */ - MIPS_INVAL("OPC_MXU_Q8MACSU"); - gen_reserved_instruction(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - - /* * Main MXU decoding function - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------------------------------------+-----------+ - * | SPECIAL2 | |x x x x x x| - * +-----------+---------------------------------------+-----------+ - * */ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) { - /* - * TODO: Investigate necessity of including handling of - * CLZ, CLO, SDBB in this function, as they belong to - * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs. - */ uint32_t opcode =3D extract32(ctx->opcode, 0, 6); =20 if (opcode =3D=3D OPC__MXU_MUL) { @@ -26903,226 +25816,27 @@ static void decode_opc_mxu(CPUMIPSState *env, Di= sasContext *ctx) tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit); =20 switch (opcode) { - case OPC_MXU_S32MADD: - /* TODO: Implement emulation of S32MADD instruction. */ - MIPS_INVAL("OPC_MXU_S32MADD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MADDU: - /* TODO: Implement emulation of S32MADDU instruction. */ - MIPS_INVAL("OPC_MXU_S32MADDU"); - gen_reserved_instruction(ctx); - break; case OPC_MXU__POOL00: decode_opc_mxu__pool00(env, ctx); break; - case OPC_MXU_S32MSUB: - /* TODO: Implement emulation of S32MSUB instruction. */ - MIPS_INVAL("OPC_MXU_S32MSUB"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32MSUBU: - /* TODO: Implement emulation of S32MSUBU instruction. */ - MIPS_INVAL("OPC_MXU_S32MSUBU"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU__POOL01: - decode_opc_mxu__pool01(env, ctx); - break; - case OPC_MXU__POOL02: - decode_opc_mxu__pool02(env, ctx); - break; case OPC_MXU_D16MUL: gen_mxu_d16mul(ctx); break; - case OPC_MXU__POOL03: - decode_opc_mxu__pool03(env, ctx); - break; case OPC_MXU_D16MAC: gen_mxu_d16mac(ctx); break; - case OPC_MXU_D16MACF: - /* TODO: Implement emulation of D16MACF instruction. */ - MIPS_INVAL("OPC_MXU_D16MACF"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MADL: - /* TODO: Implement emulation of D16MADL instruction. */ - MIPS_INVAL("OPC_MXU_D16MADL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S16MAD: - /* TODO: Implement emulation of S16MAD instruction. */ - MIPS_INVAL("OPC_MXU_S16MAD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16ADD: - /* TODO: Implement emulation of Q16ADD instruction. */ - MIPS_INVAL("OPC_MXU_Q16ADD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D16MACE: - /* TODO: Implement emulation of D16MACE instruction. */ - MIPS_INVAL("OPC_MXU_D16MACE"); - gen_reserved_instruction(ctx); - break; case OPC_MXU__POOL04: decode_opc_mxu__pool04(env, ctx); break; - case OPC_MXU__POOL05: - decode_opc_mxu__pool05(env, ctx); - break; - case OPC_MXU__POOL06: - decode_opc_mxu__pool06(env, ctx); - break; - case OPC_MXU__POOL07: - decode_opc_mxu__pool07(env, ctx); - break; - case OPC_MXU__POOL08: - decode_opc_mxu__pool08(env, ctx); - break; - case OPC_MXU__POOL09: - decode_opc_mxu__pool09(env, ctx); - break; - case OPC_MXU__POOL10: - decode_opc_mxu__pool10(env, ctx); - break; - case OPC_MXU__POOL11: - decode_opc_mxu__pool11(env, ctx); - break; - case OPC_MXU_D32ADD: - /* TODO: Implement emulation of D32ADD instruction. */ - MIPS_INVAL("OPC_MXU_D32ADD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU__POOL12: - decode_opc_mxu__pool12(env, ctx); - break; - case OPC_MXU__POOL13: - decode_opc_mxu__pool13(env, ctx); - break; - case OPC_MXU__POOL14: - decode_opc_mxu__pool14(env, ctx); - break; - case OPC_MXU_Q8ACCE: - /* TODO: Implement emulation of Q8ACCE instruction. */ - MIPS_INVAL("OPC_MXU_Q8ACCE"); - gen_reserved_instruction(ctx); - break; case OPC_MXU_S8LDD: gen_mxu_s8ldd(ctx); break; - case OPC_MXU_S8STD: - /* TODO: Implement emulation of S8STD instruction. */ - MIPS_INVAL("OPC_MXU_S8STD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S8LDI: - /* TODO: Implement emulation of S8LDI instruction. */ - MIPS_INVAL("OPC_MXU_S8LDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S8SDI: - /* TODO: Implement emulation of S8SDI instruction. */ - MIPS_INVAL("OPC_MXU_S8SDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU__POOL15: - decode_opc_mxu__pool15(env, ctx); - break; case OPC_MXU__POOL16: decode_opc_mxu__pool16(env, ctx); break; - case OPC_MXU__POOL17: - decode_opc_mxu__pool17(env, ctx); - break; - case OPC_MXU_S16LDD: - /* TODO: Implement emulation of S16LDD instruction. */ - MIPS_INVAL("OPC_MXU_S16LDD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S16STD: - /* TODO: Implement emulation of S16STD instruction. */ - MIPS_INVAL("OPC_MXU_S16STD"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S16LDI: - /* TODO: Implement emulation of S16LDI instruction. */ - MIPS_INVAL("OPC_MXU_S16LDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S16SDI: - /* TODO: Implement emulation of S16SDI instruction. */ - MIPS_INVAL("OPC_MXU_S16SDI"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SLL: - /* TODO: Implement emulation of D32SLL instruction. */ - MIPS_INVAL("OPC_MXU_D32SLL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SLR: - /* TODO: Implement emulation of D32SLR instruction. */ - MIPS_INVAL("OPC_MXU_D32SLR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SARL: - /* TODO: Implement emulation of D32SARL instruction. */ - MIPS_INVAL("OPC_MXU_D32SARL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_D32SAR: - /* TODO: Implement emulation of D32SAR instruction. */ - MIPS_INVAL("OPC_MXU_D32SAR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SLL: - /* TODO: Implement emulation of Q16SLL instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q16SLR: - /* TODO: Implement emulation of Q16SLR instruction. */ - MIPS_INVAL("OPC_MXU_Q16SLR"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU__POOL18: - decode_opc_mxu__pool18(env, ctx); - break; - case OPC_MXU_Q16SAR: - /* TODO: Implement emulation of Q16SAR instruction. */ - MIPS_INVAL("OPC_MXU_Q16SAR"); - gen_reserved_instruction(ctx); - break; case OPC_MXU__POOL19: decode_opc_mxu__pool19(env, ctx); break; - case OPC_MXU__POOL20: - decode_opc_mxu__pool20(env, ctx); - break; - case OPC_MXU__POOL21: - decode_opc_mxu__pool21(env, ctx); - break; - case OPC_MXU_Q16SCOP: - /* TODO: Implement emulation of Q16SCOP instruction. */ - MIPS_INVAL("OPC_MXU_Q16SCOP"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8MADL: - /* TODO: Implement emulation of Q8MADL instruction. */ - MIPS_INVAL("OPC_MXU_Q8MADL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_S32SFL: - /* TODO: Implement emulation of S32SFL instruction. */ - MIPS_INVAL("OPC_MXU_S32SFL"); - gen_reserved_instruction(ctx); - break; - case OPC_MXU_Q8SAD: - /* TODO: Implement emulation of Q8SAD instruction. */ - MIPS_INVAL("OPC_MXU_Q8SAD"); - gen_reserved_instruction(ctx); - break; default: MIPS_INVAL("decode_opc_mxu"); gen_reserved_instruction(ctx); --=20 2.26.2 From nobody Mon Feb 9 14:35:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.54 as permitted sender) client-ip=209.85.218.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614033562; cv=none; d=zohomail.com; s=zohoarc; b=HsFMRonoZv9IDihS0jiRGoshnuuyBZTxovBuUEWy9dQtVt4vTOZQSdrUp/SNwEQC2Y1cmrvOmvJnn0JPMZJ7tMWIBzR9IOBOZebBrEaLRSDgQhPaWCVhrcEGu2Cn8xFrsqil0EVkcG29X/14rJ8iJeUDqJQ4J4CU73p7WByBG0g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614033562; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cPqTdlRSqWnikQijLksatBH+7i1gXhB78//9AOt2jP4=; b=HcUS0vCzAWPgyvHPZNCQHEHuZctjs8K/nTZWv2VyfPDAk8jONBzM1XZCCEfctGSKUIB63HzcXoS5gS7sey+B4JO/3u6hdgS/aLms/8ysjrJ0ooidRnRVT+LEF2W7715FaZpsdPWp8f66AMU/nROJF6YEoF8ygLQ48GE0B/JiwvQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) by mx.zohomail.com with SMTPS id 1614033562070449.35999998568343; Mon, 22 Feb 2021 14:39:22 -0800 (PST) Received: by mail-ej1-f54.google.com with SMTP id j6so4695554eja.12 for ; Mon, 22 Feb 2021 14:39:21 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id t8sm6020479edv.16.2021.02.22.14.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cPqTdlRSqWnikQijLksatBH+7i1gXhB78//9AOt2jP4=; b=a/01CO6tXJxmMY3kw+cP21Liy1AZQZTARkuvs0tlrbaVWv+hv1Gr+NRew+rTs9AZc7 hcul3CTLE2f99YV9wb/Xq5/hdg89YQGRGhnKfttnFdwNWN5JzDh3Lghl8Ic64Jc4J0CF WkoJPBRhxzLuzfQBQGib524mF4tLZZHdIhSBADHm0qjnNh20i3Y5XC31ZQeLRY8r8m6/ FgXj0vmBZsnT8n+18TdgGkc/8+RJTF67dVtMSApqQUoF1KocjwYgM6dbGqIgpbkFUhBR pCkYLOqhUNYbBvpDgG+IBcDqE9y8Mm9Zn7IcaliRvM0vq/m3C/9LRM+d1GsUPNsVsMhh DnSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cPqTdlRSqWnikQijLksatBH+7i1gXhB78//9AOt2jP4=; b=PVtMYVn8PKsPzzm3s2aJ/p90McFt55ZIE6Pdo8XELw7WhkI1afFu+ouMDwJ+Xsqq1k vHVGXp3iXy1Vht+biMnlnVL69jE55GqMZBBkAO43X4iPS2jMOOdRYZnbuE8bsR//vzxO gw0Cl8qeuFyAZtc9AJiAj7YvdlhuMLyIZZlbU8xHw4tntfnXE7JIQ0Au4NCg/V5v4qh5 WmoNrKMnERemLnDM73tHPl/raI1wfB09Wz17Ij3GCNdJHLQdZNKncJ3/2ji/q175J0Dq jB2qCBzXr2rpaT9+rDmb7HBg/5zbQR6VNZr6OCY3wKBchTTxYZUXwUBWKi+uIzNR60pf Nomg== X-Gm-Message-State: AOAM531WSvSr/OvfbAMGO4I7lns0klBMsOBaFd+1oCbyljnL3WTy3ymP klaakrQETj7s5KPiUwxiVlQ= X-Google-Smtp-Source: ABdhPJxTH4vuh1nVGvBpb8QkyYSWx3EcK/jikVJr8pUegjBFk2PYReAGEJnUBJXrci++4aA13keOcQ== X-Received: by 2002:a17:907:da3:: with SMTP id go35mr22123070ejc.26.1614033560369; Mon, 22 Feb 2021 14:39:20 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 03/10] target/mips: Remove unused CPUMIPSState* from MXU functions Date: Mon, 22 Feb 2021 23:38:54 +0100 Message-Id: <20210222223901.2792336-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) None of these MXU functions use their CPUMIPSState* env argument, remove it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a53ce6adb9a..6f5ccd667da 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25694,7 +25694,7 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ =20 -static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool00(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); =20 @@ -25718,7 +25718,7 @@ static void decode_opc_mxu__pool00(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool04(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 20, 1); =20 @@ -25734,7 +25734,7 @@ static void decode_opc_mxu__pool04(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool16(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 18, 3); =20 @@ -25761,7 +25761,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool19(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 22, 2); =20 @@ -25780,7 +25780,7 @@ static void decode_opc_mxu__pool19(CPUMIPSState *en= v, DisasContext *ctx) /* * Main MXU decoding function */ -static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu(DisasContext *ctx) { uint32_t opcode =3D extract32(ctx->opcode, 0, 6); =20 @@ -25817,7 +25817,7 @@ static void decode_opc_mxu(CPUMIPSState *env, Disas= Context *ctx) =20 switch (opcode) { case OPC_MXU__POOL00: - decode_opc_mxu__pool00(env, ctx); + decode_opc_mxu__pool00(ctx); break; case OPC_MXU_D16MUL: gen_mxu_d16mul(ctx); @@ -25826,16 +25826,16 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) gen_mxu_d16mac(ctx); break; case OPC_MXU__POOL04: - decode_opc_mxu__pool04(env, ctx); + decode_opc_mxu__pool04(ctx); break; case OPC_MXU_S8LDD: gen_mxu_s8ldd(ctx); break; case OPC_MXU__POOL16: - decode_opc_mxu__pool16(env, ctx); + decode_opc_mxu__pool16(ctx); break; case OPC_MXU__POOL19: - decode_opc_mxu__pool19(env, ctx); + decode_opc_mxu__pool19(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); @@ -26995,7 +26995,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) #endif #if !defined(TARGET_MIPS64) if (ctx->insn_flags & ASE_MXU) { - decode_opc_mxu(env, ctx); + decode_opc_mxu(ctx); break; } #endif --=20 2.26.2 From nobody Mon Feb 9 14:35:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.41 as permitted sender) client-ip=209.85.208.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614033568; cv=none; d=zohomail.com; s=zohoarc; b=Tw/gQefCZnQzcGV/3oMjJsIAIl++tIx4tLC1rlLO3zlxw1sSySGimKRwj1WpfWIzL6p+17+/hVAF/D91dfOH4sJRRrLkfSjG32URFpsHaGNgfkZLFGXPoc2eUqkIlwFeZIvB0Fo5nDDAJNggroV3dlos+9a1HzSgHFbZdU137cg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614033568; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xZ1YSX9ym8FOAoKObo8vcKmeS2B4Q8FgYrw++zm+/vQ=; b=FPqAzy+vGb+IWBij984YdPC2QLhqSB5tg8vXalG+3mEGKxy1FoooYt5T40mV36RpzmTb2NW2U2Vz46QjX21yN1EbXHvCloSD+nWA/cmhGCOrh6QMey9VhQs6qnzUoCHK+Y0tk77AOFmPmGYj+vWrXNfInrXcRAY4UTFwGqysQCg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) by mx.zohomail.com with SMTPS id 1614033568320661.9088320053474; Mon, 22 Feb 2021 14:39:28 -0800 (PST) Received: by mail-ed1-f41.google.com with SMTP id n1so23947637edv.2 for ; Mon, 22 Feb 2021 14:39:26 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id r23sm380098eds.76.2021.02.22.14.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xZ1YSX9ym8FOAoKObo8vcKmeS2B4Q8FgYrw++zm+/vQ=; b=qc1kVVUOf5dviUdeMihuPMM9PcIC/x2aPbe8ybOT54CTKwjHs9g+Wq1jL801s+xLKL K4u/xvZIzQ2LoAngG/r1onlHtRxrDwlG7Twghd3vZZiC6QLIzBZPKwaevIdvrohngWdT 74BGR5y5GbaEEHT+8mg/pXiDUOJK0njo0NoqbTwGl4LihWpVT6FYDVx0MOtC/4nW8qQJ 1C28aZEKfZtBUc+vj3WOhz8pEwFzU8T+aNByDTbbt0TzY3PIEl+ii0vw0Olsn8ym8VSe yep7cvvTuGhxOTIU10grEdD+h6WzrEVfty8+s3fxJP6jIPcQCZjrq8zwJbIgXNwDhlO3 RGVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xZ1YSX9ym8FOAoKObo8vcKmeS2B4Q8FgYrw++zm+/vQ=; b=bMzLferqTmRl4eFca9OfejFrrxXr3htRc+LHUvm0hKgl3nFpMVz5t4fIsadMc/tg8X xeIXNKzJYUpWZGIa5RqYHCNS/+62+6cPiMsTpD7o3KxyoDZ7nc9IZNkhJsp+lKDPPW2O D1qlR1ZmFOGe7aab4XtJz0pTGsLuhyefZ4RYnbUZGMu7tYtSQrESJ5rc+mQg4CHEePXp nRj3y+7Qvvm5VLulPvMuoYU8qc7/EZo9MCoiZL9E5fn/bjDSTF69lBHQ+Vq7i2x3D3zh AheM7lZ2Sn4EoJ2hAn3h6Olz2BrL11coGM8D5C9xE8D//MpL4LXXwBMUhyEunEf5OdDU uPoA== X-Gm-Message-State: AOAM532TEXE06ktYDOMdLg+FWM/3hey3xwpmNg5W6OkHa55gqF61+WT0 Gth7ItJ19kSvYwmW3/sONzgVR8m3e6U= X-Google-Smtp-Source: ABdhPJyEfLuNf8OcS9Ls0PC4rSG3qmRxMtlXDJxfVoPCU1A9MDKMJctDuXitzmv/QGJ13H+InbqZWA== X-Received: by 2002:aa7:c9c9:: with SMTP id i9mr24540265edt.160.1614033565561; Mon, 22 Feb 2021 14:39:25 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 04/10] target/mips: Pass instruction opcode to decode_opc_mxu() Date: Mon, 22 Feb 2021 23:38:55 +0100 Message-Id: <20210222223901.2792336-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) In the next commit we'll make decode_opc_mxu() match decodetree prototype by returning a boolean. First pass ctx->opcode as an argument. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6f5ccd667da..9e875fa4a25 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25780,17 +25780,17 @@ static void decode_opc_mxu__pool19(DisasContext *= ctx) /* * Main MXU decoding function */ -static void decode_opc_mxu(DisasContext *ctx) +static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) { - uint32_t opcode =3D extract32(ctx->opcode, 0, 6); + uint32_t opcode =3D extract32(insn, 0, 6); =20 if (opcode =3D=3D OPC__MXU_MUL) { uint32_t rs, rt, rd, op1; =20 - rs =3D extract32(ctx->opcode, 21, 5); - rt =3D extract32(ctx->opcode, 16, 5); - rd =3D extract32(ctx->opcode, 11, 5); - op1 =3D MASK_SPECIAL2(ctx->opcode); + rs =3D extract32(insn, 21, 5); + rt =3D extract32(insn, 16, 5); + rd =3D extract32(insn, 11, 5); + op1 =3D MASK_SPECIAL2(insn); =20 gen_arith(ctx, op1, rd, rs, rt); =20 @@ -26995,7 +26995,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) #endif #if !defined(TARGET_MIPS64) if (ctx->insn_flags & ASE_MXU) { - decode_opc_mxu(ctx); + decode_opc_mxu(ctx, ctx->opcode); break; } #endif --=20 2.26.2 From nobody Mon Feb 9 14:35:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.47 as permitted sender) client-ip=209.85.208.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614033573; cv=none; d=zohomail.com; s=zohoarc; b=LurQhImEVioYvUuns803BahYzd3oxGqitUSJEY5y/rezg4rBS5VHaTAVFkY6M230POEWWOQDs4oZ0T61OHKRUoOEb77xkwL22bsbIB6RRN6qe0bJQoBBgr5bRuOR/Az0XKNAQoZgjasbUoV43D33exGdByR9nUDVl5/X/8Qrmcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614033573; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hhlpouH+U3rNOrspZgB0QgIcQmhAf1zcqiPcomofBiI=; b=WKiR5bzkCsyPCRBw5Evg+J2QhY3Tb77QQaYgRHZSRGxrlZKG0kF/QfR8rH0qYhVVDMrGRLAHQcQc1KcxTL6Vl6saOrx03e89yD53wIbvPC/Y8n1stAWemuOjEBAzt82HaevGALrHKmG6+/C/zMhDGtHUf/0gUMmX1sZHuyieVX0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) by mx.zohomail.com with SMTPS id 1614033572648896.5889563316454; Mon, 22 Feb 2021 14:39:32 -0800 (PST) Received: by mail-ed1-f47.google.com with SMTP id d2so23862027edq.10 for ; Mon, 22 Feb 2021 14:39:32 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id x17sm13176654edq.42.2021.02.22.14.39.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hhlpouH+U3rNOrspZgB0QgIcQmhAf1zcqiPcomofBiI=; b=UkHdRzu1SPs4TbCGedYqhjNBjNrFEYSGbqLo4NSxdLNLZaHEYC7LQD5UPUeElpD8vs KHc13V0KbINvaKqtM4cSou0XHW40gpC7fK6M5lJ4u3RsD7C57kM02mMarXBwMIJEkIWF POBBpDD/NRwrC4C85N+ICjxN6zuQ7mRD6Lyya/LgnjgKr4mDw7MPhoZ5Fw2HJuZctX1U yft2JKx1UXVEgNsL9C5mJiTBMnUwHVY6WrxgaPYqZzNjNRQ2myxPAMozVnI3MypdmFij 1Yp2Cb3EbZ+XQmgKNH0iN2rqRSxqN8OROWe5SdcwI08SNdW2drgM3NP0G1tjrgZ/bmGc TDAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=hhlpouH+U3rNOrspZgB0QgIcQmhAf1zcqiPcomofBiI=; b=GZDM+nFlhoC9uSz0sguyVxdugSNBeKIt3JuQ/tBn6iElzPXAw+R43ajupsrpXqlsEG qv860gSJU1XG7hex8dVVuQjlODT1tIdNLWsfuAvtuzgKF9CwPIzeUgBNr31p0zKcO9Tp 2aD9wyDwzh+5PSEdWz8fmIh1yJ8MFcu9z2w/GkNdg15WttVtvwjrrsec9BUX/cwh/Px7 uVsGbP/CF0976NDsUUeBJrJaKo1+oLO3wWmp1ImA/MVcvUDOzV3V1a+59ooVD88l4QLR gHlcqaGAfkYTfKxiubB6kt8LJGr+0HAYUfz7stUznQQoK1euUBYOdqRs70J0kDIJhlR3 KjIQ== X-Gm-Message-State: AOAM530TL1cQk+GHq/hZ49hxyH9beiyoM3veH64pbhna/9lLZDK2IXZ7 3NaM8Sw1UHLkXgHBCUvH7KmIct/Gfbg= X-Google-Smtp-Source: ABdhPJzZJKd++38iXJTzzoH/HCYOR9QnGGAiKOvFY7VFGs6kBEXxLbKhLePddPMuiRZCPzCm8ruFIg== X-Received: by 2002:aa7:dace:: with SMTP id x14mr4903561eds.142.1614033570925; Mon, 22 Feb 2021 14:39:30 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 05/10] target/mips: Extract decode_ase_mxu() from decode_opc_mxu() Date: Mon, 22 Feb 2021 23:38:56 +0100 Message-Id: <20210222223901.2792336-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To easily convert MXU code to decodetree, extract decode_ase_mxu() from decode_opc_mxu(), making it return a boolean. We will keep decode_opc_mxu() in the translate.c unit because it calls gen_arith(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 45 ++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 9e875fa4a25..6f853fcdcce 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25777,34 +25777,18 @@ static void decode_opc_mxu__pool19(DisasContext *= ctx) } } =20 -/* - * Main MXU decoding function - */ -static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) +static bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) { uint32_t opcode =3D extract32(insn, 0, 6); =20 - if (opcode =3D=3D OPC__MXU_MUL) { - uint32_t rs, rt, rd, op1; - - rs =3D extract32(insn, 21, 5); - rt =3D extract32(insn, 16, 5); - rd =3D extract32(insn, 11, 5); - op1 =3D MASK_SPECIAL2(insn); - - gen_arith(ctx, op1, rd, rs, rt); - - return; - } - if (opcode =3D=3D OPC_MXU_S32M2I) { gen_mxu_s32m2i(ctx); - return; + return true; } =20 if (opcode =3D=3D OPC_MXU_S32I2M) { gen_mxu_s32i2m(ctx); - return; + return true; } =20 { @@ -25845,6 +25829,29 @@ static void decode_opc_mxu(DisasContext *ctx, uint= 32_t insn) gen_set_label(l_exit); tcg_temp_free(t_mxu_cr); } + + return true; +} + +/* + * Main MXU decoding function + */ +static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) +{ + if (extract32(insn, 0, 6) =3D=3D OPC__MXU_MUL) { + uint32_t rs, rt, rd, op1; + + rs =3D extract32(insn, 21, 5); + rt =3D extract32(insn, 16, 5); + rd =3D extract32(insn, 11, 5); + op1 =3D MASK_SPECIAL2(insn); + + gen_arith(ctx, op1, rd, rs, rt); + + return; + } + + decode_ase_mxu(ctx, insn); } =20 #endif /* !defined(TARGET_MIPS64) */ --=20 2.26.2 From nobody Mon Feb 9 14:35:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.41 as permitted sender) client-ip=209.85.208.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614033578; cv=none; d=zohomail.com; s=zohoarc; b=avaj9fXWAtQ5CVgGJyWhzlU4/u85Fn5nuJEMjfNBb61QRpePt85ugFPXOUcJ0CKpUpHg3x8Hz+GzIxcdgYnFfoK+ocNCPikeMfViMN6FwHrNHjv+4kLI8UPER69scIMvsA0w7RQITF7fr7mrSDUWJzVQcaC8ftyBYP09eXB2OHI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614033578; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YUh8CuRVecN07OYPv+7aGP1f69kub+P2q8KnhbsjCeI=; b=CzO6jKpAd3PayfOAnajWC8cuIVliDaMP4emzhCMlj4gOPXLlUMWGpr5CCt5NSKJxWLmzQD6vfvVeRmAgm1asMygr4VOJblr3cgZFzNQg8NpNZhlhEQ9i7Zteu/TeXMzpF1L8NXmrUVfiK4yBOuK2sH21XHZqaWlQuS900lRH/Z4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) by mx.zohomail.com with SMTPS id 1614033578129428.42364104042065; Mon, 22 Feb 2021 14:39:38 -0800 (PST) Received: by mail-ed1-f41.google.com with SMTP id h19so441820edb.9 for ; Mon, 22 Feb 2021 14:39:37 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id la24sm10957452ejb.18.2021.02.22.14.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YUh8CuRVecN07OYPv+7aGP1f69kub+P2q8KnhbsjCeI=; b=tElMSdp2VdxlBIZssNBCYQtvbIoj4k34J4TXgVq+87kKlFI5vz3Db9xv6lZ+hfsBLK 6k97IS01XhJSCqGQfeA3M07NhPCuZV0Xg/Zw5uoy65Cy17/SceoiKsIlDLeMHuDzB2X8 cliPijlBEwBavtcY1P8OkRIH9nHYghMMkGRNSJvZ+WmRNB20ZqToT7/jPX/e2N7psFxo h9b9/XIWxq7lgmBjtZRTdBdGPj52kT/PYQOOpcu2S9EO+VbR59URkl0OYiTCYCRGAc8k owc6YVjtCYiZFDq4mfLMOgUoqkCtIC21ZkLaPUlxbxnm+AXkcY8HLn1qaWd6Ovlc226z BS4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YUh8CuRVecN07OYPv+7aGP1f69kub+P2q8KnhbsjCeI=; b=rb2HQn33oXnAaqteVYrjpXUbQmkZap+G89V/itB2fIYss22hVZF9W4WQv7iewgtXHm 7LTDFu4qsFIjmvrF8V6cTSbbMS1Dr/Nc9r+N6RP87Dgzr2LuvbndtAUIU1L4XnhJvPsq l/jWjZbxaLcSP5j7c6l2l1AgNicbb/Gl6MY2oWd0yZjdmNXoOaEJBhQf+6esI+Pp+6vA 6kMzzn8Ie+46RnuDspSYhvv6E2EC5krnI5Ww8qSM2XcP82NNGPSrumBlX803UC0M36pN LB38TRvPVkOY3UkwIS3sIWqV8ffYkFNx0gnTp1Uo+OJzDMcLduWjmdXGUXkHUFSIudXk 1xgQ== X-Gm-Message-State: AOAM532Yg9ffRlqFcHra/65itYLHm1glWmiHBya2Bu7WtA8gx0ncjdhi lKUJ0x+c1UoiGobq8SrRtS8= X-Google-Smtp-Source: ABdhPJyl2M9BNNtYZ2nUQYetDZjEMru931hLF2ub8vnXFgokVObIlyZOeZV7U+ZcXcZBjJpD60OSHQ== X-Received: by 2002:a05:6402:3d3:: with SMTP id t19mr16642212edw.124.1614033576336; Mon, 22 Feb 2021 14:39:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 06/10] target/mips: Use OPC_MUL instead of OPC__MXU_MUL Date: Mon, 22 Feb 2021 23:38:57 +0100 Message-Id: <20210222223901.2792336-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We already have a macro and definition to extract / check the Special2 MUL opcode. Use it instead of the unnecessary OPC__MXU_MUL macro. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 6f853fcdcce..c897f3900d8 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1464,7 +1464,6 @@ enum { */ =20 enum { - OPC__MXU_MUL =3D 0x02, OPC_MXU__POOL00 =3D 0x03, OPC_MXU_D16MUL =3D 0x08, OPC_MXU_D16MAC =3D 0x0A, @@ -25838,7 +25837,7 @@ static bool decode_ase_mxu(DisasContext *ctx, uint3= 2_t insn) */ static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) { - if (extract32(insn, 0, 6) =3D=3D OPC__MXU_MUL) { + if (MASK_SPECIAL2(insn) =3D=3D OPC_MUL) { uint32_t rs, rt, rd, op1; =20 rs =3D extract32(insn, 21, 5); --=20 2.26.2 From nobody Mon Feb 9 14:35:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.54 as permitted sender) client-ip=209.85.208.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1614033584; cv=none; d=zohomail.com; s=zohoarc; b=EJGB/Pkojcx6f0B5Lyiip9CR6wqG4t1mcB1p6ebaTTT2DZwc4lFnQzu9bM+IBS90/ISoiseJmQWZcvIVWa928uswkk7Xf9wJGDjmtXK4TrXUpFKz5aGXk723j8oz/i9vkouLbnutTBeqBtY8YnMuuAzjAiz0SpxbyqfUjEbYIGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614033584; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IX1y81rCSxsmxkLrafmm9o5V9M7N65ucGEOOogWT+Hk=; b=TF4YApiNObOaNpU6vJP2/pUZCezRGpx6U+a5OuYY7X5ABYPgq7r3/MfnvYzs9DqOahS0SALY8hpIaMpEuHAI26i3HpVZ1kKpBXFCj3Nn9WaLGBK3ogQTw1mhpa2WSfzc2BdpjGKcACDSlz63xtq2sOgPGPflIAy0azF0XDLMvZo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) by mx.zohomail.com with SMTPS id 1614033583601292.10752302575634; Mon, 22 Feb 2021 14:39:43 -0800 (PST) Received: by mail-ed1-f54.google.com with SMTP id c6so24012696ede.0 for ; Mon, 22 Feb 2021 14:39:43 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract the MXU register initialization code from mips_tcg_init() as a new mxu_translate_init() helper Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index c897f3900d8..52a7005e18f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2045,7 +2045,20 @@ static const char * const mxuregnames[] =3D { "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", }; -#endif + +static void mxu_translate_init(void) +{ + for (unsigned i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { + mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.m= xu_gpr[i]), + mxuregnames[i]); + } + + mxu_CR =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.mxu_cr), + mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); +} +#endif /* defined(TARGET_MIPS64) */ =20 /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) @@ -28064,16 +28077,7 @@ void mips_tcg_init(void) "llval"); =20 #if !defined(TARGET_MIPS64) - for (i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { - mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, - active_tc.mxu_gpr[i]), - mxuregnames[i]); - } - - mxu_CR =3D tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, active_tc.mxu_cr), - mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); + mxu_translate_init(); #endif /* !TARGET_MIPS64 */ } =20 --=20 2.26.2 From nobody Mon Feb 9 14:35:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.54 as permitted sender) client-ip=209.85.218.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id i18sm12889735edt.68.2021.02.22.14.39.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w42rjh8kWYW1iTxLcpjhEOnKOinsG7BggxSZMmsgS4w=; b=W6tgJkm0RJAwRYVBa5VhrxiAmPm0L1zm9PtXkWazVXhAWT9tF5CN9CtkW5LWJKaVbQ DHfCLBDBhRYjsWbYeQZRyL19uQzFf9gnVvsHrNuqB6x9P7yRhzzcd4yAp04Vzpw+cGhF uKwowmCwnAJYEqNW3MTFzKKFUMS5fofA4N2R0RhmOouxC97VGlzFB+ggb1mNdt+oJAuw Fn9Sl+gJ3ZWVbzyWFVEoSq8xt9+/zW8zw+UBcKcHAvj57QZCek48+yAjZvC3UV1WHH5P cKpwPrLUJUQypq8a9gexGH8uPtjw5aiOzyZ1nHktPl+Qx3vbuX96abfaRH79bRCCrGyx GPLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=w42rjh8kWYW1iTxLcpjhEOnKOinsG7BggxSZMmsgS4w=; b=HB7EJGSr0mAVQCzKxFtj6U+ia8SQIHD1fQNQLvcElRwBYToyRm84CwCJ7iU0WvfW/k zQPom/gbL4FbSzfJtH+vnYWrPwnF6H6NdIolvbIUielH7fYLuAJbmhn69nx67WHRqSrR KsdBnXkSFVrgSpBqx9PvM0PuuZOf185yDvStBtzvIy6UuH4gNyXaMhrmGe46bGCRENh4 b9M3go3XH6l74ik1cJuKw+a0rSpo+Ft3ctfVUMYHYrTmdCw7GmVX8nF5PXvPRK1ycBY2 I4AR7Yr017hzxWcVrBXkgoKiilB1cQSlG0y2NFe4O6yzsybN8w2PrLlmjJ5uCp+hstTM 4P5w== X-Gm-Message-State: AOAM5306wz/1rbKO+6TenSxVuryColuGg0R9eSlboAKP2jhwobAMpuJ2 tLuxtCBoeYHjS+8sEMBoJKY= X-Google-Smtp-Source: ABdhPJyTM+qFfnNHDD5/UgxzdPUcmBbxwo7hqSNmiaTcUYoo0F3VzS83rFuwImcIVOdywxA4+S+kfA== X-Received: by 2002:a17:907:104e:: with SMTP id oy14mr22571144ejb.218.1614033587407; Mon, 22 Feb 2021 14:39:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 08/10] target/mips: Make mxu_translate_init() / decode_ase_mxu() proto public Date: Mon, 22 Feb 2021 23:38:59 +0100 Message-Id: <20210222223901.2792336-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to move these functions out of the big translate.c, make their prototype public. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.h | 6 ++++++ target/mips/translate.c | 9 +++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 468e29d7578..1801e7f819e 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -178,6 +178,12 @@ extern TCGv bcond; /* MSA */ void msa_translate_init(void); =20 +/* MXU */ +#if !defined(TARGET_MIPS64) +void mxu_translate_init(void); +bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); +#endif /* !TARGET_MIPS64 */ + /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/translate.c b/target/mips/translate.c index 52a7005e18f..609798a0bee 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2046,7 +2046,7 @@ static const char * const mxuregnames[] =3D { "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", }; =20 -static void mxu_translate_init(void) +void mxu_translate_init(void) { for (unsigned i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, @@ -2058,6 +2058,11 @@ static void mxu_translate_init(void) offsetof(CPUMIPSState, active_tc.mxu_cr), mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); } +#else /* !defined(TARGET_MIPS64) */ +void mxu_translate_init(void) +{ + g_assert_not_reached(); +} #endif /* defined(TARGET_MIPS64) */ =20 /* General purpose registers moves. */ @@ -25789,7 +25794,7 @@ static void decode_opc_mxu__pool19(DisasContext *ct= x) } } =20 -static bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) +bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) { uint32_t opcode =3D extract32(insn, 0, 6); =20 --=20 2.26.2 From nobody Mon Feb 9 14:35:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) client-ip=209.85.208.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614033595; cv=none; d=zohomail.com; s=zohoarc; b=NYhi9P81tl0abDhKA0UjYhPz10nN0zOZCaMr4EAH8JMpFQglEMBuPhh6cTto5ZuwDzfKqYhc8fOHqdfXkgiYRqZyoycGbPPDjUOlrRriPWPSnzI/Xy5ssipvyP+m4ZiPTq2cgWNscXYc6Qp2ky0Jtu6HSc/SjBTB/XV/OKMJbQU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614033595; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GffC1GuMfIrowgrdDz3KRuGciqckVQz9nSpe3QdruD0=; b=E16Q6ytMrklpj4YIKKED1zxfvUL3YMElqvNM0WQKN8mZmtnl/QYH1NBmZir1d2f+pkhyFYEDYJSvDaIkYpvXWNACB9gAlc6p9igSrLtgTpHgPwFN3DrwtC/SF9hjqjbqeBd7kOqVqz+cP7Ffy9wYzkqBLlCC2sUW0fk3USzC+Sk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) by mx.zohomail.com with SMTPS id 1614033594603709.5587207340828; Mon, 22 Feb 2021 14:39:54 -0800 (PST) Received: by mail-ed1-f48.google.com with SMTP id j9so23973521edp.1 for ; Mon, 22 Feb 2021 14:39:54 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id i17sm12293170ejo.25.2021.02.22.14.39.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GffC1GuMfIrowgrdDz3KRuGciqckVQz9nSpe3QdruD0=; b=giAGhhYxLS/S/BpECU8533DwHz8MPGcYE6NU7K+6MCcRoqlzxt3WfpFxwmcuKknT6U lfuCbOzmhy91G9OQQjJzy/xOKuFYU0SqOVf+MgFa2C9knrIdr+W6G7Hirqmze+R8RMuB JexjdZj/cwQ0l7YFq/PWvcK1QG+Xi2VFqYiGfAraxY5geQV1EYqxyKsMWTwxXjpivoek 6h7ih6y0OT5q8pxQW7oNNPhBuld7D14MqCmmhDcXVdaFfN1VpRY4rImdJDupKJgARNVd I2nSdaWFnQjIO0ISoxaYWXdCsSO2sBNYMihvctPKZ20G8nbBoPy2XuC5YL3xPs+1tSaT 3yrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GffC1GuMfIrowgrdDz3KRuGciqckVQz9nSpe3QdruD0=; b=s/uNqLeAE+nrooALmYAa8aKVrxwHgde5wdqRzkazJPkrX1Qq60/HlX+uB4w45s2faN wicpVa7lUnbtdc7iwsha5Owl2tV8Cmom9tSKOv6Um2B5WlBINR1ISGiqWUKDcDw4gKqf +z9vhBc5DP6F2bFK3WsH2epWYhcQ1GpU0IopZN2gu7poN/95DE9lIDUZKGRdk7BNDnZF b6Dug2W2Icz5LGnX8a94LXVfyuOhJzYwFREvAt49zZL55HeXS1TnsZWSEF1bkMo9NJjr eCY3PDoiEKAHGQXio6UpL/BEBfWQ3drR/9J1CGAlsiQeGhm2FJafwu2KCisymTvNPqn8 OVCQ== X-Gm-Message-State: AOAM531cjcHxmIopwXXXLpmtf2XQqIda8kqf0fjHAb3OSJN3lerUvOcd AGsUf19GaSScO4PBOYxjrV0= X-Google-Smtp-Source: ABdhPJzVj8H+v7H5/dNrA0TnQIQyLe27LA4rb6k6i45bRutp0KFE+tm0Drllbw10vNBqHiC2BW/1bA== X-Received: by 2002:a05:6402:151:: with SMTP id s17mr23862685edu.107.1614033592813; Mon, 22 Feb 2021 14:39:52 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 09/10] target/mips: Simplify 64-bit ifdef'ry of MXU code Date: Mon, 22 Feb 2021 23:39:00 +0100 Message-Id: <20210222223901.2792336-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Check for 'TARGET_LONG_BITS =3D=3D 32' and simplify 64-bit ifdef'ry. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.h | 2 -- target/mips/translate.c | 18 ++++++++++-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 1801e7f819e..a807b3d2566 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -179,10 +179,8 @@ extern TCGv bcond; void msa_translate_init(void); =20 /* MXU */ -#if !defined(TARGET_MIPS64) void mxu_translate_init(void); bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); -#endif /* !TARGET_MIPS64 */ =20 /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/translate.c b/target/mips/translate.c index 609798a0bee..68b5dee4bab 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -25850,6 +25850,15 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t in= sn) return true; } =20 +#else /* !defined(TARGET_MIPS64) */ + +bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) +{ + return false; +} + +#endif /* defined(TARGET_MIPS64) */ + /* * Main MXU decoding function */ @@ -25871,9 +25880,6 @@ static void decode_opc_mxu(DisasContext *ctx, uint3= 2_t insn) decode_ase_mxu(ctx, insn); } =20 -#endif /* !defined(TARGET_MIPS64) */ - - static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ct= x) { int rs, rt, rd; @@ -27017,12 +27023,10 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) break; } #endif -#if !defined(TARGET_MIPS64) - if (ctx->insn_flags & ASE_MXU) { + if ((TARGET_LONG_BITS =3D=3D 32) && (ctx->insn_flags & ASE_MXU)) { decode_opc_mxu(ctx, ctx->opcode); break; } -#endif decode_opc_special2_legacy(env, ctx); break; case OPC_SPECIAL3: @@ -28081,9 +28085,7 @@ void mips_tcg_init(void) cpu_llval =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval= ), "llval"); =20 -#if !defined(TARGET_MIPS64) mxu_translate_init(); -#endif /* !TARGET_MIPS64 */ } =20 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, --=20 2.26.2 From nobody Mon Feb 9 14:35:04 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) client-ip=209.85.208.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1614033602; cv=none; d=zohomail.com; s=zohoarc; b=hwEaz+L7ObxOafi1KntdHPEJ5C4ljrT68Qrg/fdWFEOKhl7HE4A7DSl8bgNtCUNUsU7rEJR1+ia5Y6ib2f/qNMboIsMX16cCTsIAQBh8nirH4IrJY5w9eG7+rG+5URg2kFskMPhr8CPhn/lnMDGe5YH6T5ucoUjsoxeuX5OEJlM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1614033602; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V+Py7qSV2lBK+YKNG35J1GHCYNs/+KNP46gCnzC963o=; b=gjvmF0MamDoYx6U1m8blG9uy86wTDXM04oxact9+nPmRc7MF2AWhTYNkIiTFa4H+Vl5/mp7baFwKBvZNwhfZzltbCBwpeI5nMpTckHyPPWVR8ayA8a0g0B9zud7aRhCcRPEF6oBdAHwgzvRs67IBXz+mZUFw0i+l5ynIDcJfAgI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) by mx.zohomail.com with SMTPS id 1614033601670264.59048391122633; Mon, 22 Feb 2021 14:40:01 -0800 (PST) Received: by mail-ed1-f48.google.com with SMTP id i14so23651752eds.8 for ; Mon, 22 Feb 2021 14:40:00 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id r11sm13078630edt.58.2021.02.22.14.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 14:39:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V+Py7qSV2lBK+YKNG35J1GHCYNs/+KNP46gCnzC963o=; b=s57x6fEaPSkAX1M/+tsAtx/g1Zm3xNj7BdOgxCqqSYcUFJqlt4jIgI9wEVfLvVV4z0 BbHLP5OXtmbEHDvyjX3r+wRoBjhQ140IZMzTHWWwvWI8PmipKu5wTKqL61b9mypYxun+ zgzDwl67m7die82FVkHjgAO0kG1VidMN+ZPHVyIr6rDxDzpXfDOgGSuMz4G5BifaMz3i iIVK9tchaHw8WQmXFkwS/jmNTR3QmvYvuyIQgkXTWkDsia49WC62t1/QzMxBk5VOdazr 9D9n43Te6vhRj4tCOJo6ti6Rb1BZ/YRRUi5ZjgQRdCYFNJQ2wxIZYDHmjaHMRba9hjhA IWDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=V+Py7qSV2lBK+YKNG35J1GHCYNs/+KNP46gCnzC963o=; b=fQSEGJeID03pkGMBzDbdxFVJoWcfFOpcRFr/bgSIwS80pXIsJvNdR5JcsZt5ZfnjiO 8ZUC0PfwIPZnCf36NiMKjeSJaYNEdPLARlY6NezQZoBzfcLqWfL+D3RJ+7PgUaH6+V+g d8YEPPBwDi1RW+FlW1D5tJUoK+RMR18H50Prcjip/cYvOU9AZdbFvTTGCw4gbAMAfgo3 WnZQcGyUE9AYnoi1b1/oNXxaFqXOUu5V0OiYB39ECmrFklhUHApMuKbgQL4xOKQWU8PB LKIrkYuS5UyQ2dgQtCoDKwAs7zrRjSrEF9xQ5EM0hxaiCUUzuqtOB6kYTx7DJnwBuag1 2ulA== X-Gm-Message-State: AOAM531bY5HJT8+dHH636q6PwUtvYjOEOqv9aprljAJrVuK0s0S44BfI KMxLDmnNc4R3Tj3MllhVQqI= X-Google-Smtp-Source: ABdhPJxr+IDZQjCJpR+5R+zfK21AkuUGLWXdNRSdCH/zOpC23O+IO6CDqj/9coOUr0+lwZuE1PMWUw== X-Received: by 2002:aa7:dc17:: with SMTP id b23mr25351849edu.139.1614033598928; Mon, 22 Feb 2021 14:39:58 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo Subject: [PATCH v3 10/10] target/mips: Extract MXU code to new mxu_translate.c file Date: Mon, 22 Feb 2021 23:39:01 +0100 Message-Id: <20210222223901.2792336-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210222223901.2792336-1-f4bug@amsat.org> References: <20210222223901.2792336-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract 1600+ lines from the big translate.c into a new file. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/mxu_translate.c | 1625 +++++++++++++++++++++++++++++++++++ target/mips/translate.c | 1613 ---------------------------------- target/mips/meson.build | 1 + 3 files changed, 1626 insertions(+), 1613 deletions(-) create mode 100644 target/mips/mxu_translate.c diff --git a/target/mips/mxu_translate.c b/target/mips/mxu_translate.c new file mode 100644 index 00000000000..a3a95b50c42 --- /dev/null +++ b/target/mips/mxu_translate.c @@ -0,0 +1,1625 @@ +/* + * Ingenic XBurst Media eXtension Unit (MXU) translation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + * + * Datasheet: + * + * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it + * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2,= 2017 + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" + +#if !defined(TARGET_MIPS64) + +/* + * + * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * + * + * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MI= PS32 + * instructions set. It is designed to fit the needs of signal, graphical = and + * video processing applications. MXU instruction set is used in Xburst fa= mily + * of microprocessors by Ingenic. + * + * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X1= 6 is + * the control register. + * + * + * The notation used in MXU assembler mnemonics + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * Register operands: + * + * XRa, XRb, XRc, XRd - MXU registers + * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers + * + * Non-register operands: + * + * aptn1 - 1-bit accumulate add/subtract pattern + * aptn2 - 2-bit accumulate add/subtract pattern + * eptn2 - 2-bit execute add/subtract pattern + * optn2 - 2-bit operand pattern + * optn3 - 3-bit operand pattern + * sft4 - 4-bit shift amount + * strd2 - 2-bit stride amount + * + * Prefixes: + * + * Level of parallelism: Operand size: + * S - single operation at a time 32 - word + * D - two operations in parallel 16 - half word + * Q - four operations in parallel 8 - byte + * + * Operations: + * + * ADD - Add or subtract + * ADDC - Add with carry-in + * ACC - Accumulate + * ASUM - Sum together then accumulate (add or subtract) + * ASUMC - Sum together then accumulate (add or subtract) with carry-in + * AVG - Average between 2 operands + * ABD - Absolute difference + * ALN - Align data + * AND - Logical bitwise 'and' operation + * CPS - Copy sign + * EXTR - Extract bits + * I2M - Move from GPR register to MXU register + * LDD - Load data from memory to XRF + * LDI - Load data from memory to XRF (and increase the address base) + * LUI - Load unsigned immediate + * MUL - Multiply + * MULU - Unsigned multiply + * MADD - 64-bit operand add 32x32 product + * MSUB - 64-bit operand subtract 32x32 product + * MAC - Multiply and accumulate (add or subtract) + * MAD - Multiply and add or subtract + * MAX - Maximum between 2 operands + * MIN - Minimum between 2 operands + * M2I - Move from MXU register to GPR register + * MOVZ - Move if zero + * MOVN - Move if non-zero + * NOR - Logical bitwise 'nor' operation + * OR - Logical bitwise 'or' operation + * STD - Store data from XRF to memory + * SDI - Store data from XRF to memory (and increase the address base) + * SLT - Set of less than comparison + * SAD - Sum of absolute differences + * SLL - Logical shift left + * SLR - Logical shift right + * SAR - Arithmetic shift right + * SAT - Saturation + * SFL - Shuffle + * SCOP - Calculate x=E2=80=99s scope (-1, means x<0; 0, means x=3D=3D0= ; 1, means x>0) + * XOR - Logical bitwise 'exclusive or' operation + * + * Suffixes: + * + * E - Expand results + * F - Fixed point multiplication + * L - Low part result + * R - Doing rounding + * V - Variable instead of immediate + * W - Combine above L and V + * + * + * The list of MXU instructions grouped by functionality + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * Load/Store instructions Multiplication instructions + * ----------------------- --------------------------- + * + * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt + * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt + * S32LDDV XRa, Rb, rc, strd2 S32MSUB XRa, XRd, Rs, Rt + * S32STDV XRa, Rb, rc, strd2 S32MSUBU XRa, XRd, Rs, Rt + * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt + * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt + * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2 + * S32SDIV XRa, Rb, rc, strd2 D16MULE XRa, XRb, XRc, optn2 + * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2 + * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, op= tn2 + * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, o= ptn2 + * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, o= ptn2 + * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, o= ptn2 + * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, op= tn2 + * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd + * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd + * S16LDD XRa, Rb, s10, eptn2 Q8MAC XRa, XRb, XRc, XRd, aptn2 + * S16STD XRa, Rb, s10, eptn2 Q8MACSU XRa, XRb, XRc, XRd, aptn2 + * S16LDI XRa, Rb, s10, eptn2 Q8MADL XRa, XRb, XRc, XRd, aptn2 + * S16SDI XRa, Rb, s10, eptn2 + * S8LDD XRa, Rb, s8, eptn3 + * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions + * S8LDI XRa, Rb, s8, eptn3 ------------------------------------- + * S8SDI XRa, Rb, s8, eptn3 + * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2 + * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd + * LXHU Rd, Rs, Rt, strd2 D32ACC XRa, XRb, XRc, XRd, eptn2 + * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2 + * LXBU Rd, Rs, Rt, strd2 D32ASUM XRa, XRb, XRc, XRd, eptn2 + * S32CPS XRa, XRb, XRc + * Q16ADD XRa, XRb, XRc, XRd, eptn2, op= tn2 + * Comparison instructions Q16ACC XRa, XRb, XRc, XRd, eptn2 + * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2 + * D16ASUM XRa, XRb, XRc, XRd, eptn2 + * S32MAX XRa, XRb, XRc D16CPS XRa, XRb, + * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc + * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc + * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2 + * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2 + * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2 + * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc + * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd + * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc + * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc + * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd + * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd + * Q8SLT XRa, XRb, XRc + * Q8SLTU XRa, XRb, XRc + * Q8MOVZ XRa, XRb, XRc Shift instructions + * Q8MOVN XRa, XRb, XRc ------------------ + * + * D32SLL XRa, XRb, XRc, XRd, sft4 + * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4 + * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4 + * D32SARL XRa, XRb, XRc, sft4 + * S32NOR XRa, XRb, XRc D32SLLV XRa, XRb, Rb + * S32AND XRa, XRb, XRc D32SLRV XRa, XRb, Rb + * S32XOR XRa, XRb, XRc D32SARV XRa, XRb, Rb + * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb + * Q16SLL XRa, XRb, XRc, XRd, sft4 + * Q16SLR XRa, XRb, XRc, XRd, sft4 + * Miscellaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4 + * ------------------------- Q16SLLV XRa, XRb, Rb + * Q16SLRV XRa, XRb, Rb + * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb + * S32ALN XRa, XRb, XRc, Rb + * S32ALNI XRa, XRb, XRc, s3 + * S32LUI XRa, s8, optn3 Move instructions + * S32EXTR XRa, XRb, Rb, bits5 ----------------- + * S32EXTRV XRa, XRb, Rs, Rt + * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb + * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb + * + * + * The opcode organization of MXU instructions + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred + * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning = of + * other bits up to the instruction level is as follows: + * + * bits + * 05..00 + * + * =E2=94=8C=E2=94=80 000000 =E2=94=80 OPC_MXU_S32MADD + * =E2=94=9C=E2=94=80 000001 =E2=94=80 OPC_MXU_S32MADDU + * =E2=94=9C=E2=94=80 000010 =E2=94=80 (non-MXU = OPC_MUL) + * =E2=94=82 + * =E2=94=82 20..18 + * =E2=94=9C=E2=94=80 000011 =E2=94=80 OPC_MXU__POOL00 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32MAX + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32MIN + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MAX + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MIN + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8MAX + * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8MIN + * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_Q8SLT + * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8SLTU + * =E2=94=9C=E2=94=80 000100 =E2=94=80 OPC_MXU_S32MSUB + * =E2=94=9C=E2=94=80 000101 =E2=94=80 OPC_MXU_S32MSUBU 20..18 + * =E2=94=9C=E2=94=80 000110 =E2=94=80 OPC_MXU__POOL01 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32SLT + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_D16SLT + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16AVG + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16AVGR + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8AVG + * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8AVGR + * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8ADD + * =E2=94=82 + * =E2=94=82 20..18 + * =E2=94=9C=E2=94=80 000111 =E2=94=80 OPC_MXU__POOL02 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32CPS + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16CPS + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8ABD + * =E2=94=82 =E2=94=94=E2=94=80 110 = =E2=94=80 OPC_MXU_Q16SAT + * =E2=94=9C=E2=94=80 001000 =E2=94=80 OPC_MXU_D16MUL + * =E2=94=82 25..24 + * =E2=94=9C=E2=94=80 001001 =E2=94=80 OPC_MXU__POOL03 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D16MULF + * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_D16MULE + * =E2=94=9C=E2=94=80 001010 =E2=94=80 OPC_MXU_D16MAC + * =E2=94=9C=E2=94=80 001011 =E2=94=80 OPC_MXU_D16MACF + * =E2=94=9C=E2=94=80 001100 =E2=94=80 OPC_MXU_D16MADL + * =E2=94=9C=E2=94=80 001101 =E2=94=80 OPC_MXU_S16MAD + * =E2=94=9C=E2=94=80 001110 =E2=94=80 OPC_MXU_Q16ADD + * =E2=94=9C=E2=94=80 001111 =E2=94=80 OPC_MXU_D16MACE 23 + * =E2=94=82 =E2=94=8C=E2=94=80 0 =E2= =94=80 OPC_MXU_S32LDD + * =E2=94=9C=E2=94=80 010000 =E2=94=80 OPC_MXU__POOL04 =E2=94=80= =E2=94=B4=E2=94=80 1 =E2=94=80 OPC_MXU_S32LDDR + * =E2=94=82 + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010001 =E2=94=80 OPC_MXU__POOL05 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32STD + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32STDR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010010 =E2=94=80 OPC_MXU__POOL06 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDDV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDDVR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010011 =E2=94=80 OPC_MXU__POOL07 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32STDV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32STDVR + * =E2=94=82 + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010100 =E2=94=80 OPC_MXU__POOL08 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32LDI + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32LDIR + * =E2=94=82 + * =E2=94=82 23 + * =E2=94=9C=E2=94=80 010101 =E2=94=80 OPC_MXU__POOL09 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32SDI + * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32SDIR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010110 =E2=94=80 OPC_MXU__POOL10 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDIV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDIVR + * =E2=94=82 + * =E2=94=82 13..10 + * =E2=94=9C=E2=94=80 010111 =E2=94=80 OPC_MXU__POOL11 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32SDIV + * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32SDIVR + * =E2=94=9C=E2=94=80 011000 =E2=94=80 OPC_MXU_D32ADD + * =E2=94=82 23..22 + * MXU =E2=94=9C=E2=94=80 011001 =E2=94=80 OPC_MXU__POOL12 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D32ACC + * opcodes =E2=94=80=E2=94=A4 =E2=94=9C=E2=94= =80 01 =E2=94=80 OPC_MXU_D32ACCM + * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_D32ASUM + * =E2=94=9C=E2=94=80 011010 =E2=94=80 + * =E2=94=82 23..22 + * =E2=94=9C=E2=94=80 011011 =E2=94=80 OPC_MXU__POOL13 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q16ACC + * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_Q16ACCM + * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q16ASUM + * =E2=94=82 + * =E2=94=82 23..22 + * =E2=94=9C=E2=94=80 011100 =E2=94=80 OPC_MXU__POOL14 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8ADDE + * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_D8SUM + * =E2=94=9C=E2=94=80 011101 =E2=94=80 OPC_MXU_Q8ACCE =E2=94=94= =E2=94=80 10 =E2=94=80 OPC_MXU_D8SUMC + * =E2=94=9C=E2=94=80 011110 =E2=94=80 + * =E2=94=9C=E2=94=80 011111 =E2=94=80 + * =E2=94=9C=E2=94=80 100000 =E2=94=80 (overlaps= with CLZ) + * =E2=94=9C=E2=94=80 100001 =E2=94=80 (overlaps= with CLO) + * =E2=94=9C=E2=94=80 100010 =E2=94=80 OPC_MXU_S8LDD + * =E2=94=9C=E2=94=80 100011 =E2=94=80 OPC_MXU_S8STD 15..14 + * =E2=94=9C=E2=94=80 100100 =E2=94=80 OPC_MXU_S8LDI =E2=94=8C= =E2=94=80 00 =E2=94=80 OPC_MXU_S32MUL + * =E2=94=9C=E2=94=80 100101 =E2=94=80 OPC_MXU_S8SDI =E2=94=9C= =E2=94=80 00 =E2=94=80 OPC_MXU_S32MULU + * =E2=94=82 =E2=94=9C=E2=94=80 00 =E2= =94=80 OPC_MXU_S32EXTR + * =E2=94=9C=E2=94=80 100110 =E2=94=80 OPC_MXU__POOL15 =E2=94=80= =E2=94=B4=E2=94=80 00 =E2=94=80 OPC_MXU_S32EXTRV + * =E2=94=82 + * =E2=94=82 20..18 + * =E2=94=9C=E2=94=80 100111 =E2=94=80 OPC_MXU__POOL16 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_D32SARW + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32ALN + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_S32ALNI + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_S32LUI + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32NOR + * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_S32AND + * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_S32OR + * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_S32XOR + * =E2=94=82 + * =E2=94=82 7..5 + * =E2=94=9C=E2=94=80 101000 =E2=94=80 OPC_MXU__POOL17 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_LXB + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_LXH + * =E2=94=9C=E2=94=80 101001 =E2=94=80 =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_LXW + * =E2=94=9C=E2=94=80 101010 =E2=94=80 OPC_MXU_S16LDD =E2=94=9C= =E2=94=80 100 =E2=94=80 OPC_MXU_LXBU + * =E2=94=9C=E2=94=80 101011 =E2=94=80 OPC_MXU_S16STD =E2=94=94= =E2=94=80 101 =E2=94=80 OPC_MXU_LXHU + * =E2=94=9C=E2=94=80 101100 =E2=94=80 OPC_MXU_S16LDI + * =E2=94=9C=E2=94=80 101101 =E2=94=80 OPC_MXU_S16SDI + * =E2=94=9C=E2=94=80 101110 =E2=94=80 OPC_MXU_S32M2I + * =E2=94=9C=E2=94=80 101111 =E2=94=80 OPC_MXU_S32I2M + * =E2=94=9C=E2=94=80 110000 =E2=94=80 OPC_MXU_D32SLL + * =E2=94=9C=E2=94=80 110001 =E2=94=80 OPC_MXU_D32SLR 20..18 + * =E2=94=9C=E2=94=80 110010 =E2=94=80 OPC_MXU_D32SARL =E2=94=8C= =E2=94=80 000 =E2=94=80 OPC_MXU_D32SLLV + * =E2=94=9C=E2=94=80 110011 =E2=94=80 OPC_MXU_D32SAR =E2=94=9C= =E2=94=80 001 =E2=94=80 OPC_MXU_D32SLRV + * =E2=94=9C=E2=94=80 110100 =E2=94=80 OPC_MXU_Q16SLL =E2=94=9C= =E2=94=80 010 =E2=94=80 OPC_MXU_D32SARV + * =E2=94=9C=E2=94=80 110101 =E2=94=80 OPC_MXU_Q16SLR =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_Q16SLLV + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q16SLRV + * =E2=94=9C=E2=94=80 110110 =E2=94=80 OPC_MXU__POOL18 =E2=94=80= =E2=94=B4=E2=94=80 101 =E2=94=80 OPC_MXU_Q16SARV + * =E2=94=82 + * =E2=94=9C=E2=94=80 110111 =E2=94=80 OPC_MXU_Q16SAR + * =E2=94=82 23..22 + * =E2=94=9C=E2=94=80 111000 =E2=94=80 OPC_MXU__POOL19 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MUL + * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_Q8MULSU + * =E2=94=82 + * =E2=94=82 20..18 + * =E2=94=9C=E2=94=80 111001 =E2=94=80 OPC_MXU__POOL20 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_Q8MOVZ + * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_Q8MOVN + * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MOVZ + * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MOVN + * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32MOVZ + * =E2=94=82 =E2=94=94=E2=94=80 101 = =E2=94=80 OPC_MXU_S32MOVN + * =E2=94=82 + * =E2=94=82 23..22 + * =E2=94=9C=E2=94=80 111010 =E2=94=80 OPC_MXU__POOL21 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MAC + * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q8MACSU + * =E2=94=9C=E2=94=80 111011 =E2=94=80 OPC_MXU_Q16SCOP + * =E2=94=9C=E2=94=80 111100 =E2=94=80 OPC_MXU_Q8MADL + * =E2=94=9C=E2=94=80 111101 =E2=94=80 OPC_MXU_S32SFL + * =E2=94=9C=E2=94=80 111110 =E2=94=80 OPC_MXU_Q8SAD + * =E2=94=94=E2=94=80 111111 =E2=94=80 (overlaps= with SDBBP) + * + * + * Compiled after: + * + * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it + * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2,= 2017 + */ + +enum { + OPC_MXU__POOL00 =3D 0x03, + OPC_MXU_D16MUL =3D 0x08, + OPC_MXU_D16MAC =3D 0x0A, + OPC_MXU__POOL04 =3D 0x10, + OPC_MXU_S8LDD =3D 0x22, + OPC_MXU__POOL16 =3D 0x27, + OPC_MXU_S32M2I =3D 0x2E, + OPC_MXU_S32I2M =3D 0x2F, + OPC_MXU__POOL19 =3D 0x38, +}; + + +/* + * MXU pool 00 + */ +enum { + OPC_MXU_S32MAX =3D 0x00, + OPC_MXU_S32MIN =3D 0x01, + OPC_MXU_D16MAX =3D 0x02, + OPC_MXU_D16MIN =3D 0x03, + OPC_MXU_Q8MAX =3D 0x04, + OPC_MXU_Q8MIN =3D 0x05, +}; + +/* + * MXU pool 04 + */ +enum { + OPC_MXU_S32LDD =3D 0x00, + OPC_MXU_S32LDDR =3D 0x01, +}; + +/* + * MXU pool 16 + */ +enum { + OPC_MXU_S32ALNI =3D 0x02, + OPC_MXU_S32NOR =3D 0x04, + OPC_MXU_S32AND =3D 0x05, + OPC_MXU_S32OR =3D 0x06, + OPC_MXU_S32XOR =3D 0x07, +}; + +/* + * MXU pool 19 + */ +enum { + OPC_MXU_Q8MUL =3D 0x00, + OPC_MXU_Q8MULSU =3D 0x01, +}; + +/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */ +#define MXU_APTN1_A 0 +#define MXU_APTN1_S 1 + +/* MXU accumulate add/subtract 2-bit pattern 'aptn2' */ +#define MXU_APTN2_AA 0 +#define MXU_APTN2_AS 1 +#define MXU_APTN2_SA 2 +#define MXU_APTN2_SS 3 + +/* MXU execute add/subtract 2-bit pattern 'eptn2' */ +#define MXU_EPTN2_AA 0 +#define MXU_EPTN2_AS 1 +#define MXU_EPTN2_SA 2 +#define MXU_EPTN2_SS 3 + +/* MXU operand getting pattern 'optn2' */ +#define MXU_OPTN2_PTN0 0 +#define MXU_OPTN2_PTN1 1 +#define MXU_OPTN2_PTN2 2 +#define MXU_OPTN2_PTN3 3 +/* alternative naming scheme for 'optn2' */ +#define MXU_OPTN2_WW 0 +#define MXU_OPTN2_LW 1 +#define MXU_OPTN2_HW 2 +#define MXU_OPTN2_XW 3 + +/* MXU operand getting pattern 'optn3' */ +#define MXU_OPTN3_PTN0 0 +#define MXU_OPTN3_PTN1 1 +#define MXU_OPTN3_PTN2 2 +#define MXU_OPTN3_PTN3 3 +#define MXU_OPTN3_PTN4 4 +#define MXU_OPTN3_PTN5 5 +#define MXU_OPTN3_PTN6 6 +#define MXU_OPTN3_PTN7 7 + +/* MXU registers */ +static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; +static TCGv mxu_CR; + +static const char * const mxuregnames[] =3D { + "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", + "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", +}; + +void mxu_translate_init(void) +{ + for (unsigned i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { + mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.m= xu_gpr[i]), + mxuregnames[i]); + } + + mxu_CR =3D tcg_global_mem_new(cpu_env, + offsetof(CPUMIPSState, active_tc.mxu_cr), + mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); +} + +/* MXU General purpose registers moves. */ +static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg =3D=3D 0) { + tcg_gen_movi_tl(t, 0); + } else if (reg <=3D 15) { + tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); + } +} + +static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg) +{ + if (reg > 0 && reg <=3D 15) { + tcg_gen_mov_tl(mxu_gpr[reg - 1], t); + } +} + +/* MXU control register moves. */ +static inline void gen_load_mxu_cr(TCGv t) +{ + tcg_gen_mov_tl(t, mxu_CR); +} + +static inline void gen_store_mxu_cr(TCGv t) +{ + /* TODO: Add handling of RW rules for MXU_CR. */ + tcg_gen_mov_tl(mxu_CR, t); +} + +/* + * S32I2M XRa, rb - Register move from GRF to XRF + */ +static void gen_mxu_s32i2m(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 5); + Rb =3D extract32(ctx->opcode, 16, 5); + + gen_load_gpr(t0, Rb); + if (XRa <=3D 15) { + gen_store_mxu_gpr(t0, XRa); + } else if (XRa =3D=3D 16) { + gen_store_mxu_cr(t0); + } + + tcg_temp_free(t0); +} + +/* + * S32M2I XRa, rb - Register move from XRF to GRF + */ +static void gen_mxu_s32m2i(DisasContext *ctx) +{ + TCGv t0; + uint32_t XRa, Rb; + + t0 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 5); + Rb =3D extract32(ctx->opcode, 16, 5); + + if (XRa <=3D 15) { + gen_load_mxu_gpr(t0, XRa); + } else if (XRa =3D=3D 16) { + gen_load_mxu_cr(t0); + } + + gen_store_gpr(t0, Rb); + + tcg_temp_free(t0); +} + +/* + * S8LDD XRa, Rb, s8, optn3 - Load a byte from memory to XRF + */ +static void gen_mxu_s8ldd(DisasContext *ctx) +{ + TCGv t0, t1; + uint32_t XRa, Rb, s8, optn3; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + s8 =3D extract32(ctx->opcode, 10, 8); + optn3 =3D extract32(ctx->opcode, 18, 3); + Rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_gpr(t0, Rb); + tcg_gen_addi_tl(t0, t0, (int8_t)s8); + + switch (optn3) { + /* XRa[7:0] =3D tmp8 */ + case MXU_OPTN3_PTN0: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 0, 8); + break; + /* XRa[15:8] =3D tmp8 */ + case MXU_OPTN3_PTN1: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 8, 8); + break; + /* XRa[23:16] =3D tmp8 */ + case MXU_OPTN3_PTN2: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 16, 8); + break; + /* XRa[31:24] =3D tmp8 */ + case MXU_OPTN3_PTN3: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + gen_load_mxu_gpr(t0, XRa); + tcg_gen_deposit_tl(t0, t0, t1, 24, 8); + break; + /* XRa =3D {8'b0, tmp8, 8'b0, tmp8} */ + case MXU_OPTN3_PTN4: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + /* XRa =3D {tmp8, 8'b0, tmp8, 8'b0} */ + case MXU_OPTN3_PTN5: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_shli_tl(t1, t1, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + /* XRa =3D {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */ + case MXU_OPTN3_PTN6: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB); + tcg_gen_mov_tl(t0, t1); + tcg_gen_andi_tl(t0, t0, 0xFF00FFFF); + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_or_tl(t0, t0, t1); + break; + /* XRa =3D {tmp8, tmp8, tmp8, tmp8} */ + case MXU_OPTN3_PTN7: + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_deposit_tl(t1, t1, t1, 8, 8); + tcg_gen_deposit_tl(t0, t1, t1, 16, 16); + break; + } + + gen_store_mxu_gpr(t0, XRa); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + +/* + * D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication + */ +static void gen_mxu_d16mul(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3; + uint32_t XRa, XRb, XRc, XRd, optn2; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRc =3D extract32(ctx->opcode, 14, 4); + XRd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + + gen_load_mxu_gpr(t1, XRb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + gen_load_mxu_gpr(t3, XRc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, XRa); + gen_store_mxu_gpr(t2, XRd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + +/* + * D16MAC XRa, XRb, XRc, XRd, aptn2, optn2 - Signed 16 bit pattern multiply + * and accumulate + */ +static void gen_mxu_d16mac(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3; + uint32_t XRa, XRb, XRc, XRd, optn2, aptn2; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRc =3D extract32(ctx->opcode, 14, 4); + XRd =3D extract32(ctx->opcode, 18, 4); + optn2 =3D extract32(ctx->opcode, 22, 2); + aptn2 =3D extract32(ctx->opcode, 24, 2); + + gen_load_mxu_gpr(t1, XRb); + tcg_gen_sextract_tl(t0, t1, 0, 16); + tcg_gen_sextract_tl(t1, t1, 16, 16); + + gen_load_mxu_gpr(t3, XRc); + tcg_gen_sextract_tl(t2, t3, 0, 16); + tcg_gen_sextract_tl(t3, t3, 16, 16); + + switch (optn2) { + case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t0, t2); + break; + case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t1, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ + tcg_gen_mul_tl(t3, t0, t3); + tcg_gen_mul_tl(t2, t1, t2); + break; + } + gen_load_mxu_gpr(t0, XRa); + gen_load_mxu_gpr(t1, XRd); + + switch (aptn2) { + case MXU_APTN2_AA: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case MXU_APTN2_AS: + tcg_gen_add_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + case MXU_APTN2_SA: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_add_tl(t2, t1, t2); + break; + case MXU_APTN2_SS: + tcg_gen_sub_tl(t3, t0, t3); + tcg_gen_sub_tl(t2, t1, t2); + break; + } + gen_store_mxu_gpr(t3, XRa); + gen_store_mxu_gpr(t2, XRd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); +} + +/* + * Q8MUL XRa, XRb, XRc, XRd - Parallel unsigned 8 bit pattern multiply + * Q8MULSU XRa, XRb, XRc, XRd - Parallel signed 8 bit pattern multiply + */ +static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) +{ + TCGv t0, t1, t2, t3, t4, t5, t6, t7; + uint32_t XRa, XRb, XRc, XRd, sel; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + t3 =3D tcg_temp_new(); + t4 =3D tcg_temp_new(); + t5 =3D tcg_temp_new(); + t6 =3D tcg_temp_new(); + t7 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRc =3D extract32(ctx->opcode, 14, 4); + XRd =3D extract32(ctx->opcode, 18, 4); + sel =3D extract32(ctx->opcode, 22, 2); + + gen_load_mxu_gpr(t3, XRb); + gen_load_mxu_gpr(t7, XRc); + + if (sel =3D=3D 0x2) { + /* Q8MULSU */ + tcg_gen_ext8s_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8s_tl(t3, t3); + } else { + /* Q8MUL */ + tcg_gen_ext8u_tl(t0, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t1, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t2, t3); + tcg_gen_shri_tl(t3, t3, 8); + tcg_gen_ext8u_tl(t3, t3); + } + + tcg_gen_ext8u_tl(t4, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t5, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t6, t7); + tcg_gen_shri_tl(t7, t7, 8); + tcg_gen_ext8u_tl(t7, t7); + + tcg_gen_mul_tl(t0, t0, t4); + tcg_gen_mul_tl(t1, t1, t5); + tcg_gen_mul_tl(t2, t2, t6); + tcg_gen_mul_tl(t3, t3, t7); + + tcg_gen_andi_tl(t0, t0, 0xFFFF); + tcg_gen_andi_tl(t1, t1, 0xFFFF); + tcg_gen_andi_tl(t2, t2, 0xFFFF); + tcg_gen_andi_tl(t3, t3, 0xFFFF); + + tcg_gen_shli_tl(t1, t1, 16); + tcg_gen_shli_tl(t3, t3, 16); + + tcg_gen_or_tl(t0, t0, t1); + tcg_gen_or_tl(t1, t2, t3); + + gen_store_mxu_gpr(t0, XRd); + gen_store_mxu_gpr(t1, XRa); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); + tcg_temp_free(t4); + tcg_temp_free(t5); + tcg_temp_free(t6); + tcg_temp_free(t7); +} + +/* + * S32LDD XRa, Rb, S12 - Load a word from memory to XRF + * S32LDDR XRa, Rb, S12 - Load a word from memory to XRF, reversed byte se= q. + */ +static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) +{ + TCGv t0, t1; + uint32_t XRa, Rb, s12, sel; + + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + XRa =3D extract32(ctx->opcode, 6, 4); + s12 =3D extract32(ctx->opcode, 10, 10); + sel =3D extract32(ctx->opcode, 20, 1); + Rb =3D extract32(ctx->opcode, 21, 5); + + gen_load_gpr(t0, Rb); + + tcg_gen_movi_tl(t1, s12); + tcg_gen_shli_tl(t1, t1, 2); + if (s12 & 0x200) { + tcg_gen_ori_tl(t1, t1, 0xFFFFF000); + } + tcg_gen_add_tl(t1, t0, t1); + tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL); + + if (sel =3D=3D 1) { + /* S32LDDR */ + tcg_gen_bswap32_tl(t1, t1); + } + gen_store_mxu_gpr(t1, XRa); + + tcg_temp_free(t0); + tcg_temp_free(t1); +} + + +/* + * MXU instruction category: logic + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32NOR S32AND S32OR S32XOR + */ + +/* + * S32NOR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'nor' operation + * applied to the content of XRb and XRc. + */ +static void gen_mxu_S32NOR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 1s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0xFFFFFFFF); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just set destination to the negation of XR= c */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc =3D=3D 0)) { + /* XRa zero register -> just set destination to the negation of XR= b */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to the negation of X= Rb */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_nor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + } +} + +/* + * S32AND XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'and' operation + * applied to the content of XRb and XRc. + */ +static void gen_mxu_S32AND(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { + /* one of operands zero register -> just set destination to all 0s= */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_and_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + } +} + +/* + * S32OR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'or' operation + * applied to the content of XRb and XRc. + */ +static void gen_mxu_S32OR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 0s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just set destination to the content of XRc= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc =3D=3D 0)) { + /* XRc zero register -> just set destination to the content of XRb= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1= ]); + } +} + +/* + * S32XOR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'xor' operation + * applied to the content of XRb and XRc. + */ +static void gen_mxu_S32XOR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 0s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just set destination to the content of XRc= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc =3D=3D 0)) { + /* XRc zero register -> just set destination to the content of XRb= */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to all 0s */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else { + /* the most general case */ + tcg_gen_xor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); + } +} + + +/* + * MXU instruction category max/min + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32MAX D16MAX Q8MAX + * S32MIN D16MIN Q8MIN + */ + +/* + * S32MAX XRa, XRb, XRc + * Update XRa with the maximum of signed 32-bit integers contained + * in XRb and XRc. + * + * S32MIN XRa, XRb, XRc + * Update XRa with the minimum of signed 32-bit integers contained + * in XRb and XRc. + */ +static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + opc =3D extract32(ctx->opcode, 18, 3); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { + /* exactly one operand is zero register - find which one is not...= */ + uint32_t XRx =3D XRb ? XRb : XRc; + /* ...and do max/min operation with one operand 0 */ + if (opc =3D=3D OPC_MXU_S32MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); + } + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + if (opc =3D=3D OPC_MXU_S32MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], + mxu_gpr[XRc - 1]); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], + mxu_gpr[XRc - 1]); + } + } +} + +/* + * D16MAX + * Update XRa with the 16-bit-wise maximums of signed integers + * contained in XRb and XRc. + * + * D16MIN + * Update XRa with the 16-bit-wise minimums of signed integers + * contained in XRb and XRc. + */ +static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + opc =3D extract32(ctx->opcode, 18, 3); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRc =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRa =3D=3D 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRc - 1], 0); + } else if (unlikely((XRb =3D=3D 0) || (XRa =3D=3D 0))) { + /* exactly one operand is zero register - find which one is not...= */ + uint32_t XRx =3D XRb ? XRb : XRc; + /* ...and do half-word-wise max/min with one operand 0 */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_const_i32(0); + + /* the left half-word first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* the right half-word */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting half-words to its original position */ + tcg_gen_shri_i32(t0, t0, 16); + /* finally update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + /* the left half-word first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* the right half-word */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + tcg_gen_shli_i32(t1, t1, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_D16MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting half-words to its original position */ + tcg_gen_shri_i32(t0, t0, 16); + /* finally update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } +} + +/* + * Q8MAX + * Update XRa with the 8-bit-wise maximums of signed integers + * contained in XRb and XRc. + * + * Q8MIN + * Update XRa with the 8-bit-wise minimums of signed integers + * contained in XRb and XRc. + */ +static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad =3D extract32(ctx->opcode, 21, 5); + opc =3D extract32(ctx->opcode, 18, 3); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { + /* exactly one operand is zero register - make it be the first...*/ + uint32_t XRx =3D XRb ? XRb : XRc; + /* ...and do byte-wise max/min with one operand 0 */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_const_i32(0); + int32_t i; + + /* the leftmost byte (byte 3) first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000); + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* bytes 2, 1, 0 */ + for (i =3D 2; i >=3D 0; i--) { + /* extract the byte */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF << (8 * i)); + /* move the byte to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); + /* finally update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + } + + tcg_temp_free(t1); + tcg_temp_free(t0); + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + int32_t i; + + /* the leftmost bytes (bytes 3) first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* bytes 2, 1, 0 */ + for (i =3D 2; i >=3D 0; i--) { + /* extract corresponding bytes */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF << (8 * i)); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF << (8 * i)); + /* move the bytes to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); + tcg_gen_shli_i32(t1, t1, 8 * (3 - i)); + /* t0 will be max/min of t0 and t1 */ + if (opc =3D=3D OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); + /* finally update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + } + + tcg_temp_free(t1); + tcg_temp_free(t0); + } +} + + +/* + * MXU instruction category: align + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32ALN S32ALNI + */ + +/* + * S32ALNI XRc, XRb, XRa, optn3 + * Arrange bytes from XRb and XRc according to one of five sets of + * rules determined by optn3, and place the result in XRa. + */ +static void gen_mxu_S32ALNI(DisasContext *ctx) +{ + uint32_t optn3, pad, XRc, XRb, XRa; + + optn3 =3D extract32(ctx->opcode, 23, 3); + pad =3D extract32(ctx->opcode, 21, 2); + XRc =3D extract32(ctx->opcode, 14, 4); + XRb =3D extract32(ctx->opcode, 10, 4); + XRa =3D extract32(ctx->opcode, 6, 4); + + if (unlikely(pad !=3D 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa =3D=3D 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { + /* both operands zero registers -> just set destination to all 0s = */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb =3D=3D 0)) { + /* XRb zero register -> just appropriatelly shift XRc into XRa */ + switch (optn3) { + case MXU_OPTN3_PTN0: + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1], + 8 * (4 - optn3)); + break; + case MXU_OPTN3_PTN4: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + break; + } + } else if (unlikely(XRc =3D=3D 0)) { + /* XRc zero register -> just appropriatelly shift XRb into XRa */ + switch (optn3) { + case MXU_OPTN3_PTN0: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3= ); + break; + case MXU_OPTN3_PTN4: + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + break; + } + } else if (unlikely(XRb =3D=3D XRc)) { + /* both operands same -> just rotation or moving from any of them = */ + switch (optn3) { + case MXU_OPTN3_PTN0: + case MXU_OPTN3_PTN4: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_rotli_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn= 3); + break; + } + } else { + /* the most general case */ + switch (optn3) { + case MXU_OPTN3_PTN0: + { + /* */ + /* XRb XRc */ + /* +---------------+ */ + /* | A B C D | E F G H */ + /* +-------+-------+ */ + /* | */ + /* XRa */ + /* */ + + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } + break; + case MXU_OPTN3_PTN1: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A | B C D E | F G H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF); + tcg_gen_shli_i32(t0, t0, 8); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); + tcg_gen_shri_i32(t1, t1, 24); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN2: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A B | C D E F | G H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); + tcg_gen_shli_i32(t0, t0, 16); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); + tcg_gen_shri_i32(t1, t1, 16); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN3: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A B C | D E F G | H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 =3D tcg_temp_new(); + TCGv_i32 t1 =3D tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF); + tcg_gen_shli_i32(t0, t0, 24); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFFFF00); + tcg_gen_shri_i32(t1, t1, 8); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN4: + { + /* */ + /* XRb XRc */ + /* +---------------+ */ + /* A B C D | E F G H | */ + /* +-------+-------+ */ + /* | */ + /* XRa */ + /* */ + + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } + break; + } + } +} + + +/* + * Decoding engine for MXU + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + */ + +static void decode_opc_mxu__pool00(DisasContext *ctx) +{ + uint32_t opcode =3D extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_S32MAX: + case OPC_MXU_S32MIN: + gen_mxu_S32MAX_S32MIN(ctx); + break; + case OPC_MXU_D16MAX: + case OPC_MXU_D16MIN: + gen_mxu_D16MAX_D16MIN(ctx); + break; + case OPC_MXU_Q8MAX: + case OPC_MXU_Q8MIN: + gen_mxu_Q8MAX_Q8MIN(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + break; + } +} + +static void decode_opc_mxu__pool04(DisasContext *ctx) +{ + uint32_t opcode =3D extract32(ctx->opcode, 20, 1); + + switch (opcode) { + case OPC_MXU_S32LDD: + case OPC_MXU_S32LDDR: + gen_mxu_s32ldd_s32lddr(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + break; + } +} + +static void decode_opc_mxu__pool16(DisasContext *ctx) +{ + uint32_t opcode =3D extract32(ctx->opcode, 18, 3); + + switch (opcode) { + case OPC_MXU_S32ALNI: + gen_mxu_S32ALNI(ctx); + break; + case OPC_MXU_S32NOR: + gen_mxu_S32NOR(ctx); + break; + case OPC_MXU_S32AND: + gen_mxu_S32AND(ctx); + break; + case OPC_MXU_S32OR: + gen_mxu_S32OR(ctx); + break; + case OPC_MXU_S32XOR: + gen_mxu_S32XOR(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + break; + } +} + +static void decode_opc_mxu__pool19(DisasContext *ctx) +{ + uint32_t opcode =3D extract32(ctx->opcode, 22, 2); + + switch (opcode) { + case OPC_MXU_Q8MUL: + case OPC_MXU_Q8MULSU: + gen_mxu_q8mul_q8mulsu(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + break; + } +} + +bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) +{ + uint32_t opcode =3D extract32(insn, 0, 6); + + if (opcode =3D=3D OPC_MXU_S32M2I) { + gen_mxu_s32m2i(ctx); + return true; + } + + if (opcode =3D=3D OPC_MXU_S32I2M) { + gen_mxu_s32i2m(ctx); + return true; + } + + { + TCGv t_mxu_cr =3D tcg_temp_new(); + TCGLabel *l_exit =3D gen_new_label(); + + gen_load_mxu_cr(t_mxu_cr); + tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN); + tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit); + + switch (opcode) { + case OPC_MXU__POOL00: + decode_opc_mxu__pool00(ctx); + break; + case OPC_MXU_D16MUL: + gen_mxu_d16mul(ctx); + break; + case OPC_MXU_D16MAC: + gen_mxu_d16mac(ctx); + break; + case OPC_MXU__POOL04: + decode_opc_mxu__pool04(ctx); + break; + case OPC_MXU_S8LDD: + gen_mxu_s8ldd(ctx); + break; + case OPC_MXU__POOL16: + decode_opc_mxu__pool16(ctx); + break; + case OPC_MXU__POOL19: + decode_opc_mxu__pool19(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); + gen_reserved_instruction(ctx); + } + + gen_set_label(l_exit); + tcg_temp_free(t_mxu_cr); + } + + return true; +} + +#else /* !defined(TARGET_MIPS64) */ + +void mxu_translate_init(void) +{ + g_assert_not_reached(); +} + +bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) +{ + return false; +} + +#endif /* defined(TARGET_MIPS64) */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 68b5dee4bab..0d7482b243a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1129,392 +1129,6 @@ enum { OPC_NMSUB_PS =3D 0x3E | OPC_CP3, }; =20 -/* - * - * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET - * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - * - * - * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MI= PS32 - * instructions set. It is designed to fit the needs of signal, graphical = and - * video processing applications. MXU instruction set is used in Xburst fa= mily - * of microprocessors by Ingenic. - * - * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X1= 6 is - * the control register. - * - * - * The notation used in MXU assembler mnemonics - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * Register operands: - * - * XRa, XRb, XRc, XRd - MXU registers - * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers - * - * Non-register operands: - * - * aptn1 - 1-bit accumulate add/subtract pattern - * aptn2 - 2-bit accumulate add/subtract pattern - * eptn2 - 2-bit execute add/subtract pattern - * optn2 - 2-bit operand pattern - * optn3 - 3-bit operand pattern - * sft4 - 4-bit shift amount - * strd2 - 2-bit stride amount - * - * Prefixes: - * - * Level of parallelism: Operand size: - * S - single operation at a time 32 - word - * D - two operations in parallel 16 - half word - * Q - four operations in parallel 8 - byte - * - * Operations: - * - * ADD - Add or subtract - * ADDC - Add with carry-in - * ACC - Accumulate - * ASUM - Sum together then accumulate (add or subtract) - * ASUMC - Sum together then accumulate (add or subtract) with carry-in - * AVG - Average between 2 operands - * ABD - Absolute difference - * ALN - Align data - * AND - Logical bitwise 'and' operation - * CPS - Copy sign - * EXTR - Extract bits - * I2M - Move from GPR register to MXU register - * LDD - Load data from memory to XRF - * LDI - Load data from memory to XRF (and increase the address base) - * LUI - Load unsigned immediate - * MUL - Multiply - * MULU - Unsigned multiply - * MADD - 64-bit operand add 32x32 product - * MSUB - 64-bit operand subtract 32x32 product - * MAC - Multiply and accumulate (add or subtract) - * MAD - Multiply and add or subtract - * MAX - Maximum between 2 operands - * MIN - Minimum between 2 operands - * M2I - Move from MXU register to GPR register - * MOVZ - Move if zero - * MOVN - Move if non-zero - * NOR - Logical bitwise 'nor' operation - * OR - Logical bitwise 'or' operation - * STD - Store data from XRF to memory - * SDI - Store data from XRF to memory (and increase the address base) - * SLT - Set of less than comparison - * SAD - Sum of absolute differences - * SLL - Logical shift left - * SLR - Logical shift right - * SAR - Arithmetic shift right - * SAT - Saturation - * SFL - Shuffle - * SCOP - Calculate x=E2=80=99s scope (-1, means x<0; 0, means x=3D=3D0= ; 1, means x>0) - * XOR - Logical bitwise 'exclusive or' operation - * - * Suffixes: - * - * E - Expand results - * F - Fixed point multiplication - * L - Low part result - * R - Doing rounding - * V - Variable instead of immediate - * W - Combine above L and V - * - * - * The list of MXU instructions grouped by functionality - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * Load/Store instructions Multiplication instructions - * ----------------------- --------------------------- - * - * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt - * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt - * S32LDDV XRa, Rb, rc, strd2 S32MSUB XRa, XRd, Rs, Rt - * S32STDV XRa, Rb, rc, strd2 S32MSUBU XRa, XRd, Rs, Rt - * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt - * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt - * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2 - * S32SDIV XRa, Rb, rc, strd2 D16MULE XRa, XRb, XRc, optn2 - * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2 - * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, op= tn2 - * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, o= ptn2 - * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, o= ptn2 - * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, o= ptn2 - * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, op= tn2 - * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd - * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd - * S16LDD XRa, Rb, s10, eptn2 Q8MAC XRa, XRb, XRc, XRd, aptn2 - * S16STD XRa, Rb, s10, eptn2 Q8MACSU XRa, XRb, XRc, XRd, aptn2 - * S16LDI XRa, Rb, s10, eptn2 Q8MADL XRa, XRb, XRc, XRd, aptn2 - * S16SDI XRa, Rb, s10, eptn2 - * S8LDD XRa, Rb, s8, eptn3 - * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions - * S8LDI XRa, Rb, s8, eptn3 ------------------------------------- - * S8SDI XRa, Rb, s8, eptn3 - * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2 - * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd - * LXHU Rd, Rs, Rt, strd2 D32ACC XRa, XRb, XRc, XRd, eptn2 - * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2 - * LXBU Rd, Rs, Rt, strd2 D32ASUM XRa, XRb, XRc, XRd, eptn2 - * S32CPS XRa, XRb, XRc - * Q16ADD XRa, XRb, XRc, XRd, eptn2, op= tn2 - * Comparison instructions Q16ACC XRa, XRb, XRc, XRd, eptn2 - * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2 - * D16ASUM XRa, XRb, XRc, XRd, eptn2 - * S32MAX XRa, XRb, XRc D16CPS XRa, XRb, - * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc - * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc - * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2 - * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2 - * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2 - * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc - * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd - * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc - * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc - * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd - * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd - * Q8SLT XRa, XRb, XRc - * Q8SLTU XRa, XRb, XRc - * Q8MOVZ XRa, XRb, XRc Shift instructions - * Q8MOVN XRa, XRb, XRc ------------------ - * - * D32SLL XRa, XRb, XRc, XRd, sft4 - * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4 - * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4 - * D32SARL XRa, XRb, XRc, sft4 - * S32NOR XRa, XRb, XRc D32SLLV XRa, XRb, Rb - * S32AND XRa, XRb, XRc D32SLRV XRa, XRb, Rb - * S32XOR XRa, XRb, XRc D32SARV XRa, XRb, Rb - * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb - * Q16SLL XRa, XRb, XRc, XRd, sft4 - * Q16SLR XRa, XRb, XRc, XRd, sft4 - * Miscellaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4 - * ------------------------- Q16SLLV XRa, XRb, Rb - * Q16SLRV XRa, XRb, Rb - * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb - * S32ALN XRa, XRb, XRc, Rb - * S32ALNI XRa, XRb, XRc, s3 - * S32LUI XRa, s8, optn3 Move instructions - * S32EXTR XRa, XRb, Rb, bits5 ----------------- - * S32EXTRV XRa, XRb, Rs, Rt - * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb - * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb - * - * - * The opcode organization of MXU instructions - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred - * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning = of - * other bits up to the instruction level is as follows: - * - * bits - * 05..00 - * - * =E2=94=8C=E2=94=80 000000 =E2=94=80 OPC_MXU_S32MADD - * =E2=94=9C=E2=94=80 000001 =E2=94=80 OPC_MXU_S32MADDU - * =E2=94=9C=E2=94=80 000010 =E2=94=80 (non-MXU = OPC_MUL) - * =E2=94=82 - * =E2=94=82 20..18 - * =E2=94=9C=E2=94=80 000011 =E2=94=80 OPC_MXU__POOL00 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32MAX - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32MIN - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MAX - * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MIN - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8MAX - * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8MIN - * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_Q8SLT - * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8SLTU - * =E2=94=9C=E2=94=80 000100 =E2=94=80 OPC_MXU_S32MSUB - * =E2=94=9C=E2=94=80 000101 =E2=94=80 OPC_MXU_S32MSUBU 20..18 - * =E2=94=9C=E2=94=80 000110 =E2=94=80 OPC_MXU__POOL01 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32SLT - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_D16SLT - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16AVG - * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16AVGR - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8AVG - * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_Q8AVGR - * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_Q8ADD - * =E2=94=82 - * =E2=94=82 20..18 - * =E2=94=9C=E2=94=80 000111 =E2=94=80 OPC_MXU__POOL02 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_S32CPS - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16CPS - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q8ABD - * =E2=94=82 =E2=94=94=E2=94=80 110 = =E2=94=80 OPC_MXU_Q16SAT - * =E2=94=9C=E2=94=80 001000 =E2=94=80 OPC_MXU_D16MUL - * =E2=94=82 25..24 - * =E2=94=9C=E2=94=80 001001 =E2=94=80 OPC_MXU__POOL03 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D16MULF - * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_D16MULE - * =E2=94=9C=E2=94=80 001010 =E2=94=80 OPC_MXU_D16MAC - * =E2=94=9C=E2=94=80 001011 =E2=94=80 OPC_MXU_D16MACF - * =E2=94=9C=E2=94=80 001100 =E2=94=80 OPC_MXU_D16MADL - * =E2=94=9C=E2=94=80 001101 =E2=94=80 OPC_MXU_S16MAD - * =E2=94=9C=E2=94=80 001110 =E2=94=80 OPC_MXU_Q16ADD - * =E2=94=9C=E2=94=80 001111 =E2=94=80 OPC_MXU_D16MACE 23 - * =E2=94=82 =E2=94=8C=E2=94=80 0 =E2= =94=80 OPC_MXU_S32LDD - * =E2=94=9C=E2=94=80 010000 =E2=94=80 OPC_MXU__POOL04 =E2=94=80= =E2=94=B4=E2=94=80 1 =E2=94=80 OPC_MXU_S32LDDR - * =E2=94=82 - * =E2=94=82 23 - * =E2=94=9C=E2=94=80 010001 =E2=94=80 OPC_MXU__POOL05 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32STD - * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32STDR - * =E2=94=82 - * =E2=94=82 13..10 - * =E2=94=9C=E2=94=80 010010 =E2=94=80 OPC_MXU__POOL06 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDDV - * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDDVR - * =E2=94=82 - * =E2=94=82 13..10 - * =E2=94=9C=E2=94=80 010011 =E2=94=80 OPC_MXU__POOL07 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32STDV - * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32STDVR - * =E2=94=82 - * =E2=94=82 23 - * =E2=94=9C=E2=94=80 010100 =E2=94=80 OPC_MXU__POOL08 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32LDI - * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32LDIR - * =E2=94=82 - * =E2=94=82 23 - * =E2=94=9C=E2=94=80 010101 =E2=94=80 OPC_MXU__POOL09 =E2=94=80= =E2=94=AC=E2=94=80 0 =E2=94=80 OPC_MXU_S32SDI - * =E2=94=82 =E2=94=94=E2=94=80 1 =E2= =94=80 OPC_MXU_S32SDIR - * =E2=94=82 - * =E2=94=82 13..10 - * =E2=94=9C=E2=94=80 010110 =E2=94=80 OPC_MXU__POOL10 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32LDIV - * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32LDIVR - * =E2=94=82 - * =E2=94=82 13..10 - * =E2=94=9C=E2=94=80 010111 =E2=94=80 OPC_MXU__POOL11 =E2=94=80= =E2=94=AC=E2=94=80 0000 =E2=94=80 OPC_MXU_S32SDIV - * =E2=94=82 =E2=94=94=E2=94=80 0001 = =E2=94=80 OPC_MXU_S32SDIVR - * =E2=94=9C=E2=94=80 011000 =E2=94=80 OPC_MXU_D32ADD - * =E2=94=82 23..22 - * MXU =E2=94=9C=E2=94=80 011001 =E2=94=80 OPC_MXU__POOL12 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_D32ACC - * opcodes =E2=94=80=E2=94=A4 =E2=94=9C=E2=94= =80 01 =E2=94=80 OPC_MXU_D32ACCM - * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_D32ASUM - * =E2=94=9C=E2=94=80 011010 =E2=94=80 - * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 011011 =E2=94=80 OPC_MXU__POOL13 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q16ACC - * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_Q16ACCM - * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q16ASUM - * =E2=94=82 - * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 011100 =E2=94=80 OPC_MXU__POOL14 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8ADDE - * =E2=94=82 =E2=94=9C=E2=94=80 01 =E2= =94=80 OPC_MXU_D8SUM - * =E2=94=9C=E2=94=80 011101 =E2=94=80 OPC_MXU_Q8ACCE =E2=94=94= =E2=94=80 10 =E2=94=80 OPC_MXU_D8SUMC - * =E2=94=9C=E2=94=80 011110 =E2=94=80 - * =E2=94=9C=E2=94=80 011111 =E2=94=80 - * =E2=94=9C=E2=94=80 100000 =E2=94=80 (overlaps= with CLZ) - * =E2=94=9C=E2=94=80 100001 =E2=94=80 (overlaps= with CLO) - * =E2=94=9C=E2=94=80 100010 =E2=94=80 OPC_MXU_S8LDD - * =E2=94=9C=E2=94=80 100011 =E2=94=80 OPC_MXU_S8STD 15..14 - * =E2=94=9C=E2=94=80 100100 =E2=94=80 OPC_MXU_S8LDI =E2=94=8C= =E2=94=80 00 =E2=94=80 OPC_MXU_S32MUL - * =E2=94=9C=E2=94=80 100101 =E2=94=80 OPC_MXU_S8SDI =E2=94=9C= =E2=94=80 00 =E2=94=80 OPC_MXU_S32MULU - * =E2=94=82 =E2=94=9C=E2=94=80 00 =E2= =94=80 OPC_MXU_S32EXTR - * =E2=94=9C=E2=94=80 100110 =E2=94=80 OPC_MXU__POOL15 =E2=94=80= =E2=94=B4=E2=94=80 00 =E2=94=80 OPC_MXU_S32EXTRV - * =E2=94=82 - * =E2=94=82 20..18 - * =E2=94=9C=E2=94=80 100111 =E2=94=80 OPC_MXU__POOL16 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_D32SARW - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_S32ALN - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_S32ALNI - * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_S32LUI - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32NOR - * =E2=94=82 =E2=94=9C=E2=94=80 101 = =E2=94=80 OPC_MXU_S32AND - * =E2=94=82 =E2=94=9C=E2=94=80 110 = =E2=94=80 OPC_MXU_S32OR - * =E2=94=82 =E2=94=94=E2=94=80 111 = =E2=94=80 OPC_MXU_S32XOR - * =E2=94=82 - * =E2=94=82 7..5 - * =E2=94=9C=E2=94=80 101000 =E2=94=80 OPC_MXU__POOL17 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_LXB - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_LXH - * =E2=94=9C=E2=94=80 101001 =E2=94=80 =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_LXW - * =E2=94=9C=E2=94=80 101010 =E2=94=80 OPC_MXU_S16LDD =E2=94=9C= =E2=94=80 100 =E2=94=80 OPC_MXU_LXBU - * =E2=94=9C=E2=94=80 101011 =E2=94=80 OPC_MXU_S16STD =E2=94=94= =E2=94=80 101 =E2=94=80 OPC_MXU_LXHU - * =E2=94=9C=E2=94=80 101100 =E2=94=80 OPC_MXU_S16LDI - * =E2=94=9C=E2=94=80 101101 =E2=94=80 OPC_MXU_S16SDI - * =E2=94=9C=E2=94=80 101110 =E2=94=80 OPC_MXU_S32M2I - * =E2=94=9C=E2=94=80 101111 =E2=94=80 OPC_MXU_S32I2M - * =E2=94=9C=E2=94=80 110000 =E2=94=80 OPC_MXU_D32SLL - * =E2=94=9C=E2=94=80 110001 =E2=94=80 OPC_MXU_D32SLR 20..18 - * =E2=94=9C=E2=94=80 110010 =E2=94=80 OPC_MXU_D32SARL =E2=94=8C= =E2=94=80 000 =E2=94=80 OPC_MXU_D32SLLV - * =E2=94=9C=E2=94=80 110011 =E2=94=80 OPC_MXU_D32SAR =E2=94=9C= =E2=94=80 001 =E2=94=80 OPC_MXU_D32SLRV - * =E2=94=9C=E2=94=80 110100 =E2=94=80 OPC_MXU_Q16SLL =E2=94=9C= =E2=94=80 010 =E2=94=80 OPC_MXU_D32SARV - * =E2=94=9C=E2=94=80 110101 =E2=94=80 OPC_MXU_Q16SLR =E2=94=9C= =E2=94=80 011 =E2=94=80 OPC_MXU_Q16SLLV - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_Q16SLRV - * =E2=94=9C=E2=94=80 110110 =E2=94=80 OPC_MXU__POOL18 =E2=94=80= =E2=94=B4=E2=94=80 101 =E2=94=80 OPC_MXU_Q16SARV - * =E2=94=82 - * =E2=94=9C=E2=94=80 110111 =E2=94=80 OPC_MXU_Q16SAR - * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 111000 =E2=94=80 OPC_MXU__POOL19 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MUL - * =E2=94=82 =E2=94=94=E2=94=80 01 =E2= =94=80 OPC_MXU_Q8MULSU - * =E2=94=82 - * =E2=94=82 20..18 - * =E2=94=9C=E2=94=80 111001 =E2=94=80 OPC_MXU__POOL20 =E2=94=80= =E2=94=AC=E2=94=80 000 =E2=94=80 OPC_MXU_Q8MOVZ - * =E2=94=82 =E2=94=9C=E2=94=80 001 = =E2=94=80 OPC_MXU_Q8MOVN - * =E2=94=82 =E2=94=9C=E2=94=80 010 = =E2=94=80 OPC_MXU_D16MOVZ - * =E2=94=82 =E2=94=9C=E2=94=80 011 = =E2=94=80 OPC_MXU_D16MOVN - * =E2=94=82 =E2=94=9C=E2=94=80 100 = =E2=94=80 OPC_MXU_S32MOVZ - * =E2=94=82 =E2=94=94=E2=94=80 101 = =E2=94=80 OPC_MXU_S32MOVN - * =E2=94=82 - * =E2=94=82 23..22 - * =E2=94=9C=E2=94=80 111010 =E2=94=80 OPC_MXU__POOL21 =E2=94=80= =E2=94=AC=E2=94=80 00 =E2=94=80 OPC_MXU_Q8MAC - * =E2=94=82 =E2=94=94=E2=94=80 10 =E2= =94=80 OPC_MXU_Q8MACSU - * =E2=94=9C=E2=94=80 111011 =E2=94=80 OPC_MXU_Q16SCOP - * =E2=94=9C=E2=94=80 111100 =E2=94=80 OPC_MXU_Q8MADL - * =E2=94=9C=E2=94=80 111101 =E2=94=80 OPC_MXU_S32SFL - * =E2=94=9C=E2=94=80 111110 =E2=94=80 OPC_MXU_Q8SAD - * =E2=94=94=E2=94=80 111111 =E2=94=80 (overlaps= with SDBBP) - * - * - * Compiled after: - * - * "XBurst=C2=AE Instruction Set Architecture MIPS eXtension/enhanced Un= it - * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2,= 2017 - */ - -enum { - OPC_MXU__POOL00 =3D 0x03, - OPC_MXU_D16MUL =3D 0x08, - OPC_MXU_D16MAC =3D 0x0A, - OPC_MXU__POOL04 =3D 0x10, - OPC_MXU_S8LDD =3D 0x22, - OPC_MXU__POOL16 =3D 0x27, - OPC_MXU_S32M2I =3D 0x2E, - OPC_MXU_S32I2M =3D 0x2F, - OPC_MXU__POOL19 =3D 0x38, -}; - - -/* - * MXU pool 00 - */ -enum { - OPC_MXU_S32MAX =3D 0x00, - OPC_MXU_S32MIN =3D 0x01, - OPC_MXU_D16MAX =3D 0x02, - OPC_MXU_D16MIN =3D 0x03, - OPC_MXU_Q8MAX =3D 0x04, - OPC_MXU_Q8MIN =3D 0x05, -}; - -/* - * MXU pool 04 - */ -enum { - OPC_MXU_S32LDD =3D 0x00, - OPC_MXU_S32LDDR =3D 0x01, -}; - -/* - * MXU pool 16 - */ -enum { - OPC_MXU_S32ALNI =3D 0x02, - OPC_MXU_S32NOR =3D 0x04, - OPC_MXU_S32AND =3D 0x05, - OPC_MXU_S32OR =3D 0x06, - OPC_MXU_S32XOR =3D 0x07, -}; - -/* - * MXU pool 19 - */ -enum { - OPC_MXU_Q8MUL =3D 0x00, - OPC_MXU_Q8MULSU =3D 0x01, -}; - /* * Overview of the TX79-specific instruction set * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -1965,12 +1579,6 @@ static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; TCGv_i64 fpu_f64[32]; =20 -#if !defined(TARGET_MIPS64) -/* MXU registers */ -static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; -static TCGv mxu_CR; -#endif - #include "exec/gen-icount.h" =20 #define gen_helper_0e0i(name, arg) do { \ @@ -2040,31 +1648,6 @@ static const char * const fregnames[] =3D { "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; =20 -#if !defined(TARGET_MIPS64) -static const char * const mxuregnames[] =3D { - "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", - "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", -}; - -void mxu_translate_init(void) -{ - for (unsigned i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { - mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, active_tc.m= xu_gpr[i]), - mxuregnames[i]); - } - - mxu_CR =3D tcg_global_mem_new(cpu_env, - offsetof(CPUMIPSState, active_tc.mxu_cr), - mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); -} -#else /* !defined(TARGET_MIPS64) */ -void mxu_translate_init(void) -{ - g_assert_not_reached(); -} -#endif /* defined(TARGET_MIPS64) */ - /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) { @@ -2148,38 +1731,6 @@ static inline void gen_store_srsgpr(int from, int to) } } =20 -#if !defined(TARGET_MIPS64) -/* MXU General purpose registers moves. */ -static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg) -{ - if (reg =3D=3D 0) { - tcg_gen_movi_tl(t, 0); - } else if (reg <=3D 15) { - tcg_gen_mov_tl(t, mxu_gpr[reg - 1]); - } -} - -static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg) -{ - if (reg > 0 && reg <=3D 15) { - tcg_gen_mov_tl(mxu_gpr[reg - 1], t); - } -} - -/* MXU control register moves. */ -static inline void gen_load_mxu_cr(TCGv t) -{ - tcg_gen_mov_tl(t, mxu_CR); -} - -static inline void gen_store_mxu_cr(TCGv t) -{ - /* TODO: Add handling of RW rules for MXU_CR. */ - tcg_gen_mov_tl(mxu_CR, t); -} -#endif - - /* Tests */ static inline void gen_save_pc(target_ulong pc) { @@ -24695,1170 +24246,6 @@ static void gen_mmi_pcpyud(DisasContext *ctx) =20 #endif =20 - -#if !defined(TARGET_MIPS64) - -/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */ -#define MXU_APTN1_A 0 -#define MXU_APTN1_S 1 - -/* MXU accumulate add/subtract 2-bit pattern 'aptn2' */ -#define MXU_APTN2_AA 0 -#define MXU_APTN2_AS 1 -#define MXU_APTN2_SA 2 -#define MXU_APTN2_SS 3 - -/* MXU execute add/subtract 2-bit pattern 'eptn2' */ -#define MXU_EPTN2_AA 0 -#define MXU_EPTN2_AS 1 -#define MXU_EPTN2_SA 2 -#define MXU_EPTN2_SS 3 - -/* MXU operand getting pattern 'optn2' */ -#define MXU_OPTN2_PTN0 0 -#define MXU_OPTN2_PTN1 1 -#define MXU_OPTN2_PTN2 2 -#define MXU_OPTN2_PTN3 3 -/* alternative naming scheme for 'optn2' */ -#define MXU_OPTN2_WW 0 -#define MXU_OPTN2_LW 1 -#define MXU_OPTN2_HW 2 -#define MXU_OPTN2_XW 3 - -/* MXU operand getting pattern 'optn3' */ -#define MXU_OPTN3_PTN0 0 -#define MXU_OPTN3_PTN1 1 -#define MXU_OPTN3_PTN2 2 -#define MXU_OPTN3_PTN3 3 -#define MXU_OPTN3_PTN4 4 -#define MXU_OPTN3_PTN5 5 -#define MXU_OPTN3_PTN6 6 -#define MXU_OPTN3_PTN7 7 - - -/* - * S32I2M XRa, rb - Register move from GRF to XRF - */ -static void gen_mxu_s32i2m(DisasContext *ctx) -{ - TCGv t0; - uint32_t XRa, Rb; - - t0 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 5); - Rb =3D extract32(ctx->opcode, 16, 5); - - gen_load_gpr(t0, Rb); - if (XRa <=3D 15) { - gen_store_mxu_gpr(t0, XRa); - } else if (XRa =3D=3D 16) { - gen_store_mxu_cr(t0); - } - - tcg_temp_free(t0); -} - -/* - * S32M2I XRa, rb - Register move from XRF to GRF - */ -static void gen_mxu_s32m2i(DisasContext *ctx) -{ - TCGv t0; - uint32_t XRa, Rb; - - t0 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 5); - Rb =3D extract32(ctx->opcode, 16, 5); - - if (XRa <=3D 15) { - gen_load_mxu_gpr(t0, XRa); - } else if (XRa =3D=3D 16) { - gen_load_mxu_cr(t0); - } - - gen_store_gpr(t0, Rb); - - tcg_temp_free(t0); -} - -/* - * S8LDD XRa, Rb, s8, optn3 - Load a byte from memory to XRF - */ -static void gen_mxu_s8ldd(DisasContext *ctx) -{ - TCGv t0, t1; - uint32_t XRa, Rb, s8, optn3; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - s8 =3D extract32(ctx->opcode, 10, 8); - optn3 =3D extract32(ctx->opcode, 18, 3); - Rb =3D extract32(ctx->opcode, 21, 5); - - gen_load_gpr(t0, Rb); - tcg_gen_addi_tl(t0, t0, (int8_t)s8); - - switch (optn3) { - /* XRa[7:0] =3D tmp8 */ - case MXU_OPTN3_PTN0: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - gen_load_mxu_gpr(t0, XRa); - tcg_gen_deposit_tl(t0, t0, t1, 0, 8); - break; - /* XRa[15:8] =3D tmp8 */ - case MXU_OPTN3_PTN1: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - gen_load_mxu_gpr(t0, XRa); - tcg_gen_deposit_tl(t0, t0, t1, 8, 8); - break; - /* XRa[23:16] =3D tmp8 */ - case MXU_OPTN3_PTN2: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - gen_load_mxu_gpr(t0, XRa); - tcg_gen_deposit_tl(t0, t0, t1, 16, 8); - break; - /* XRa[31:24] =3D tmp8 */ - case MXU_OPTN3_PTN3: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - gen_load_mxu_gpr(t0, XRa); - tcg_gen_deposit_tl(t0, t0, t1, 24, 8); - break; - /* XRa =3D {8'b0, tmp8, 8'b0, tmp8} */ - case MXU_OPTN3_PTN4: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_deposit_tl(t0, t1, t1, 16, 16); - break; - /* XRa =3D {tmp8, 8'b0, tmp8, 8'b0} */ - case MXU_OPTN3_PTN5: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_shli_tl(t1, t1, 8); - tcg_gen_deposit_tl(t0, t1, t1, 16, 16); - break; - /* XRa =3D {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */ - case MXU_OPTN3_PTN6: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB); - tcg_gen_mov_tl(t0, t1); - tcg_gen_andi_tl(t0, t0, 0xFF00FFFF); - tcg_gen_shli_tl(t1, t1, 16); - tcg_gen_or_tl(t0, t0, t1); - break; - /* XRa =3D {tmp8, tmp8, tmp8, tmp8} */ - case MXU_OPTN3_PTN7: - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); - tcg_gen_deposit_tl(t1, t1, t1, 8, 8); - tcg_gen_deposit_tl(t0, t1, t1, 16, 16); - break; - } - - gen_store_mxu_gpr(t0, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); -} - -/* - * D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication - */ -static void gen_mxu_d16mul(DisasContext *ctx) -{ - TCGv t0, t1, t2, t3; - uint32_t XRa, XRb, XRc, XRd, optn2; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - t2 =3D tcg_temp_new(); - t3 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRc =3D extract32(ctx->opcode, 14, 4); - XRd =3D extract32(ctx->opcode, 18, 4); - optn2 =3D extract32(ctx->opcode, 22, 2); - - gen_load_mxu_gpr(t1, XRb); - tcg_gen_sextract_tl(t0, t1, 0, 16); - tcg_gen_sextract_tl(t1, t1, 16, 16); - gen_load_mxu_gpr(t3, XRc); - tcg_gen_sextract_tl(t2, t3, 0, 16); - tcg_gen_sextract_tl(t3, t3, 16, 16); - - switch (optn2) { - case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t1, t3); - tcg_gen_mul_tl(t2, t0, t2); - break; - case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t0, t3); - tcg_gen_mul_tl(t2, t0, t2); - break; - case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t1, t3); - tcg_gen_mul_tl(t2, t1, t2); - break; - case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t0, t3); - tcg_gen_mul_tl(t2, t1, t2); - break; - } - gen_store_mxu_gpr(t3, XRa); - gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); -} - -/* - * D16MAC XRa, XRb, XRc, XRd, aptn2, optn2 - Signed 16 bit pattern multiply - * and accumulate - */ -static void gen_mxu_d16mac(DisasContext *ctx) -{ - TCGv t0, t1, t2, t3; - uint32_t XRa, XRb, XRc, XRd, optn2, aptn2; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - t2 =3D tcg_temp_new(); - t3 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRc =3D extract32(ctx->opcode, 14, 4); - XRd =3D extract32(ctx->opcode, 18, 4); - optn2 =3D extract32(ctx->opcode, 22, 2); - aptn2 =3D extract32(ctx->opcode, 24, 2); - - gen_load_mxu_gpr(t1, XRb); - tcg_gen_sextract_tl(t0, t1, 0, 16); - tcg_gen_sextract_tl(t1, t1, 16, 16); - - gen_load_mxu_gpr(t3, XRc); - tcg_gen_sextract_tl(t2, t3, 0, 16); - tcg_gen_sextract_tl(t3, t3, 16, 16); - - switch (optn2) { - case MXU_OPTN2_WW: /* XRB.H*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t1, t3); - tcg_gen_mul_tl(t2, t0, t2); - break; - case MXU_OPTN2_LW: /* XRB.L*XRC.H =3D=3D lop, XRB.L*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t0, t3); - tcg_gen_mul_tl(t2, t0, t2); - break; - case MXU_OPTN2_HW: /* XRB.H*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t1, t3); - tcg_gen_mul_tl(t2, t1, t2); - break; - case MXU_OPTN2_XW: /* XRB.L*XRC.H =3D=3D lop, XRB.H*XRC.L =3D=3D rop */ - tcg_gen_mul_tl(t3, t0, t3); - tcg_gen_mul_tl(t2, t1, t2); - break; - } - gen_load_mxu_gpr(t0, XRa); - gen_load_mxu_gpr(t1, XRd); - - switch (aptn2) { - case MXU_APTN2_AA: - tcg_gen_add_tl(t3, t0, t3); - tcg_gen_add_tl(t2, t1, t2); - break; - case MXU_APTN2_AS: - tcg_gen_add_tl(t3, t0, t3); - tcg_gen_sub_tl(t2, t1, t2); - break; - case MXU_APTN2_SA: - tcg_gen_sub_tl(t3, t0, t3); - tcg_gen_add_tl(t2, t1, t2); - break; - case MXU_APTN2_SS: - tcg_gen_sub_tl(t3, t0, t3); - tcg_gen_sub_tl(t2, t1, t2); - break; - } - gen_store_mxu_gpr(t3, XRa); - gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); -} - -/* - * Q8MUL XRa, XRb, XRc, XRd - Parallel unsigned 8 bit pattern multiply - * Q8MULSU XRa, XRb, XRc, XRd - Parallel signed 8 bit pattern multiply - */ -static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) -{ - TCGv t0, t1, t2, t3, t4, t5, t6, t7; - uint32_t XRa, XRb, XRc, XRd, sel; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - t2 =3D tcg_temp_new(); - t3 =3D tcg_temp_new(); - t4 =3D tcg_temp_new(); - t5 =3D tcg_temp_new(); - t6 =3D tcg_temp_new(); - t7 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRc =3D extract32(ctx->opcode, 14, 4); - XRd =3D extract32(ctx->opcode, 18, 4); - sel =3D extract32(ctx->opcode, 22, 2); - - gen_load_mxu_gpr(t3, XRb); - gen_load_mxu_gpr(t7, XRc); - - if (sel =3D=3D 0x2) { - /* Q8MULSU */ - tcg_gen_ext8s_tl(t0, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8s_tl(t1, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8s_tl(t2, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8s_tl(t3, t3); - } else { - /* Q8MUL */ - tcg_gen_ext8u_tl(t0, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8u_tl(t1, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8u_tl(t2, t3); - tcg_gen_shri_tl(t3, t3, 8); - tcg_gen_ext8u_tl(t3, t3); - } - - tcg_gen_ext8u_tl(t4, t7); - tcg_gen_shri_tl(t7, t7, 8); - tcg_gen_ext8u_tl(t5, t7); - tcg_gen_shri_tl(t7, t7, 8); - tcg_gen_ext8u_tl(t6, t7); - tcg_gen_shri_tl(t7, t7, 8); - tcg_gen_ext8u_tl(t7, t7); - - tcg_gen_mul_tl(t0, t0, t4); - tcg_gen_mul_tl(t1, t1, t5); - tcg_gen_mul_tl(t2, t2, t6); - tcg_gen_mul_tl(t3, t3, t7); - - tcg_gen_andi_tl(t0, t0, 0xFFFF); - tcg_gen_andi_tl(t1, t1, 0xFFFF); - tcg_gen_andi_tl(t2, t2, 0xFFFF); - tcg_gen_andi_tl(t3, t3, 0xFFFF); - - tcg_gen_shli_tl(t1, t1, 16); - tcg_gen_shli_tl(t3, t3, 16); - - tcg_gen_or_tl(t0, t0, t1); - tcg_gen_or_tl(t1, t2, t3); - - gen_store_mxu_gpr(t0, XRd); - gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); - tcg_temp_free(t4); - tcg_temp_free(t5); - tcg_temp_free(t6); - tcg_temp_free(t7); -} - -/* - * S32LDD XRa, Rb, S12 - Load a word from memory to XRF - * S32LDDR XRa, Rb, S12 - Load a word from memory to XRF, reversed byte se= q. - */ -static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) -{ - TCGv t0, t1; - uint32_t XRa, Rb, s12, sel; - - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - - XRa =3D extract32(ctx->opcode, 6, 4); - s12 =3D extract32(ctx->opcode, 10, 10); - sel =3D extract32(ctx->opcode, 20, 1); - Rb =3D extract32(ctx->opcode, 21, 5); - - gen_load_gpr(t0, Rb); - - tcg_gen_movi_tl(t1, s12); - tcg_gen_shli_tl(t1, t1, 2); - if (s12 & 0x200) { - tcg_gen_ori_tl(t1, t1, 0xFFFFF000); - } - tcg_gen_add_tl(t1, t0, t1); - tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_SL); - - if (sel =3D=3D 1) { - /* S32LDDR */ - tcg_gen_bswap32_tl(t1, t1); - } - gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); -} - - -/* - * MXU instruction category: logic - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * S32NOR S32AND S32OR S32XOR - */ - -/* - * S32NOR XRa, XRb, XRc - * Update XRa with the result of logical bitwise 'nor' operation - * applied to the content of XRb and XRc. - */ -static void gen_mxu_S32NOR(DisasContext *ctx) -{ - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 1s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0xFFFFFFFF); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just set destination to the negation of XR= c */ - tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } else if (unlikely(XRc =3D=3D 0)) { - /* XRa zero register -> just set destination to the negation of XR= b */ - tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to the negation of X= Rb */ - tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - tcg_gen_nor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); - } -} - -/* - * S32AND XRa, XRb, XRc - * Update XRa with the result of logical bitwise 'and' operation - * applied to the content of XRb and XRc. - */ -static void gen_mxu_S32AND(DisasContext *ctx) -{ - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { - /* one of operands zero register -> just set destination to all 0s= */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - tcg_gen_and_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); - } -} - -/* - * S32OR XRa, XRb, XRc - * Update XRa with the result of logical bitwise 'or' operation - * applied to the content of XRb and XRc. - */ -static void gen_mxu_S32OR(DisasContext *ctx) -{ - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 0s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just set destination to the content of XRc= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } else if (unlikely(XRc =3D=3D 0)) { - /* XRc zero register -> just set destination to the content of XRb= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1= ]); - } -} - -/* - * S32XOR XRa, XRb, XRc - * Update XRa with the result of logical bitwise 'xor' operation - * applied to the content of XRb and XRc. - */ -static void gen_mxu_S32XOR(DisasContext *ctx) -{ - uint32_t pad, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 0s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just set destination to the content of XRc= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } else if (unlikely(XRc =3D=3D 0)) { - /* XRc zero register -> just set destination to the content of XRb= */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to all 0s */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else { - /* the most general case */ - tcg_gen_xor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - = 1]); - } -} - - -/* - * MXU instruction category max/min - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * S32MAX D16MAX Q8MAX - * S32MIN D16MIN Q8MIN - */ - -/* - * S32MAX XRa, XRb, XRc - * Update XRa with the maximum of signed 32-bit integers contained - * in XRb and XRc. - * - * S32MIN XRa, XRb, XRc - * Update XRa with the minimum of signed 32-bit integers contained - * in XRb and XRc. - */ -static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx) -{ - uint32_t pad, opc, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - opc =3D extract32(ctx->opcode, 18, 3); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { - /* exactly one operand is zero register - find which one is not...= */ - uint32_t XRx =3D XRb ? XRb : XRc; - /* ...and do max/min operation with one operand 0 */ - if (opc =3D=3D OPC_MXU_S32MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); - } - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - if (opc =3D=3D OPC_MXU_S32MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], - mxu_gpr[XRc - 1]); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], - mxu_gpr[XRc - 1]); - } - } -} - -/* - * D16MAX - * Update XRa with the 16-bit-wise maximums of signed integers - * contained in XRb and XRc. - * - * D16MIN - * Update XRa with the 16-bit-wise minimums of signed integers - * contained in XRb and XRc. - */ -static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) -{ - uint32_t pad, opc, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - opc =3D extract32(ctx->opcode, 18, 3); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRc =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRa =3D=3D 0))) { - /* both operands zero registers -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRc - 1], 0); - } else if (unlikely((XRb =3D=3D 0) || (XRa =3D=3D 0))) { - /* exactly one operand is zero register - find which one is not...= */ - uint32_t XRx =3D XRb ? XRb : XRc; - /* ...and do half-word-wise max/min with one operand 0 */ - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_const_i32(0); - - /* the left half-word first */ - tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); - if (opc =3D=3D OPC_MXU_D16MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); - } - - /* the right half-word */ - tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF); - /* move half-words to the leftmost position */ - tcg_gen_shli_i32(t0, t0, 16); - /* t0 will be max/min of t0 and t1 */ - if (opc =3D=3D OPC_MXU_D16MAX) { - tcg_gen_smax_i32(t0, t0, t1); - } else { - tcg_gen_smin_i32(t0, t0, t1); - } - /* return resulting half-words to its original position */ - tcg_gen_shri_i32(t0, t0, 16); - /* finally update the destination */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - - /* the left half-word first */ - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000); - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); - if (opc =3D=3D OPC_MXU_D16MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); - } - - /* the right half-word */ - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF); - /* move half-words to the leftmost position */ - tcg_gen_shli_i32(t0, t0, 16); - tcg_gen_shli_i32(t1, t1, 16); - /* t0 will be max/min of t0 and t1 */ - if (opc =3D=3D OPC_MXU_D16MAX) { - tcg_gen_smax_i32(t0, t0, t1); - } else { - tcg_gen_smin_i32(t0, t0, t1); - } - /* return resulting half-words to its original position */ - tcg_gen_shri_i32(t0, t0, 16); - /* finally update the destination */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } -} - -/* - * Q8MAX - * Update XRa with the 8-bit-wise maximums of signed integers - * contained in XRb and XRc. - * - * Q8MIN - * Update XRa with the 8-bit-wise minimums of signed integers - * contained in XRb and XRc. - */ -static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) -{ - uint32_t pad, opc, XRc, XRb, XRa; - - pad =3D extract32(ctx->opcode, 21, 5); - opc =3D extract32(ctx->opcode, 18, 3); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to zero */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely((XRb =3D=3D 0) || (XRc =3D=3D 0))) { - /* exactly one operand is zero register - make it be the first...*/ - uint32_t XRx =3D XRb ? XRb : XRc; - /* ...and do byte-wise max/min with one operand 0 */ - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_const_i32(0); - int32_t i; - - /* the leftmost byte (byte 3) first */ - tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000); - if (opc =3D=3D OPC_MXU_Q8MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); - } - - /* bytes 2, 1, 0 */ - for (i =3D 2; i >=3D 0; i--) { - /* extract the byte */ - tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF << (8 * i)); - /* move the byte to the leftmost position */ - tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); - /* t0 will be max/min of t0 and t1 */ - if (opc =3D=3D OPC_MXU_Q8MAX) { - tcg_gen_smax_i32(t0, t0, t1); - } else { - tcg_gen_smin_i32(t0, t0, t1); - } - /* return resulting byte to its original position */ - tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); - /* finally update the destination */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - } - - tcg_temp_free(t1); - tcg_temp_free(t0); - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just set destination to one of them */ - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } else { - /* the most general case */ - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - int32_t i; - - /* the leftmost bytes (bytes 3) first */ - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000); - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); - if (opc =3D=3D OPC_MXU_Q8MAX) { - tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); - } else { - tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); - } - - /* bytes 2, 1, 0 */ - for (i =3D 2; i >=3D 0; i--) { - /* extract corresponding bytes */ - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF << (8 * i)); - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF << (8 * i)); - /* move the bytes to the leftmost position */ - tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); - tcg_gen_shli_i32(t1, t1, 8 * (3 - i)); - /* t0 will be max/min of t0 and t1 */ - if (opc =3D=3D OPC_MXU_Q8MAX) { - tcg_gen_smax_i32(t0, t0, t1); - } else { - tcg_gen_smin_i32(t0, t0, t1); - } - /* return resulting byte to its original position */ - tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); - /* finally update the destination */ - tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - } - - tcg_temp_free(t1); - tcg_temp_free(t0); - } -} - - -/* - * MXU instruction category: align - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * S32ALN S32ALNI - */ - -/* - * S32ALNI XRc, XRb, XRa, optn3 - * Arrange bytes from XRb and XRc according to one of five sets of - * rules determined by optn3, and place the result in XRa. - */ -static void gen_mxu_S32ALNI(DisasContext *ctx) -{ - uint32_t optn3, pad, XRc, XRb, XRa; - - optn3 =3D extract32(ctx->opcode, 23, 3); - pad =3D extract32(ctx->opcode, 21, 2); - XRc =3D extract32(ctx->opcode, 14, 4); - XRb =3D extract32(ctx->opcode, 10, 4); - XRa =3D extract32(ctx->opcode, 6, 4); - - if (unlikely(pad !=3D 0)) { - /* opcode padding incorrect -> do nothing */ - } else if (unlikely(XRa =3D=3D 0)) { - /* destination is zero register -> do nothing */ - } else if (unlikely((XRb =3D=3D 0) && (XRc =3D=3D 0))) { - /* both operands zero registers -> just set destination to all 0s = */ - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - } else if (unlikely(XRb =3D=3D 0)) { - /* XRb zero register -> just appropriatelly shift XRc into XRa */ - switch (optn3) { - case MXU_OPTN3_PTN0: - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - break; - case MXU_OPTN3_PTN1: - case MXU_OPTN3_PTN2: - case MXU_OPTN3_PTN3: - tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1], - 8 * (4 - optn3)); - break; - case MXU_OPTN3_PTN4: - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - break; - } - } else if (unlikely(XRc =3D=3D 0)) { - /* XRc zero register -> just appropriatelly shift XRb into XRa */ - switch (optn3) { - case MXU_OPTN3_PTN0: - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - break; - case MXU_OPTN3_PTN1: - case MXU_OPTN3_PTN2: - case MXU_OPTN3_PTN3: - tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3= ); - break; - case MXU_OPTN3_PTN4: - tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); - break; - } - } else if (unlikely(XRb =3D=3D XRc)) { - /* both operands same -> just rotation or moving from any of them = */ - switch (optn3) { - case MXU_OPTN3_PTN0: - case MXU_OPTN3_PTN4: - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - break; - case MXU_OPTN3_PTN1: - case MXU_OPTN3_PTN2: - case MXU_OPTN3_PTN3: - tcg_gen_rotli_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn= 3); - break; - } - } else { - /* the most general case */ - switch (optn3) { - case MXU_OPTN3_PTN0: - { - /* */ - /* XRb XRc */ - /* +---------------+ */ - /* | A B C D | E F G H */ - /* +-------+-------+ */ - /* | */ - /* XRa */ - /* */ - - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); - } - break; - case MXU_OPTN3_PTN1: - { - /* */ - /* XRb XRc */ - /* +-------------------+ */ - /* A | B C D E | F G H */ - /* +---------+---------+ */ - /* | */ - /* XRa */ - /* */ - - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF); - tcg_gen_shli_i32(t0, t0, 8); - - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); - tcg_gen_shri_i32(t1, t1, 24); - - tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } - break; - case MXU_OPTN3_PTN2: - { - /* */ - /* XRb XRc */ - /* +-------------------+ */ - /* A B | C D E F | G H */ - /* +---------+---------+ */ - /* | */ - /* XRa */ - /* */ - - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); - tcg_gen_shli_i32(t0, t0, 16); - - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); - tcg_gen_shri_i32(t1, t1, 16); - - tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } - break; - case MXU_OPTN3_PTN3: - { - /* */ - /* XRb XRc */ - /* +-------------------+ */ - /* A B C | D E F G | H */ - /* +---------+---------+ */ - /* | */ - /* XRa */ - /* */ - - TCGv_i32 t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new(); - - tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF); - tcg_gen_shli_i32(t0, t0, 24); - - tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFFFF00); - tcg_gen_shri_i32(t1, t1, 8); - - tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); - } - break; - case MXU_OPTN3_PTN4: - { - /* */ - /* XRb XRc */ - /* +---------------+ */ - /* A B C D | E F G H | */ - /* +-------+-------+ */ - /* | */ - /* XRa */ - /* */ - - tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); - } - break; - } - } -} - - -/* - * Decoding engine for MXU - * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - */ - -static void decode_opc_mxu__pool00(DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_S32MAX: - case OPC_MXU_S32MIN: - gen_mxu_S32MAX_S32MIN(ctx); - break; - case OPC_MXU_D16MAX: - case OPC_MXU_D16MIN: - gen_mxu_D16MAX_D16MIN(ctx); - break; - case OPC_MXU_Q8MAX: - case OPC_MXU_Q8MIN: - gen_mxu_Q8MAX_Q8MIN(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_opc_mxu__pool04(DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 20, 1); - - switch (opcode) { - case OPC_MXU_S32LDD: - case OPC_MXU_S32LDDR: - gen_mxu_s32ldd_s32lddr(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_opc_mxu__pool16(DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 18, 3); - - switch (opcode) { - case OPC_MXU_S32ALNI: - gen_mxu_S32ALNI(ctx); - break; - case OPC_MXU_S32NOR: - gen_mxu_S32NOR(ctx); - break; - case OPC_MXU_S32AND: - gen_mxu_S32AND(ctx); - break; - case OPC_MXU_S32OR: - gen_mxu_S32OR(ctx); - break; - case OPC_MXU_S32XOR: - gen_mxu_S32XOR(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_opc_mxu__pool19(DisasContext *ctx) -{ - uint32_t opcode =3D extract32(ctx->opcode, 22, 2); - - switch (opcode) { - case OPC_MXU_Q8MUL: - case OPC_MXU_Q8MULSU: - gen_mxu_q8mul_q8mulsu(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - break; - } -} - -bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) -{ - uint32_t opcode =3D extract32(insn, 0, 6); - - if (opcode =3D=3D OPC_MXU_S32M2I) { - gen_mxu_s32m2i(ctx); - return true; - } - - if (opcode =3D=3D OPC_MXU_S32I2M) { - gen_mxu_s32i2m(ctx); - return true; - } - - { - TCGv t_mxu_cr =3D tcg_temp_new(); - TCGLabel *l_exit =3D gen_new_label(); - - gen_load_mxu_cr(t_mxu_cr); - tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN); - tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit); - - switch (opcode) { - case OPC_MXU__POOL00: - decode_opc_mxu__pool00(ctx); - break; - case OPC_MXU_D16MUL: - gen_mxu_d16mul(ctx); - break; - case OPC_MXU_D16MAC: - gen_mxu_d16mac(ctx); - break; - case OPC_MXU__POOL04: - decode_opc_mxu__pool04(ctx); - break; - case OPC_MXU_S8LDD: - gen_mxu_s8ldd(ctx); - break; - case OPC_MXU__POOL16: - decode_opc_mxu__pool16(ctx); - break; - case OPC_MXU__POOL19: - decode_opc_mxu__pool19(ctx); - break; - default: - MIPS_INVAL("decode_opc_mxu"); - gen_reserved_instruction(ctx); - } - - gen_set_label(l_exit); - tcg_temp_free(t_mxu_cr); - } - - return true; -} - -#else /* !defined(TARGET_MIPS64) */ - -bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) -{ - return false; -} - -#endif /* defined(TARGET_MIPS64) */ - /* * Main MXU decoding function */ diff --git a/target/mips/meson.build b/target/mips/meson.build index 9741545440c..a909da46063 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -17,6 +17,7 @@ 'lmmi_helper.c', 'msa_helper.c', 'msa_translate.c', + 'mxu_translate.c', 'op_helper.c', 'rel6_translate.c', 'tlb_helper.c', --=20 2.26.2