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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id w11sm3812320wru.3.2021.02.21.14.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Feb 2021 14:26:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wqm+61I+iUlDlEUVidXloBrgjcCcgJbWQO+9DBAAkf4=; b=RAIjvf6wj+GQMkzFFydJunuuKoF1dUACoCW0rsZ2oiknkKsAmavP66SHxIHHmddtUN HtIcA45ZH9tNX4EwVIgypQeT/ysHExVB0pli3izJ/SwU2/NPLp+YDwg5G7Ah5FGTI7e1 biqHdvNnzzOTUoqusvZANBRmzVolA/XKcz8Ur3u0kovyKrKK57mQ2TJvm6GZUJlcU49f 3QDBznyHim5sJeheg5C0ptatUTLOwNYQJqVfZOT8FdV+fnhfTHrjPcI+nptETstjmKNZ EMhODDPmbuBLvIDwqc8raEkdk8kNwXLhBnl+An8KY6KG+9zeZLKFYfy4kp2UH1M0jsJk 5MKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wqm+61I+iUlDlEUVidXloBrgjcCcgJbWQO+9DBAAkf4=; b=Fy+XKC6Hu7Paz0sdynZ1fychS4uUj7tJ+f/CX9qjxW5WpW6sabDxpugvC+WGTYg/aO 2NwZwmO2ng9I3qY9TWitHB2NYPudZZoyYwdbWPLoLi1iD2nc6SUU+44TDqNNhGSLNRJn Tv8Hjf8Nqgtj5Fc2BeSoQPSV9iurG+LKY/AagtMihtsyErW6Jq4EEkM+ZCObgxfvOpZo AD6lqfevUx5+ZEG96I09Civ9oO6Z7a88ZJng/UhTzP/UCKoIRm//ffMqy28M4/+mctDl SqvShlrlln7PuzB9TqvMpltooY8H0Vn/JEO6M4dJEei9o+FNYlDhNaMik2hgQmNb4btM 1wog== X-Gm-Message-State: AOAM530yOEuRpjFyeIurjLQ37Tta5jEmLWgDRJlrd/75ATeQQ/xQ+owp +Apba0zMLO/djqPI/kFr/ZJx4j1ElhI= X-Google-Smtp-Source: ABdhPJx8ABak7m6CJYMGXiqTDglaJuJsY6W/huvmHyDqakXDQy8CQA80xfe8hYZAOTEopynQRfVYKA== X-Received: by 2002:a1c:7204:: with SMTP id n4mr471586wmc.87.1613946384636; Sun, 21 Feb 2021 14:26:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG Date: Sun, 21 Feb 2021 23:26:15 +0100 Message-Id: <20210221222617.2579610-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210221222617.2579610-1-f4bug@amsat.org> References: <20210221222617.2579610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) IDAU is specific to M-profile. KVM only supports A-profile. Restrict this interface to TCG, as it is pointless (and confusing) on a KVM-only build. Reviewed-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 7 ------- target/arm/cpu_tcg.c | 8 ++++++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b8bc89e71fc..a772fd4926f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2380,12 +2380,6 @@ static const TypeInfo arm_cpu_type_info =3D { .class_init =3D arm_cpu_class_init, }; =20 -static const TypeInfo idau_interface_type_info =3D { - .name =3D TYPE_IDAU_INTERFACE, - .parent =3D TYPE_INTERFACE, - .class_size =3D sizeof(IDAUInterfaceClass), -}; - static void arm_cpu_register_types(void) { const size_t cpu_count =3D ARRAY_SIZE(arm_cpus); @@ -2399,7 +2393,6 @@ static void arm_cpu_register_types(void) if (cpu_count) { size_t i; =20 - type_register_static(&idau_interface_type_info); for (i =3D 0; i < cpu_count; ++i) { arm_cpu_register(&arm_cpus[i]); } diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index c29b434c60d..fb07a336939 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -14,6 +14,7 @@ #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ #include "internals.h" +#include "target/arm/idau.h" =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -739,10 +740,17 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, }; =20 +static const TypeInfo idau_interface_type_info =3D { + .name =3D TYPE_IDAU_INTERFACE, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(IDAUInterfaceClass), +}; + static void arm_tcg_cpu_register_types(void) { size_t i; =20 + type_register_static(&idau_interface_type_info); for (i =3D 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { arm_cpu_register(&arm_tcg_cpus[i]); } --=20 2.26.2 From nobody Mon Feb 9 14:15:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f50.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613946391; cv=none; d=zohomail.com; s=zohoarc; b=LEv7kAAt/pJZjrIEaR1hS7dlO7bSh2J/A8FLoGxYTQ7MYLQOPW/pLEf/cT0QEDwoAiS4ZN3DkvciB/DWB/+OgFdkiOVlP/wNI7ZgEQPsrJ8oN+mD+g0eqZVmGNAs7gOTkQFn4i38vgOSRFnYIPlBZQ6AQAKxPfM7cWgK75adQAk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613946391; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cEXLvbn+xOMhhi0R83S9d9mv5EMrvbKx+ABzbeLQvl8=; b=DK3iZ7Np7FG/VpzX0qbA9B3AFYw0e1Bt7k8G0K5UvavG+WtgBekv3nM3wP03ywkaxtXeegpvX6Jm9MT4dKDiBesBnPURkdKT2CQWhIhBY7XIPN2IPXHiS/SQpLzOfWIeell/COXUk9L8T/hUiwUDnR9z5Y3J+dx0Hq6odRzmRrQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mx.zohomail.com with SMTPS id 1613946391319624.5528855194342; Sun, 21 Feb 2021 14:26:31 -0800 (PST) Received: by mail-wr1-f50.google.com with SMTP id l12so17129735wry.2 for ; Sun, 21 Feb 2021 14:26:30 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 2sm26365710wre.24.2021.02.21.14.26.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Feb 2021 14:26:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cEXLvbn+xOMhhi0R83S9d9mv5EMrvbKx+ABzbeLQvl8=; b=eSeWjLq+KyscXQ8Th017uO4fqnLfNOGj1jhqKRVZxvfslt9thLpQkdj9gAz+gV2uYS nAzrsd/of2lfj/e306RaaqsmhFbkmtn5nYZ4OMbIw9fSH+FsUQWxcjwuOCKQSIEw+62h WrBmGC2d+XhMJFjVON9XQ75qnFI1z/FDhohCB/oeFAE0X0iPr1eFlrJs/oPE9mgiSsW/ b7ka2h/tvLYtlAONyw39pLSczlMC2qQLmxZYmKFrvqo26d7d7HXkMhd2g1IVmJdNOBDU UeWIZO37PZX/7Vvf6IVzHgpHkvhxiIU+MvHF2REGm9c1fktS4H1iE54/40XLfJAMLqVZ pLEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cEXLvbn+xOMhhi0R83S9d9mv5EMrvbKx+ABzbeLQvl8=; b=qnPKzl0RVwVn2kMeJ2iQNjKPdk9IJi5hxcEa0XpWfLsAf3LezNcl7OLXOEuY9C4kCG uZC6zEnh77Mtqs6Z6/si3l2gIEgwKGfu9ws4LXL76VryKk3FHFNBLk5qzXI8aPnVEXsW pv+qyWDuXcg1W4tGd/Guf309AI25p6GJu3isizPwFwhwwydBnbk8Hk/gNM6XkOVCTGZ/ BoHIhkBHrEG8xcMjwDzD4QyfR+gnmaGfJ3x1mkOa6AdJuGXADcrK1FbpNOzldxeV2IpY k45avAyat4IQyJRD/Yn3ZMn5B34imtRwgpIzyn3Wc5gwbbLaXD+l20iAonthxap/ecNi T74A== X-Gm-Message-State: AOAM531JmE7QKzTuZPTDgAWjQT+uhF4D0OnnsPKKqPC8ez45WNocx5vD 3zjHqAqYSBcZlVjmPxdm+DdfXKwq48A= X-Google-Smtp-Source: ABdhPJyOMrKoQte92dYJDiRgfO2901+usjlYn5za/rvDrvWS7sh459Depdk1zlTmdwirU3j52qsWLw== X-Received: by 2002:adf:f4d1:: with SMTP id h17mr696657wrp.350.1613946389648; Sun, 21 Feb 2021 14:26:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/3] target/arm/cpu: Update coding style to make checkpatch.pl happy Date: Sun, 21 Feb 2021 23:26:16 +0100 Message-Id: <20210221222617.2579610-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210221222617.2579610-1-f4bug@amsat.org> References: <20210221222617.2579610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We will move this code in the next commit. Clean it up first to avoid checkpatch.pl errors. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a772fd4926f..6865ea76466 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1972,7 +1972,8 @@ static void cortex_a8_initfn(Object *obj) } =20 static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { - /* power_control should be set to maximum latency. Again, + /* + * power_control should be set to maximum latency. Again, * default to 0 and set by private hook */ { .name =3D "A9_PWRCTL", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, @@ -2009,7 +2010,8 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); - /* Note that A9 supports the MP extensions even for + /* + * Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). */ @@ -2046,7 +2048,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, con= st ARMCPRegInfo *ri) { MachineState *ms =3D MACHINE(qdev_get_machine()); =20 - /* Linux wants the number of processors from here. + /* + * Linux wants the number of processors from here. * Might as well set the interrupt-controller bit too. */ return ((ms->smp.cpus - 1) << 24) | (1 << 23); @@ -2093,7 +2096,8 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.id_mmfr1 =3D 0x40000000; cpu->isar.id_mmfr2 =3D 0x01240000; cpu->isar.id_mmfr3 =3D 0x02102211; - /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ cpu->isar.id_isar0 =3D 0x02101110; --=20 2.26.2 From nobody Mon Feb 9 14:15:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613946396; cv=none; d=zohomail.com; s=zohoarc; b=cH73RPLAx/AfmSXRNlFVGvFuTDOybcVo4GA7zDfnvUZ6yo9haM+5IJq7zTV1mVyesmigT0evkwh4c722ei7rXLBiJarUcf22vdL/Cr8iqliyJKKPUFAMgCTnt+6VO/t9nPtlAsdcqEOkv7RgFoYGIa3uPbaeY6V4cNVTQdLHDBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613946396; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=abvYlgbxp+qnt7oGypu6kSIUTyAzh4XUcm0yaEcwfBM=; b=WvEh7swjrf2JifSuYQpY98DKgzazYcvPGoDeM8qoKrP7M8cGlM9pvIhuc5N3jt1bZwfTGEgaWhpQ/iSWkEoEldoFJiCtWCFGrSLxVvz5h+Dkw8fVj3HrVz6oLhnY8PYxCA5Snncdzj5vYngVztju8TqIu1R4EZk+XVm6vq9/x4A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.zohomail.com with SMTPS id 1613946396585683.4703960396552; Sun, 21 Feb 2021 14:26:36 -0800 (PST) Received: by mail-wm1-f52.google.com with SMTP id n10so12701549wmq.0 for ; Sun, 21 Feb 2021 14:26:35 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id y12sm14379006wrm.33.2021.02.21.14.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Feb 2021 14:26:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=abvYlgbxp+qnt7oGypu6kSIUTyAzh4XUcm0yaEcwfBM=; b=Do39XBpiaCjdx4o3acLIlsdzRldWXhgMtR2yQg9FD963XM0tMo/n9Oq+CoLzHxQbXG c9QDNu05tB11IirmGU2xvKEUeIvOpK846DvRU66vZEA9FETswV/qK0Icf3VeIh5htJmY 8jfwm166sCNBuYj6tc4fTeOciLTIdv4IsLwjkANH6DYVDV7c6euxD06TpoWDeQz+iKsW Z1eR/C5+Pcr0q81ZRBkV4ACL4broZlpfmkFqFVotnahggwpAkFITBRcDH0/2EC01cXfW GrfUMG4OvMcoK2COLMDHxxKVYRZCxOeH4fD14+J93BK5spndJln+U6FfJseXEQ9MoYME Wp5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=abvYlgbxp+qnt7oGypu6kSIUTyAzh4XUcm0yaEcwfBM=; b=ibNTcQ8oAZvKZkzXs9CCu+qtLsS8rn4BL7l5/C+sUgahK8y+juF7QchANugqVjLeTA ZGbXE7560QevJEi8UeS0O5JbxQ0RlEvfhvV0poCuqrXvTDFNn5l3E+dsgoGIyuScwRDZ xV8lrNbAuu8ONvBSJ9GtOly1sX5q5xMA/5nknQdQ5N6hj/CozNpquadoCHJ5mqDO5n3N iRSxF2gsV+nD51Z1YOFvVJ6BJ4TTHJIQ/P61jtm7Q5v4n7fK0WCy5GR1ljjj+d2Sqqhz FL8raDwTeicfaAjiknZ9xbjO9YZmlJ1VeB7vIPRIbeqjj3zKF/MNg6MPpm+fEXtE+pWs i62A== X-Gm-Message-State: AOAM532j3TkdRj2FAv/8qcL19Xy2WLNLG9RoKZagzHjaXi8tZ9TC7caP /4nVKcLL+vUYX/Vz5avjRzA= X-Google-Smtp-Source: ABdhPJyHP94q30yxiCEuYjfa9h4+nYyHehwbFYqmGqDJX0e9EUZgygdcessSIchwnj+9HpcdvypoQA== X-Received: by 2002:a7b:c40c:: with SMTP id k12mr8094446wmi.66.1613946394619; Sun, 21 Feb 2021 14:26:34 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel Date: Sun, 21 Feb 2021 23:26:17 +0100 Message-Id: <20210221222617.2579610-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210221222617.2579610-1-f4bug@amsat.org> References: <20210221222617.2579610-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) KVM requires the target cpu to be at least ARMv8 architecture (support on ARMv7 has been dropped in commit 82bf7ae84ce: "target/arm: Remove KVM support for 32-bit Arm hosts"). A KVM-only build won't be able to run TCG cpus, move the v7A CPU definitions to cpu_tcg.c. Reported-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 331 ------------------------------------------- target/arm/cpu_tcg.c | 314 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 314 insertions(+), 331 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6865ea76466..ae04884408c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1922,327 +1922,6 @@ static ObjectClass *arm_cpu_class_by_name(const cha= r *cpu_model) return oc; } =20 -/* CPU models. These are not needed for the AArch64 linux-user build. */ -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - -static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { - { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2AUXCR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void cortex_a8_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a8"; - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_EL3); - cpu->midr =3D 0x410fc080; - cpu->reset_fpsid =3D 0x410330c0; - cpu->isar.mvfr0 =3D 0x11110222; - cpu->isar.mvfr1 =3D 0x00011111; - cpu->ctr =3D 0x82048004; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; - cpu->isar.id_dfr0 =3D 0x400; - cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x31100003; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01202000; - cpu->isar.id_mmfr3 =3D 0x11; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x12112111; - cpu->isar.id_isar2 =3D 0x21232031; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; - cpu->isar.dbgdidr =3D 0x15141000; - cpu->clidr =3D (1 << 27) | (2 << 24) | 3; - cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ - cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ - cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ - cpu->reset_auxcr =3D 2; - define_arm_cp_regs(cpu, cortexa8_cp_reginfo); -} - -static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { - /* - * power_control should be set to maximum latency. Again, - * default to 0 and set by private hook - */ - { .name =3D "A9_PWRCTL", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_control) }, - { .name =3D "A9_DIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D = 0, .opc2 =3D 1, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_diagnostic) }, - { .name =3D "A9_PWRDIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_diagnostic) }, - { .name =3D "NEONBUSY", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - /* TLB lockdown control */ - { .name =3D "TLB_LOCKR", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 2, - .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, - { .name =3D "TLB_LOCKW", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 4, - .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, - { .name =3D "TLB_VA", .cp =3D 15, .crn =3D 15, .crm =3D 5, .opc1 =3D 5= , .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - { .name =3D "TLB_PA", .cp =3D 15, .crn =3D 15, .crm =3D 6, .opc1 =3D 5= , .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - { .name =3D "TLB_ATTR", .cp =3D 15, .crn =3D 15, .crm =3D 7, .opc1 =3D= 5, .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - REGINFO_SENTINEL -}; - -static void cortex_a9_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a9"; - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_EL3); - /* - * Note that A9 supports the MP extensions even for - * A9UP and single-core A9MP (which are both different - * and valid configurations; we don't model A9UP). - */ - set_feature(&cpu->env, ARM_FEATURE_V7MP); - set_feature(&cpu->env, ARM_FEATURE_CBAR); - cpu->midr =3D 0x410fc090; - cpu->reset_fpsid =3D 0x41033090; - cpu->isar.mvfr0 =3D 0x11110222; - cpu->isar.mvfr1 =3D 0x01111111; - cpu->ctr =3D 0x80038003; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x1031; - cpu->isar.id_pfr1 =3D 0x11; - cpu->isar.id_dfr0 =3D 0x000; - cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x00100103; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01230000; - cpu->isar.id_mmfr3 =3D 0x00002111; - cpu->isar.id_isar0 =3D 0x00101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x00111142; - cpu->isar.dbgdidr =3D 0x35141000; - cpu->clidr =3D (1 << 27) | (1 << 24) | 3; - cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ - cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ - define_arm_cp_regs(cpu, cortexa9_cp_reginfo); -} - -#ifndef CONFIG_USER_ONLY -static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - MachineState *ms =3D MACHINE(qdev_get_machine()); - - /* - * Linux wants the number of processors from here. - * Might as well set the interrupt-controller bit too. - */ - return ((ms->smp.cpus - 1) << 24) | (1 << 23); -} -#endif - -static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, - .writefn =3D arm_cp_write_ignore, }, -#endif - { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void cortex_a7_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a7"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A7; - cpu->midr =3D 0x410fc075; - cpu->reset_fpsid =3D 0x41023075; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x11111111; - cpu->ctr =3D 0x84448003; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x02010555; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10101105; - cpu->isar.id_mmfr1 =3D 0x40000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; - /* - * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but - * table 4-41 gives 0x02101110, which includes the arm div insns. - */ - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; - cpu->isar.dbgdidr =3D 0x3515f005; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ -} - -static void cortex_a15_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a15"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; - cpu->midr =3D 0x412fc0f1; - cpu->reset_fpsid =3D 0x410430f0; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x11111111; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x02010555; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; - cpu->isar.dbgdidr =3D 0x3515f021; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); -} - -#ifndef TARGET_AARCH64 -/* - * -cpu max: a CPU with as many features enabled as our emulation supports. - * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; - * this only needs to handle 32 bits, and need not care about KVM. - */ -static void arm_max_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cortex_a15_initfn(obj); - - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - -#ifdef CONFIG_USER_ONLY - /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. - */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - } -#endif -} -#endif - -#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ - -static const ARMCPUInfo arm_cpus[] =3D { -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, - { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, - { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, - { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, -#ifndef TARGET_AARCH64 - { .name =3D "max", .initfn =3D arm_max_initfn }, -#endif -#ifdef CONFIG_USER_ONLY - { .name =3D "any", .initfn =3D arm_max_initfn }, -#endif -#endif -}; - static Property arm_cpu_properties[] =3D { DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), @@ -2386,21 +2065,11 @@ static const TypeInfo arm_cpu_type_info =3D { =20 static void arm_cpu_register_types(void) { - const size_t cpu_count =3D ARRAY_SIZE(arm_cpus); - type_register_static(&arm_cpu_type_info); =20 #ifdef CONFIG_KVM type_register_static(&host_arm_cpu_type_info); #endif - - if (cpu_count) { - size_t i; - - for (i =3D 0; i < cpu_count; ++i) { - arm_cpu_register(&arm_cpus[i]); - } - } } =20 type_init(arm_cpu_register_types) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index fb07a336939..b420c8c555c 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -15,6 +15,9 @@ #endif /* CONFIG_TCG */ #include "internals.h" #include "target/arm/idau.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/boards.h" +#endif =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -255,6 +258,236 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_auxcr =3D 1; } =20 +static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { + { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2AUXCR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void cortex_a8_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a8"; + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->midr =3D 0x410fc080; + cpu->reset_fpsid =3D 0x410330c0; + cpu->isar.mvfr0 =3D 0x11110222; + cpu->isar.mvfr1 =3D 0x00011111; + cpu->ctr =3D 0x82048004; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x1031; + cpu->isar.id_pfr1 =3D 0x11; + cpu->isar.id_dfr0 =3D 0x400; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x31100003; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01202000; + cpu->isar.id_mmfr3 =3D 0x11; + cpu->isar.id_isar0 =3D 0x00101111; + cpu->isar.id_isar1 =3D 0x12112111; + cpu->isar.id_isar2 =3D 0x21232031; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x00111142; + cpu->isar.dbgdidr =3D 0x15141000; + cpu->clidr =3D (1 << 27) | (2 << 24) | 3; + cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ + cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ + cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ + cpu->reset_auxcr =3D 2; + define_arm_cp_regs(cpu, cortexa8_cp_reginfo); +} + +static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { + /* + * power_control should be set to maximum latency. Again, + * default to 0 and set by private hook + */ + { .name =3D "A9_PWRCTL", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_control) }, + { .name =3D "A9_DIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D = 0, .opc2 =3D 1, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_diagnostic) }, + { .name =3D "A9_PWRDIAG", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_power_diagnostic) }, + { .name =3D "NEONBUSY", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + /* TLB lockdown control */ + { .name =3D "TLB_LOCKR", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 2, + .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, + { .name =3D "TLB_LOCKW", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 = =3D 5, .opc2 =3D 4, + .access =3D PL1_W, .resetvalue =3D 0, .type =3D ARM_CP_NOP }, + { .name =3D "TLB_VA", .cp =3D 15, .crn =3D 15, .crm =3D 5, .opc1 =3D 5= , .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + { .name =3D "TLB_PA", .cp =3D 15, .crn =3D 15, .crm =3D 6, .opc1 =3D 5= , .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + { .name =3D "TLB_ATTR", .cp =3D 15, .crn =3D 15, .crm =3D 7, .opc1 =3D= 5, .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, + REGINFO_SENTINEL +}; + +static void cortex_a9_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a9"; + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); + /* + * Note that A9 supports the MP extensions even for + * A9UP and single-core A9MP (which are both different + * and valid configurations; we don't model A9UP). + */ + set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_CBAR); + cpu->midr =3D 0x410fc090; + cpu->reset_fpsid =3D 0x41033090; + cpu->isar.mvfr0 =3D 0x11110222; + cpu->isar.mvfr1 =3D 0x01111111; + cpu->ctr =3D 0x80038003; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x1031; + cpu->isar.id_pfr1 =3D 0x11; + cpu->isar.id_dfr0 =3D 0x000; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x00100103; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01230000; + cpu->isar.id_mmfr3 =3D 0x00002111; + cpu->isar.id_isar0 =3D 0x00101111; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x00111142; + cpu->isar.dbgdidr =3D 0x35141000; + cpu->clidr =3D (1 << 27) | (1 << 24) | 3; + cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ + cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ + define_arm_cp_regs(cpu, cortexa9_cp_reginfo); +} + +#ifndef CONFIG_USER_ONLY +static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + /* + * Linux wants the number of processors from here. + * Might as well set the interrupt-controller bit too. + */ + return ((ms->smp.cpus - 1) << 24) | (1 << 23); +} +#endif + +static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { +#ifndef CONFIG_USER_ONLY + { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, + .writefn =3D arm_cp_write_ignore, }, +#endif + { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void cortex_a7_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a7"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A7; + cpu->midr =3D 0x410fc075; + cpu->reset_fpsid =3D 0x41023075; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x11111111; + cpu->ctr =3D 0x84448003; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x02010555; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + * table 4-41 gives 0x02101110, which includes the arm div insns. + */ + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x10011142; + cpu->isar.dbgdidr =3D 0x3515f005; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ +} + +static void cortex_a15_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a15"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; + cpu->midr =3D 0x412fc0f1; + cpu->reset_fpsid =3D 0x410430f0; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x11111111; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x02010555; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x10011142; + cpu->isar.dbgdidr =3D 0x3515f021; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); +} + static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -695,6 +928,77 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) cc->gdb_core_xml_file =3D "arm-m-profile.xml"; } =20 +#ifndef TARGET_AARCH64 +/* + * -cpu max: a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; + * this only needs to handle 32 bits, and need not care about KVM. + */ +static void arm_max_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cortex_a15_initfn(obj); + + /* old-style VFP short-vector support */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + +#ifdef CONFIG_USER_ONLY + /* + * We don't set these in system emulation mode for the moment, + * since we don't correctly set (all of) the ID registers to + * advertise them. + */ + set_feature(&cpu->env, ARM_FEATURE_V8); + { + uint32_t t; + + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + } +#endif /* CONFIG_USER_ONLY */ +} +#endif /* !TARGET_AARCH64 */ + static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "arm926", .initfn =3D arm926_initfn }, { .name =3D "arm946", .initfn =3D arm946_initfn }, @@ -708,6 +1012,10 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "arm1136", .initfn =3D arm1136_initfn }, { .name =3D "arm1176", .initfn =3D arm1176_initfn }, { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, + { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, + { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, + { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, + { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, @@ -738,6 +1046,12 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "pxa270-b1", .initfn =3D pxa270b1_initfn }, { .name =3D "pxa270-c0", .initfn =3D pxa270c0_initfn }, { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, +#ifndef TARGET_AARCH64 + { .name =3D "max", .initfn =3D arm_max_initfn }, +#endif +#ifdef CONFIG_USER_ONLY + { .name =3D "any", .initfn =3D arm_max_initfn }, +#endif }; =20 static const TypeInfo idau_interface_type_info =3D { --=20 2.26.2