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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id h20sm6417404wmb.1.2021.02.21.06.37.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Feb 2021 06:37:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2T+hpNRPaClY3K4hATCoC3PY+rExU+CseU3tyEMImpE=; b=j1uJHVkTSe8Tc+cQRNwemTeiBzyCt2LrhAk1s1+mSRGdWUxhPzxBMixOaJ8A6JTUzI +z0GQWmqs+nMC8lDJbd9usU8L789UMb7OmKNAxRZ4JwKMLsyr15j3hGHgviZ6DZBNE3P JlLMVBmE+4DWXdSCcV4N4GY00UlB/1sHtjPabCuH9cL3PiJMBKZMctpODvlkNl0D6AQk 6rZ4+F7xOfyc3ajSFXq4kdulKY5JMUt9fKfzmAqaJN3h5rLYPGlONO87MQ7dBab7Fj74 9bqL2VzfFFHCmBENaifz9QEw62Cv/th7VkHlOVqWlsdzzfl3VqhCNz+gA2jwM5jxYMwi iEWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2T+hpNRPaClY3K4hATCoC3PY+rExU+CseU3tyEMImpE=; b=Iv5n+500BXV9fEwlTQVW4PboBM7EDM08TiViGx208UwliLSyJqiTnyNI0ck9HAc9jY qnb9LBnBn6/ZJ1e8KCbjdJXoQaYMCu/OTRJbEzv5h70H6ClCa4Q353O+jm/axIaTd5Cf PHXdxZCr7jB5sBjWrd18mv1s7binOFg55LVaSuQigojP0evPSA46oD1r5BJ8yiaoHeY7 xSMScRtFS4QSc/tQTWDeMIVtCeLNQHOpE1DwzP0KH++MDudgjh5oFfhUY43RIgkLVJhb yrZInYujFlgJJ9GJdrQWxS6noVuhLnMFeJD2jEAu4W9z+9s2JfPEG8rKRmzS2XFRp6FD MeFQ== X-Gm-Message-State: AOAM5338xaJwVlMTVccvupZPlJbWaO+nTTdysd/rDO5r0ULBOCHDRDtw if8BIfeMMrYm+poknZW/qwg= X-Google-Smtp-Source: ABdhPJxTk07QfGnDVXIHuy1MPreAarCrDoQQJQ7hxQO+eqp64EwGoBhFQt/G+YZgA0kvmrExPBmShg== X-Received: by 2002:a1c:a791:: with SMTP id q139mr16144950wme.20.1613918264173; Sun, 21 Feb 2021 06:37:44 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Wainer dos Santos Moschetta , Aleksandar Rikalo , Aurelien Jarno , Marcel Apfelbaum , Cleber Rosa , "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , BALATON Zoltan Subject: [PULL 38/43] vt82c686: Move creation of ISA devices to the ISA bridge Date: Sun, 21 Feb 2021 15:34:27 +0100 Message-Id: <20210221143432.2468220-39-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210221143432.2468220-1-f4bug@amsat.org> References: <20210221143432.2468220-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: BALATON Zoltan Currently the ISA devices that are part of the VIA south bridge, superio chip are wired up by board code. Move creation of these ISA devices to the VIA ISA bridge model so that board code does not need to access ISA bus. This also allows vt82c686b-superio to be made internal to vt82c686 which allows implementing its configuration via registers in subseqent commits. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/vt82c686.c | 20 ++++++++++++++++++++ hw/mips/fuloong2e.c | 29 +++++------------------------ 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 7e5fa060f5f..a37f1931ce0 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -16,6 +16,11 @@ #include "hw/qdev-properties.h" #include "hw/isa/isa.h" #include "hw/isa/superio.h" +#include "hw/intc/i8259.h" +#include "hw/irq.h" +#include "hw/dma/i8257.h" +#include "hw/timer/i8254.h" +#include "hw/rtc/mc146818rtc.h" #include "migration/vmstate.h" #include "hw/isa/apm.h" #include "hw/acpi/acpi.h" @@ -307,9 +312,16 @@ OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686= B_ISA) =20 struct VT82C686BISAState { PCIDevice dev; + qemu_irq cpu_intr; SuperIOConfig superio_cfg; }; =20 +static void via_isa_request_i8259_irq(void *opaque, int irq, int level) +{ + VT82C686BISAState *s =3D opaque; + qemu_set_irq(s->cpu_intr, level); +} + static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) { @@ -365,10 +377,18 @@ static void vt82c686b_realize(PCIDevice *d, Error **e= rrp) VT82C686BISAState *s =3D VT82C686B_ISA(d); DeviceState *dev =3D DEVICE(d); ISABus *isa_bus; + qemu_irq *isa_irq; int i; =20 + qdev_init_gpio_out(dev, &s->cpu_intr, 1); + isa_irq =3D qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); isa_bus =3D isa_bus_new(dev, get_system_memory(), pci_address_space_io= (d), &error_fatal); + isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); + i8254_pit_init(isa_bus, 0x40, 0, NULL); + i8257_dma_init(isa_bus, 0); + isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); + mc146818_rtc_init(isa_bus, 2000, NULL); =20 for (i =3D 0; i < PCI_CONFIG_HEADER_SIZE; i++) { if (i < PCI_COMMAND || i >=3D PCI_REVISION_ID) { diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 94f4718147f..4f61f2c873b 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -25,9 +25,6 @@ #include "qapi/error.h" #include "cpu.h" #include "hw/clock.h" -#include "hw/intc/i8259.h" -#include "hw/dma/i8257.h" -#include "hw/isa/superio.h" #include "net/net.h" #include "hw/boards.h" #include "hw/i2c/smbus_eeprom.h" @@ -39,13 +36,13 @@ #include "qemu/log.h" #include "hw/loader.h" #include "hw/ide/pci.h" +#include "hw/qdev-properties.h" #include "elf.h" #include "hw/isa/vt82c686.h" -#include "hw/rtc/mc146818rtc.h" -#include "hw/timer/i8254.h" #include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" +#include "sysemu/sysemu.h" #include "qemu/error-report.h" =20 #define ENVP_PADDR 0x2000 @@ -203,26 +200,13 @@ static void main_cpu_reset(void *opaque) } =20 static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq= intc, - I2CBus **i2c_bus, ISABus **p_isa_bu= s) + I2CBus **i2c_bus) { - qemu_irq *i8259; - ISABus *isa_bus; PCIDevice *dev; =20 dev =3D pci_create_simple_multifunction(pci_bus, PCI_DEVFN(slot, 0), t= rue, TYPE_VT82C686B_ISA); - isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(dev), "isa.0")); - assert(isa_bus); - *p_isa_bus =3D isa_bus; - /* Interrupt controller */ - /* The 8259 -> IP5 */ - i8259 =3D i8259_init(isa_bus, intc); - isa_bus_irqs(isa_bus, i8259); - /* init other devices */ - i8254_pit_init(isa_bus, 0x40, 0, NULL); - i8257_dma_init(isa_bus, 0); - /* Super I/O */ - isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); + qdev_connect_gpio_out(DEVICE(dev), 0, intc); =20 dev =3D pci_create_simple(pci_bus, PCI_DEVFN(slot, 1), "via-ide"); pci_ide_create_devs(dev); @@ -269,7 +253,6 @@ static void mips_fuloong2e_init(MachineState *machine) uint64_t kernel_entry; PCIDevice *pci_dev; PCIBus *pci_bus; - ISABus *isa_bus; I2CBus *smbus; Clock *cpuclk; MIPSCPU *cpu; @@ -336,7 +319,7 @@ static void mips_fuloong2e_init(MachineState *machine) =20 /* South bridge -> IP5 */ vt82c686b_southbridge_init(pci_bus, FULOONG2E_VIA_SLOT, env->irq[5], - &smbus, &isa_bus); + &smbus); =20 /* GPU */ if (vga_interface_type !=3D VGA_NONE) { @@ -351,8 +334,6 @@ static void mips_fuloong2e_init(MachineState *machine) spd_data =3D spd_data_generate(DDR, machine->ram_size); smbus_eeprom_init_one(smbus, 0x50, spd_data); =20 - mc146818_rtc_init(isa_bus, 2000, NULL); - /* Network card: RTL8139D */ network_init(pci_bus); } --=20 2.26.2