From nobody Tue Feb 10 11:16:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) client-ip=209.85.128.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613918195; cv=none; d=zohomail.com; s=zohoarc; b=M7uFyqa5VilcrDGqq0N7W3oVpmKzO8aGvoSPnIgqbGHt1qF4lcZwlJOXg56NzASFChZyMBlscyyWaK/gvX5TLWsPruit99VPtv8vC+LYRldPncVwBYORGFBFn8FUz0PF76EdaXMa5pcgZZ3tCpH6Da49g0ra3OfN8/VT8StbGZs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613918195; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rOF5MQDxPLOXQx0ibeRXNei5jJwKer3lL4/zvBaW5Vo=; b=jse05014Jea4djWs1OQo7SZS1rzDuT4nRWmOjPbNCqciCvCdBjKojDpKeL8Qu86MmDQK3WovJc/dGlhacSRHAKHTGl0HlSZ1IjAg+A8sPX48NdPITtNHWW7oeq0cfnhEY0BV/Kd3+Ymzz2hwYKlcyAf004UVvXBqO9xa7hb1GGA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by mx.zohomail.com with SMTPS id 161391819532833.76730161108958; Sun, 21 Feb 2021 06:36:35 -0800 (PST) Received: by mail-wm1-f53.google.com with SMTP id m25so2580168wmi.3 for ; Sun, 21 Feb 2021 06:36:34 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id t2sm8283842wrx.23.2021.02.21.06.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Feb 2021 06:36:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rOF5MQDxPLOXQx0ibeRXNei5jJwKer3lL4/zvBaW5Vo=; b=Q1qWELqS7EuSV2vdbdH29F6ehgYhPKKzxcZP65ymUWpGYNJkYBD748SQwqGtEa7iNk dzSgATeHxwGwopK0VhAX+0p8A1ExJcl0K7LlzFM1/bZeHWuuFRyLynVzXshztBnJMhVX JH4F6UD6UfK2YHnED7nMJKiAxK4sYEuIXUlR9/TlmUxb3WGrVOhvMbMJZhaPAZ3lKQLN YQtOLGy/YRvQTGzXdsqU/0Th7SBzVjHL0faiiOx3X7gsPZJJVPFiH9znun86CRoxiduS WI+yq2/7S5M+CxedB62fprLLEVGcajJEWhTIbw8csDjryFA+4L5larpDr7lpNsbXMbTQ n9dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rOF5MQDxPLOXQx0ibeRXNei5jJwKer3lL4/zvBaW5Vo=; b=moIRSXO7RLmEc27TJua66cJ2ByZh6rAfo09Jeam89mxMpBucQJBmvoOcdzAMWEp+0E qqHZfOiaB6YZ0q1aVdCUjHJxkxNTwrt4hLHQXkuJwBUomHRT7sXhGsPWg/zirj86vohg YF68Wdmdfpub2q2mzb8+fWo4BZcxWgD08uB385RUVR/NZ1PJ7PXzDloYODFJx0wmmDC3 Hdlp1175lyMcbjjs1g8DPM9N4jYeVsLVp6ruT9sJ0ZaCRQE6x1TQHa0/+zHbZdnyrOqg IIXaicoMWnqNu5yaKX44wRJinIduYsVlX31uGfssgM0C4OtwVO5SmhhZmPUv901icGwM RQPQ== X-Gm-Message-State: AOAM530HaUPViochcsMZtlJUQSQfgRT9iImKnDwDMB2Y6JMuWAJO1xa3 n9vVp0fl7H+9Rp/WUkBP6Xc= X-Google-Smtp-Source: ABdhPJwF0+ZRc92TM7zriN+Khz8uWxvUscOcRar7pRTnuJxgiOgfTBx2KSdYbyQxe8CvOEpbStT3gw== X-Received: by 2002:a1c:7705:: with SMTP id t5mr9808915wmi.148.1613918193527; Sun, 21 Feb 2021 06:36:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paul Burton , Wainer dos Santos Moschetta , Aleksandar Rikalo , Aurelien Jarno , Marcel Apfelbaum , Cleber Rosa , "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Richard Henderson Subject: [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones Date: Sun, 21 Feb 2021 15:34:13 +0100 Message-Id: <20210221143432.2468220-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210221143432.2468220-1-f4bug@amsat.org> References: <20210221143432.2468220-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The cpu::mmr[] array contains the upper halves of 128-bit GPR registers. While they are only used by the R5900 CPU, the concept is generic and could be used by another MIPS implementation. Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global. When the code is similar to the GPR lower halves, move it close by. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20210214175912.732946-5-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 10 ++++++--- target/mips/translate.h | 3 +++ target/mips/translate.c | 48 ++++++++++++++++++++--------------------- 3 files changed, 34 insertions(+), 27 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9e6028f8e63..075c24abdad 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -460,6 +460,13 @@ typedef struct mips_def_t mips_def_t; typedef struct TCState TCState; struct TCState { target_ulong gpr[32]; +#if defined(TARGET_MIPS64) + /* + * For CPUs using 128-bit GPR registers, we put the lower halves in gp= r[]) + * and the upper halves in gpr_hi[]. + */ + uint64_t gpr_hi[32]; +#endif /* TARGET_MIPS64 */ target_ulong PC; target_ulong HI[MIPS_DSP_ACC]; target_ulong LO[MIPS_DSP_ACC]; @@ -505,9 +512,6 @@ struct TCState { =20 float_status msa_fp_status; =20 - /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs= */ - uint64_t mmr[32]; - #define NUMBER_OF_MXU_REGISTERS 16 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; target_ulong mxu_cr; diff --git a/target/mips/translate.h b/target/mips/translate.h index 2a1d8f570bb..3014c20cadb 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -145,6 +145,9 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs,= int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); =20 extern TCGv cpu_gpr[32], cpu_PC; +#if defined(TARGET_MIPS64) +extern TCGv_i64 cpu_gpr_hi[32]; +#endif extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; diff --git a/target/mips/translate.c b/target/mips/translate.c index c20f630b7e7..2df76592470 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2179,6 +2179,11 @@ enum { =20 /* global register indices */ TCGv cpu_gpr[32], cpu_PC; +/* + * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gp= r[]) + * and the upper halves in cpu_gpr_hi[]. + */ +TCGv_i64 cpu_gpr_hi[32]; TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget; TCGv bcond; @@ -2187,11 +2192,6 @@ static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; TCGv_i64 fpu_f64[32]; =20 -#if defined(TARGET_MIPS64) -/* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) = */ -static TCGv_i64 cpu_mmr[32]; -#endif - #if !defined(TARGET_MIPS64) /* MXU registers */ static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; @@ -24784,7 +24784,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx) /* nop */ } else if (rt =3D=3D 0) { tcg_gen_movi_i64(cpu_gpr[rd], 0); - tcg_gen_movi_i64(cpu_mmr[rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); } else { TCGv_i64 t0 =3D tcg_temp_new(); TCGv_i64 t1 =3D tcg_temp_new(); @@ -24802,7 +24802,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx) =20 tcg_gen_mov_i64(cpu_gpr[rd], t1); =20 - tcg_gen_andi_i64(t0, cpu_mmr[rt], mask); + tcg_gen_andi_i64(t0, cpu_gpr_hi[rt], mask); tcg_gen_movi_i64(t1, 0); tcg_gen_or_i64(t1, t0, t1); tcg_gen_shli_i64(t0, t0, 16); @@ -24812,7 +24812,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx) tcg_gen_shli_i64(t0, t0, 16); tcg_gen_or_i64(t1, t0, t1); =20 - tcg_gen_mov_i64(cpu_mmr[rd], t1); + tcg_gen_mov_i64(cpu_gpr_hi[rd], t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); @@ -24844,9 +24844,9 @@ static void gen_mmi_pcpyld(DisasContext *ctx) /* nop */ } else { if (rs =3D=3D 0) { - tcg_gen_movi_i64(cpu_mmr[rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); } else { - tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]); + tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]); } if (rt =3D=3D 0) { tcg_gen_movi_i64(cpu_gpr[rd], 0); @@ -24885,13 +24885,13 @@ static void gen_mmi_pcpyud(DisasContext *ctx) if (rs =3D=3D 0) { tcg_gen_movi_i64(cpu_gpr[rd], 0); } else { - tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]); + tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr_hi[rs]); } if (rt =3D=3D 0) { - tcg_gen_movi_i64(cpu_mmr[rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); } else { if (rd !=3D rt) { - tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]); + tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]); } } } @@ -29285,6 +29285,16 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); +#if defined(TARGET_MIPS64) + cpu_gpr_hi[0] =3D NULL; + + for (unsigned i =3D 1; i < 32; i++) { + cpu_gpr_hi[i] =3D tcg_global_mem_new_i64(cpu_env, + offsetof(CPUMIPSState, + active_tc.gpr_hi[i= ]), + regnames[i]); + } +#endif /* !TARGET_MIPS64 */ for (i =3D 0; i < 32; i++) { int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); =20 @@ -29323,16 +29333,6 @@ void mips_tcg_init(void) cpu_llval =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval= ), "llval"); =20 -#if defined(TARGET_MIPS64) - cpu_mmr[0] =3D NULL; - for (i =3D 1; i < 32; i++) { - cpu_mmr[i] =3D tcg_global_mem_new_i64(cpu_env, - offsetof(CPUMIPSState, - active_tc.mmr[i]), - regnames[i]); - } -#endif - #if !defined(TARGET_MIPS64) for (i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, @@ -29344,7 +29344,7 @@ void mips_tcg_init(void) mxu_CR =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.mxu_cr), mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); -#endif +#endif /* !TARGET_MIPS64 */ } =20 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, --=20 2.26.2