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[24.113.145.216]) by smtp.gmail.com with ESMTPSA id h186sm9726559pgc.38.2021.02.20.13.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Feb 2021 13:29:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YZlcIqbge5shBdwBo+gxH2PmfFRPNLK7+lY86kmx9Oc=; b=X9rwrJvvpLPkPiHsw2/TBcuTLcGc/066IQckwwr2PODBMSZtSGwNJXrMRwiMF6Csow nEytwxwYPmpxa6CRE5SLUzEZeAxYd8bRUfp6AC6ZRGTTEp2WvrteCbb+ScpyPTx4mBwD jccd2UD9TVbZOqNniTr29cVlBIC+xVqXN8iyvpNtcFHaPUuqbAJW6w3wp3fzkWwJCTjy p+9wCZ18PeV8AWP5MW1pjhosYW8UA+ey1pF1vfBfjLpTuRK9eWAiZC+PONhPKn3wA3bX 8Bc1FPyUCYQD1r/S1r+kSpAPQSQYrWuVzEGejxovl+rumT9ipp3oFBU83IZUln79HUUM +qmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YZlcIqbge5shBdwBo+gxH2PmfFRPNLK7+lY86kmx9Oc=; b=tYba6gKFCpxXIKJ/EYdNuKadQIZHNz0AayM9LOWEYSeizFJASI8XyKrRc0RMEKW0Cf ei3kzi8GbJ7Ba/yJc7DrbD498BjIC9Q/FnRHuu6nU9kEtDEgpjFqBszLf1OFV9Ui8eD+ du19ib8keoRgTYdaE3ZX7SL4oVYnY8TeAeACXVLb5NDoAkVLLKdlrFkSOi/VkIcAleS1 RfycaGDjTmh1mKHVbPk3J1kDkMaN5epmf+Yaz9zumYTyqDHpJxZPxihgz5kQ9R64fio0 r1a3zBthU5xGKkTar0WBpVSXBQXz+HSwU7F52y0erZaJr71wcKxlj/vUBxCXS7vj/ab4 PJ/w== X-Gm-Message-State: AOAM5311lBWRhLpRnzbPiQO/hINWolCneaLgvr5mLELSLza1hOrGLIWf tHnxYzwyF18vBZ06isEnaJotU8DA/sqB9Q== X-Google-Smtp-Source: ABdhPJzwjzlZj0xXx0GmDXSgpUG3wFVii5Q7ICDjw1vKUn2fNgqPz+x9xNSLI4rne4OUCwT9ppOElw== X-Received: by 2002:a17:902:e551:b029:de:8dba:84a3 with SMTP id n17-20020a170902e551b02900de8dba84a3mr15059086plf.8.1613856545848; Sat, 20 Feb 2021 13:29:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/2] tcg/aarch64: Fix I3617_CMLE0 Date: Sat, 20 Feb 2021 13:29:02 -0800 Message-Id: <20210220212903.20944-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210220212903.20944-1-richard.henderson@linaro.org> References: <20210220212903.20944-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Fix a typo in the encodeing of the cmle (zero) instruction. Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson Tested-by: Stefan Weil --- tcg/aarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 1376cdc404..903ab97473 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -561,7 +561,7 @@ typedef enum { I3617_CMEQ0 =3D 0x0e209800, I3617_CMLT0 =3D 0x0e20a800, I3617_CMGE0 =3D 0x2e208800, - I3617_CMLE0 =3D 0x2e20a800, + I3617_CMLE0 =3D 0x2e209800, I3617_NOT =3D 0x2e205800, I3617_ABS =3D 0x0e20b800, I3617_NEG =3D 0x2e20b800, --=20 2.25.1 From nobody Mon May 13 05:00:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1613856839; cv=none; d=zohomail.com; s=zohoarc; b=E+ompcMsdVCl47ng72MBef0XZGpBch2uJfwfv0Nnbuz5NxCMe84DHHZgMeUWAnpqChLq423cAdCafS9tBBwDxPH4oSGl0uuzwMgFXXemPBSsb6LBi8fSk2CPla6nVxJ7vIKxVZXFdB/B/FypFcUcwDkE8muA1xtuBg+JPVkus4w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613856839; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aAxX9e1iUwj7TwOAad2hIzBCk1BvDRE9+2RWFovj+gI=; b=lyGpjqssOwNDwUBeiqRmu8+HhHfb6JMQfWiwV4STlr7u/CvWAg48efbuY5V9FS7fyhdj86UMT9a+WUPQ6sPg1ubd+xGnloYfLRD4TwjwWRFKoTgbGwVrMurnob0Ddku/W2/CurATJhYgkZw3hmqXC/khtClC0d2PhMMWCbd6ltI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613856839350157.19542785371857; Sat, 20 Feb 2021 13:33:59 -0800 (PST) Received: from localhost ([::1]:46016 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lDZt0-0004mg-8P for importer@patchew.org; Sat, 20 Feb 2021 16:33:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lDZoM-000147-Lk for qemu-devel@nongnu.org; Sat, 20 Feb 2021 16:29:10 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:36872) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lDZoK-0003nr-CR for qemu-devel@nongnu.org; Sat, 20 Feb 2021 16:29:10 -0500 Received: by mail-pf1-x429.google.com with SMTP id b145so4198723pfb.4 for ; Sat, 20 Feb 2021 13:29:07 -0800 (PST) Received: from localhost.localdomain (24-113-145-216.wavecable.com. [24.113.145.216]) by smtp.gmail.com with ESMTPSA id h186sm9726559pgc.38.2021.02.20.13.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 Feb 2021 13:29:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aAxX9e1iUwj7TwOAad2hIzBCk1BvDRE9+2RWFovj+gI=; b=l2wfZSdSOMzA0UIYelqhi3PBVlK9dQyKvlWkG74gFub2h7ejRlmweCZlOaYzfm/zH0 /38q/9qvgV0FDWnpeuSkB+PaZZ/V0GgHLgDpbmGC0YUMcSOvx69/faspFNPSbFYLiprW pJUwBUKRE6h0h+vZGpVGoQc0sr2ixzwwrXkQn0ZlLVEFx0IQKmVCFG6SfBXbEnFkjR1a uNVy4BHofoNqaxK7rEWNA+AzBs4pL6CJ5F2S3dfs+jzUcmaOaPptLI/extMySP8WDPkZ CdirpKsu86qRlEVXXzX0sMv/TX+3liuzDmFVI32v3ci7ZFyjvfY34C6D2o1WJVLYkmvG ZpLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aAxX9e1iUwj7TwOAad2hIzBCk1BvDRE9+2RWFovj+gI=; b=R01/SA/korNApGu9vQU4oAu6rtBRw8myS0dYddmbbit/buOVzyaEc1udc/ZItU4vFH k7d3Gdap1n5iUcRqdG5vu9VA9YtgzO/EePyuSSh5ESBCQgQwUgsSnV/KJaMfHo7apN54 Y+K6aOZq7qwX+yu7esojTQVpOMG2fHrLqm/GoerZ9OJ9PmjcJHxVzvadIHjVUEb51jj7 Zn+DDfzuXa2UOv03sWg96b8o/NSQ1nOqfh701mklN0RqnBGUQX9gBzwebytAiO0CtwEs JZX6LCLBeLUlRrPhYYOg86epppqtZGe+dDvWzF01BNbpiISG1PmitMMxxVO9ZTV9TJeY 6mJQ== X-Gm-Message-State: AOAM5304K8s2pDVw/Tr7LGq4atwVZejN6O6WWjrptInS8Pts7EYps5xX cbd8Kd+oWBg9w+Chh+aYG51sisfZu3JVmw== X-Google-Smtp-Source: ABdhPJw71NfhPDmVIAC5aEKg9AjJwcrr42OmMrV4X7LcdiL3iF59MYTuPJLx/wyhQ+ruAk3ZxPgFow== X-Received: by 2002:a63:a54e:: with SMTP id r14mr12676060pgu.380.1613856546860; Sat, 20 Feb 2021 13:29:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/2] tcg/aarch64: Fix generation of "scalar" vector operations Date: Sat, 20 Feb 2021 13:29:03 -0800 Message-Id: <20210220212903.20944-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210220212903.20944-1-richard.henderson@linaro.org> References: <20210220212903.20944-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For some vector operations, "1D" is not a valid type, and there are separate instructions for the 64-bit scalar operation. Buglink: https://bugs.launchpad.net/qemu/+bug/1916112 Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson Tested-by: Stefan Weil --- tcg/aarch64/tcg-target.c.inc | 211 ++++++++++++++++++++++++++++++----- 1 file changed, 181 insertions(+), 30 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 903ab97473..3ddc0f6864 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -519,6 +519,39 @@ typedef enum { I3606_BIC =3D 0x2f001400, I3606_ORR =3D 0x0f001400, =20 + /* AdvSIMD scalar shift by immediate */ + I3609_SSHR =3D 0x5f000400, + I3609_SSRA =3D 0x5f001400, + I3609_SHL =3D 0x5f005400, + I3609_USHR =3D 0x7f000400, + I3609_USRA =3D 0x7f001400, + I3609_SLI =3D 0x7f005400, + + /* AdvSIMD scalar three same */ + I3611_SQADD =3D 0x5e200c00, + I3611_SQSUB =3D 0x5e202c00, + I3611_CMGT =3D 0x5e203400, + I3611_CMGE =3D 0x5e203c00, + I3611_SSHL =3D 0x5e204400, + I3611_ADD =3D 0x5e208400, + I3611_CMTST =3D 0x5e208c00, + I3611_UQADD =3D 0x7e200c00, + I3611_UQSUB =3D 0x7e202c00, + I3611_CMHI =3D 0x7e203400, + I3611_CMHS =3D 0x7e203c00, + I3611_USHL =3D 0x7e204400, + I3611_SUB =3D 0x7e208400, + I3611_CMEQ =3D 0x7e208c00, + + /* AdvSIMD scalar two-reg misc */ + I3612_CMGT0 =3D 0x5e208800, + I3612_CMEQ0 =3D 0x5e209800, + I3612_CMLT0 =3D 0x5e20a800, + I3612_ABS =3D 0x5e20b800, + I3612_CMGE0 =3D 0x7e208800, + I3612_CMLE0 =3D 0x7e209800, + I3612_NEG =3D 0x7e20b800, + /* AdvSIMD shift by immediate */ I3614_SSHR =3D 0x0f000400, I3614_SSRA =3D 0x0f001400, @@ -735,6 +768,25 @@ static void tcg_out_insn_3606(TCGContext *s, AArch64In= sn insn, bool q, | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5); } =20 +static void tcg_out_insn_3609(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg rn, unsigned immhb) +{ + tcg_out32(s, insn | immhb << 16 | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3611(TCGContext *s, AArch64Insn insn, + unsigned size, TCGReg rd, TCGReg rn, TCGReg = rm) +{ + tcg_out32(s, insn | (size << 22) | (rm & 0x1f) << 16 + | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3612(TCGContext *s, AArch64Insn insn, + unsigned size, TCGReg rd, TCGReg rn) +{ + tcg_out32(s, insn | (size << 22) | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q, TCGReg rd, TCGReg rn, unsigned immhb) { @@ -2234,23 +2286,38 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args) { - static const AArch64Insn cmp_insn[16] =3D { + static const AArch64Insn cmp_vec_insn[16] =3D { [TCG_COND_EQ] =3D I3616_CMEQ, [TCG_COND_GT] =3D I3616_CMGT, [TCG_COND_GE] =3D I3616_CMGE, [TCG_COND_GTU] =3D I3616_CMHI, [TCG_COND_GEU] =3D I3616_CMHS, }; - static const AArch64Insn cmp0_insn[16] =3D { + static const AArch64Insn cmp_scalar_insn[16] =3D { + [TCG_COND_EQ] =3D I3611_CMEQ, + [TCG_COND_GT] =3D I3611_CMGT, + [TCG_COND_GE] =3D I3611_CMGE, + [TCG_COND_GTU] =3D I3611_CMHI, + [TCG_COND_GEU] =3D I3611_CMHS, + }; + static const AArch64Insn cmp0_vec_insn[16] =3D { [TCG_COND_EQ] =3D I3617_CMEQ0, [TCG_COND_GT] =3D I3617_CMGT0, [TCG_COND_GE] =3D I3617_CMGE0, [TCG_COND_LT] =3D I3617_CMLT0, [TCG_COND_LE] =3D I3617_CMLE0, }; + static const AArch64Insn cmp0_scalar_insn[16] =3D { + [TCG_COND_EQ] =3D I3612_CMEQ0, + [TCG_COND_GT] =3D I3612_CMGT0, + [TCG_COND_GE] =3D I3612_CMGE0, + [TCG_COND_LT] =3D I3612_CMLT0, + [TCG_COND_LE] =3D I3612_CMLE0, + }; =20 TCGType type =3D vecl + TCG_TYPE_V64; unsigned is_q =3D vecl; + bool is_scalar =3D !is_q && vece =3D=3D MO_64; TCGArg a0, a1, a2, a3; int cmode, imm8; =20 @@ -2269,19 +2336,35 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, tcg_out_dupm_vec(s, type, vece, a0, a1, a2); break; case INDEX_op_add_vec: - tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, ADD, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2); + } break; case INDEX_op_sub_vec: - tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, SUB, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2); + } break; case INDEX_op_mul_vec: tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2); break; case INDEX_op_neg_vec: - tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); + if (is_scalar) { + tcg_out_insn(s, 3612, NEG, vece, a0, a1); + } else { + tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); + } break; case INDEX_op_abs_vec: - tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); + if (is_scalar) { + tcg_out_insn(s, 3612, ABS, vece, a0, a1); + } else { + tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); + } break; case INDEX_op_and_vec: if (const_args[2]) { @@ -2335,16 +2418,32 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2); break; case INDEX_op_ssadd_vec: - tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, SQADD, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); + } break; case INDEX_op_sssub_vec: - tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, SQSUB, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2); + } break; case INDEX_op_usadd_vec: - tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, UQADD, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2); + } break; case INDEX_op_ussub_vec: - tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, UQSUB, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); + } break; case INDEX_op_smax_vec: tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2); @@ -2362,22 +2461,46 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; case INDEX_op_shli_vec: - tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); + if (is_scalar) { + tcg_out_insn(s, 3609, SHL, a0, a1, a2 + (8 << vece)); + } else { + tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); + } break; case INDEX_op_shri_vec: - tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2); + if (is_scalar) { + tcg_out_insn(s, 3609, USHR, a0, a1, (16 << vece) - a2); + } else { + tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2); + } break; case INDEX_op_sari_vec: - tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); + if (is_scalar) { + tcg_out_insn(s, 3609, SSHR, a0, a1, (16 << vece) - a2); + } else { + tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); + } break; case INDEX_op_aa64_sli_vec: - tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); + if (is_scalar) { + tcg_out_insn(s, 3609, SLI, a0, a2, args[3] + (8 << vece)); + } else { + tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)= ); + } break; case INDEX_op_shlv_vec: - tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, USHL, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); + } break; case INDEX_op_aa64_sshl_vec: - tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, SSHL, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2); + } break; case INDEX_op_cmp_vec: { @@ -2386,30 +2509,58 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode= opc, =20 if (cond =3D=3D TCG_COND_NE) { if (const_args[2]) { - tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1); + if (is_scalar) { + tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1); + } else { + tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a= 1); + } } else { - tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, CMEQ, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2= ); + } tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0); } } else { if (const_args[2]) { - insn =3D cmp0_insn[cond]; - if (insn) { - tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); - break; + if (is_scalar) { + insn =3D cmp0_scalar_insn[cond]; + if (insn) { + tcg_out_insn_3612(s, insn, vece, a0, a1); + break; + } + } else { + insn =3D cmp0_vec_insn[cond]; + if (insn) { + tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); + break; + } } tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); a2 =3D TCG_VEC_TMP; } - insn =3D cmp_insn[cond]; - if (insn =3D=3D 0) { - TCGArg t; - t =3D a1, a1 =3D a2, a2 =3D t; - cond =3D tcg_swap_cond(cond); - insn =3D cmp_insn[cond]; - tcg_debug_assert(insn !=3D 0); + if (is_scalar) { + insn =3D cmp_scalar_insn[cond]; + if (insn =3D=3D 0) { + TCGArg t; + t =3D a1, a1 =3D a2, a2 =3D t; + cond =3D tcg_swap_cond(cond); + insn =3D cmp_scalar_insn[cond]; + tcg_debug_assert(insn !=3D 0); + } + tcg_out_insn_3611(s, insn, vece, a0, a1, a2); + } else { + insn =3D cmp_vec_insn[cond]; + if (insn =3D=3D 0) { + TCGArg t; + t =3D a1, a1 =3D a2, a2 =3D t; + cond =3D tcg_swap_cond(cond); + insn =3D cmp_vec_insn[cond]; + tcg_debug_assert(insn !=3D 0); + } + tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2); } - tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2); } } break; --=20 2.25.1